From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: Pedro Barbuda <pbarbuda@microsoft.com>,
qemu-arm@nongnu.org,
Pierrick Bouvier <pierrick.bouvier@linaro.org>,
Mohamed Mediouni <mohamed@unpredictable.fr>,
Roman Bolshakov <rbolshakov@ddn.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
Wei Liu <wei.liu@kernel.org>,
Phil Dennis-Jordan <phil@philjordan.eu>,
Peter Maydell <peter.maydell@linaro.org>,
Zhao Liu <zhao1.liu@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH v3 34/37] whpx: i386: add feature to intercept #GP MSR accesses
Date: Wed, 22 Apr 2026 23:42:22 +0200 [thread overview]
Message-ID: <20260422214225.2242-35-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20260422214225.2242-1-mohamed@unpredictable.fr>
It turns out they're not that uncommon, so have
a feature around to log those.
Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
accel/whpx/whpx-common.c | 1 +
include/system/whpx-internal.h | 1 +
target/i386/whpx/whpx-all.c | 183 +++++++++++++++++++++++++++++----
3 files changed, 166 insertions(+), 19 deletions(-)
diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c
index 497c03138e..d846e08714 100644
--- a/accel/whpx/whpx-common.c
+++ b/accel/whpx/whpx-common.c
@@ -555,6 +555,7 @@ static void whpx_accel_instance_init(Object *obj)
/* Value determined at whpx_accel_init */
whpx->hyperv_enlightenments_enabled = false;
whpx->ignore_unknown_msr = true;
+ whpx->intercept_msr_gp = false;
}
static const TypeInfo whpx_accel_type = {
diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h
index 0aae83bd7c..15027a7d52 100644
--- a/include/system/whpx-internal.h
+++ b/include/system/whpx-internal.h
@@ -48,6 +48,7 @@ struct whpx_state {
bool hyperv_enlightenments_enabled;
bool ignore_unknown_msr;
+ bool intercept_msr_gp;
};
extern struct whpx_state whpx_global;
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 830d8acd2b..ea5d1e535c 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -1008,6 +1008,27 @@ static int emulate_instruction(CPUState *cpu, const uint8_t *insn_bytes, size_t
return 0;
}
+static int emulate_msr_instruction(CPUState *cpu,
+ const uint8_t *insn_bytes, size_t insn_len)
+{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+ struct x86_decode decode = { 0 };
+ x86_insn_stream stream = { .bytes = insn_bytes, .len = insn_len };
+
+ whpx_get_registers(cpu, WHPX_LEVEL_FAST_RUNTIME_STATE);
+ decode_instruction_stream(env, &decode, &stream);
+
+ if (decode.cmd != X86_DECODE_CMD_RDMSR
+ && decode.cmd != X86_DECODE_CMD_WRMSR) {
+ return 1;
+ }
+
+ exec_instruction(env, &decode);
+ whpx_set_registers(cpu, WHPX_LEVEL_FAST_RUNTIME_STATE);
+ return 0;
+}
+
static int whpx_handle_mmio(CPUState *cpu, WHV_RUN_VP_EXIT_CONTEXT *exit_ctx)
{
WHV_MEMORY_ACCESS_CONTEXT *ctx = &exit_ctx->MemoryAccess;
@@ -1022,6 +1043,45 @@ static int whpx_handle_mmio(CPUState *cpu, WHV_RUN_VP_EXIT_CONTEXT *exit_ctx)
return 0;
}
+static int whpx_handle_msr_from_gpf(CPUState *cpu)
+{
+ WHV_VP_EXCEPTION_CONTEXT *ctx = &cpu->accel->exit_ctx.VpException;
+ int ret;
+
+ ret = emulate_msr_instruction(cpu, ctx->InstructionBytes, ctx->InstructionByteCount);
+ if (ret == 1) {
+ /* Not an MSR instruction */
+ return 1;
+ }
+
+ return 0;
+}
+
+static void whpx_inject_back_gpf(CPUState *cpu)
+{
+ WHV_VP_EXCEPTION_CONTEXT *ctx = &cpu->accel->exit_ctx.VpException;
+ WHV_REGISTER_VALUE reg = {};
+
+ if (ctx->ExceptionInfo.SoftwareException) {
+ /* TODO */
+ warn_report("Was asked to inject software exception.");
+ return;
+ }
+
+ if (ctx->ExceptionType != EXCP0D_GPF) {
+ warn_report("Was asked to inject exception other than GPF.");
+ return;
+ }
+
+ reg.ExceptionEvent.EventPending = 1;
+ reg.ExceptionEvent.EventType = WHvX64PendingEventException;
+ reg.ExceptionEvent.DeliverErrorCode = ctx->ExceptionInfo.ErrorCodeValid;
+ reg.ExceptionEvent.Vector = ctx->ExceptionType;
+ reg.ExceptionEvent.ErrorCode = ctx->ErrorCode;
+ reg.ExceptionEvent.ExceptionParameter = ctx->ExceptionParameter;
+ whpx_set_reg(cpu, WHvRegisterPendingEvent, reg);
+}
+
static void handle_io(CPUState *env, uint16_t port, void *buffer,
int direction, int size, int count)
{
@@ -1210,13 +1270,54 @@ static target_ulong read_cr(CPUState *cpu, int cr)
return val.Reg64;
}
+static bool whpx_simulate_rdmsr(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+ uint32_t msr = ECX(env);
+ uint64_t val = 0;
+
+ switch (msr) {
+ default:
+ error_report("WHPX: unknown msr 0x%x", msr);
+ x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);
+ return 1;
+ break;
+ }
+
+ RAX(env) = (uint32_t)val;
+ RDX(env) = (uint32_t)(val >> 32);
+
+ return 0;
+}
+
+static bool whpx_simulate_wrmsr(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+ uint32_t msr = ECX(env);
+ uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
+
+ switch (msr) {
+ default:
+ error_report("WHPX: unknown msr 0x%x val %llx", msr, data);
+ x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
static const struct x86_emul_ops whpx_x86_emul_ops = {
.read_segment_descriptor = read_segment_descriptor,
.handle_io = handle_io,
.is_protected_mode = is_protected_mode,
.is_long_mode = is_long_mode,
.is_user_mode = is_user_mode,
- .read_cr = read_cr
+ .read_cr = read_cr,
+ .simulate_rdmsr = whpx_simulate_rdmsr,
+ .simulate_wrmsr = whpx_simulate_wrmsr
};
static void whpx_init_emu(void)
@@ -1356,6 +1457,18 @@ uint64_t whpx_get_supported_msr_feature(uint32_t index)
return 0;
}
+static UINT64 whpx_get_default_exceptions(void)
+{
+ struct whpx_state *whpx = &whpx_global;
+ UINT64 intercepts = 0;
+
+ if (whpx->intercept_msr_gp) {
+ intercepts |= 1UL << WHvX64ExceptionTypeGeneralProtectionFault;
+ }
+
+ return intercepts;
+}
+
/*
* Controls whether we should intercept various exceptions on the guest,
* namely breakpoint/single-step events.
@@ -1378,7 +1491,7 @@ HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions)
prop.ExtendedVmExits.X64MsrExit = 1;
prop.ExtendedVmExits.X64CpuidExit = 1;
- if (exceptions != 0) {
+ if (exceptions != 0 || whpx_get_default_exceptions() != 0) {
prop.ExtendedVmExits.ExceptionExit = 1;
}
@@ -1393,7 +1506,7 @@ HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions)
}
memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));
- prop.ExceptionExitBitmap = exceptions;
+ prop.ExceptionExitBitmap = exceptions | whpx_get_default_exceptions();
hr = whp_dispatch.WHvSetPartitionProperty(
whpx->partition,
@@ -1403,6 +1516,8 @@ HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions)
if (SUCCEEDED(hr)) {
whpx->exception_exit_bitmap = exceptions;
+ } else {
+ error_report("WHPX: Failed to set exception exit bitmap, hr=%08lx", hr);
}
return hr;
@@ -2530,6 +2645,15 @@ int whpx_vcpu_run(CPUState *cpu)
break;
}
case WHvRunVpExitReasonException:
+ if (vcpu->exit_ctx.VpException.ExceptionType ==
+ WHvX64ExceptionTypeGeneralProtectionFault) {
+ if (whpx_handle_msr_from_gpf(cpu)) {
+ whpx_inject_back_gpf(cpu);
+ }
+ ret = 0;
+ break;
+ }
+
whpx_get_registers(cpu, WHPX_LEVEL_FULL_STATE);
if ((vcpu->exit_ctx.VpException.ExceptionType ==
@@ -2818,6 +2942,38 @@ static void whpx_set_unknown_msr(Object *obj, Visitor *v,
}
}
+static void whpx_set_intercept_msr_gp(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ struct whpx_state *whpx = &whpx_global;
+ OnOffAuto mode;
+
+ if (!visit_type_OnOffAuto(v, name, &mode, errp)) {
+ return;
+ }
+
+ switch (mode) {
+ case ON_OFF_AUTO_ON:
+ whpx->intercept_msr_gp = true;
+ break;
+
+ case ON_OFF_AUTO_OFF:
+ whpx->intercept_msr_gp = false;
+ break;
+
+ case ON_OFF_AUTO_AUTO:
+ whpx->intercept_msr_gp = false;
+ break;
+ default:
+ /*
+ * The value was checked in visit_type_OnOffAuto() above. If
+ * we get here, then something is wrong in QEMU.
+ */
+ abort();
+ }
+}
+
void whpx_arch_accel_class_init(ObjectClass *oc)
{
object_class_property_add(oc, "ignore-unknown-msr", "OnOffAuto",
@@ -2825,6 +2981,11 @@ void whpx_arch_accel_class_init(ObjectClass *oc)
NULL, NULL);
object_class_property_set_description(oc, "ignore-unknown-msr",
"Configure unknown MSR behavior");
+ object_class_property_add(oc, "intercept-msr-gp", "OnOffAuto",
+ NULL, whpx_set_intercept_msr_gp,
+ NULL, NULL);
+ object_class_property_set_description(oc, "intercept-msr-gp",
+ "Intercept #GP to log erroring MSR accesses.");
}
int whpx_accel_init(AccelState *as, MachineState *ms)
@@ -3079,22 +3240,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms)
goto error;
}
- /* Register for MSR and CPUID exits */
- memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));
- prop.ExtendedVmExits.X64MsrExit = 1;
- prop.ExtendedVmExits.X64CpuidExit = 1;
-
- hr = whp_dispatch.WHvSetPartitionProperty(
- whpx->partition,
- WHvPartitionPropertyCodeExtendedVmExits,
- &prop,
- sizeof(WHV_PARTITION_PROPERTY));
- if (FAILED(hr)) {
- error_report("WHPX: Failed to enable extended VM exits, hr=%08lx", hr);
- ret = -EINVAL;
- goto error;
- }
-
memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));
prop.X64MsrExitBitmap.UnhandledMsrs = 1;
prop.X64MsrExitBitmap.ApicBaseMsrWrite = 1;
--
2.50.1 (Apple Git-155)
next prev parent reply other threads:[~2026-04-22 21:47 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-22 21:41 [PATCH v3 00/37] WHPX x86 updates for QEMU 11.1 Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 01/37] target/i386: emulate: include name of unhandled instruction Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 02/37] whpx: i386: x2apic emulation Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 03/37] whpx: i386: wire up feature probing Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 04/37] whpx: i386: disable TbFlushHypercalls for emulated LAPIC Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 05/37] whpx: i386: enable x2apic by default for user-mode LAPIC Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 06/37] whpx: i386: reintroduce enlightenments for Windows 10 Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 07/37] whpx: i386: introduce proper cpuid support Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 08/37] whpx: i386: kernel-irqchip=off fixes Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 09/37] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 10/37] whpx: i386: disable kernel-irqchip on Windows 10 when PIC enabled Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 11/37] whpx: i386: IO port fast path cleanup Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 12/37] whpx: i386: disable enlightenments and LAPIC for isapc Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 13/37] whpx: i386: interrupt priority support Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 14/37] hw/intc: apic: disallow APIC reads when disabled Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 15/37] whpx: i386: fix CPUID[1:EDX].APIC reporting Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 16/37] whpx: i386: set apicbase value only on success Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 17/37] whpx: i386: unknown MSR configurability Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 18/37] whpx: i386: enable GuestIdleReg enlightenment Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 19/37] whpx: i386: tighten APIC base validity check Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 20/37] whpx: i386: ignore vpassist when kernel-irqchip=off Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 21/37] target: i386: HLT type that ignores EFLAGS.IF Mohamed Mediouni
2026-04-30 13:43 ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 22/37] whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip Mohamed Mediouni
2026-04-30 13:21 ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 23/37] whpx: i386: some x2APIC awareness Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 24/37] whpx: i386: set WHvX64RegisterInitialApicId Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 25/37] whpx: i386: Pause VM on fatal exception to be able to inspect state Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 26/37] target/i386: emulate: use exception_payload for fault address Mohamed Mediouni
2026-04-30 13:24 ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 27/37] target/i386: make xsave_buf present unconditionally Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 28/37] target/i386: add de/compaction to xsave_helper Mohamed Mediouni
2026-04-30 13:31 ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 29/37] whpx: xsave support Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 30/37] whpx: i386: set APIC ID only when APIC present Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 31/37] whpx: i386: update migration blocker message Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 32/37] whpx: i386: don't increment eip on MSR access raising GPF Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 33/37] target/i386: emulate, hvf: rdmsr/wrmsr GPF handling Mohamed Mediouni
2026-04-22 21:42 ` Mohamed Mediouni [this message]
2026-04-22 21:42 ` [PATCH v3 35/37] whpx: i386: nested virt settings Mohamed Mediouni
2026-04-30 13:44 ` Paolo Bonzini
2026-04-30 17:52 ` Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 36/37] whpx: i386: add SeparateSecurityDomain flag and make default Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 37/37] whpx: i386: documentation update Mohamed Mediouni
2026-04-23 11:10 ` [PATCH v3 00/37] WHPX x86 updates for QEMU 11.1 Paolo Bonzini
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