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From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: Pedro Barbuda <pbarbuda@microsoft.com>,
	qemu-arm@nongnu.org,
	Pierrick Bouvier <pierrick.bouvier@linaro.org>,
	Mohamed Mediouni <mohamed@unpredictable.fr>,
	Roman Bolshakov <rbolshakov@ddn.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Wei Liu <wei.liu@kernel.org>,
	Phil Dennis-Jordan <phil@philjordan.eu>,
	Peter Maydell <peter.maydell@linaro.org>,
	Zhao Liu <zhao1.liu@intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH v3 07/37] whpx: i386: introduce proper cpuid support
Date: Wed, 22 Apr 2026 23:41:55 +0200	[thread overview]
Message-ID: <20260422214225.2242-8-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20260422214225.2242-1-mohamed@unpredictable.fr>

Unlike the implementation in QEMU 10.2, this one works.

It's not optimal though as it doesn't use the Hyper-V support for this.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
 target/i386/whpx/whpx-all.c        | 136 +++++++++++++++++++++++++----
 target/i386/whpx/whpx-cpu-legacy.c |  15 +---
 2 files changed, 122 insertions(+), 29 deletions(-)

diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index f9f330c038..73e351d895 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -2168,18 +2168,11 @@ int whpx_vcpu_run(CPUState *cpu)
                 vcpu->exit_ctx.VpContext.Rip +
                 vcpu->exit_ctx.VpContext.InstructionLength;
 
-            if (whpx_is_legacy_os()) {
-                reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
-                reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;
-                reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
-                reg_values[4].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
-            } else {
-                cpu_x86_cpuid(env, vcpu->exit_ctx.CpuidAccess.Rax,
-                    vcpu->exit_ctx.CpuidAccess.Rcx,
-                    (UINT32 *)&reg_values[1].Reg32,
-                    (UINT32 *)&reg_values[4].Reg32, (UINT32 *)&reg_values[2].Reg32,
-                    (UINT32 *)&reg_values[3].Reg32);
-            }
+             cpu_x86_cpuid(env, vcpu->exit_ctx.CpuidAccess.Rax,
+                vcpu->exit_ctx.CpuidAccess.Rcx,
+                (UINT32 *)&reg_values[1].Reg32,
+                (UINT32 *)&reg_values[4].Reg32, (UINT32 *)&reg_values[2].Reg32,
+                (UINT32 *)&reg_values[3].Reg32);
 
             if (!whpx->hyperv_enlightenments_enabled) {
                 switch (vcpu->exit_ctx.CpuidAccess.Rax) {
@@ -2220,6 +2213,68 @@ int whpx_vcpu_run(CPUState *cpu)
                     }
                     break;
                 }
+            } else {
+                switch (vcpu->exit_ctx.CpuidAccess.Rax) {
+                case 0x40000000:
+                case 0x40000001:
+                case 0x40000010:
+                    reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
+                    reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;
+                    reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
+                    reg_values[4].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
+                    break;
+                }
+            }
+
+            if (vcpu->exit_ctx.CpuidAccess.Rax == 0x1) {
+                if (cpu_has_x2apic_feature(env)) {
+                    reg_values[2].Reg64 |= CPUID_EXT_X2APIC;
+                } else {
+                    reg_values[2].Reg32 &= ~CPUID_EXT_X2APIC;
+                }
+            }
+
+            /* Dynamic depending on XCR0 and XSS, so query DefaultResult */
+            if (vcpu->exit_ctx.CpuidAccess.Rax == 0x07
+                && vcpu->exit_ctx.CpuidAccess.Rcx == 0) {
+                if (vcpu->exit_ctx.CpuidAccess.DefaultResultRdx
+                    & CPUID_7_0_EDX_CET_IBT) {
+                    reg_values[3].Reg32 |= CPUID_7_0_EDX_CET_IBT;
+                } else {
+                    reg_values[3].Reg32 &= ~CPUID_7_0_EDX_CET_IBT;
+                }
+
+                if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx
+                    & CPUID_7_0_ECX_CET_SHSTK) {
+                    reg_values[2].Reg32 |= CPUID_7_0_ECX_CET_SHSTK;
+                } else {
+                    reg_values[2].Reg32 &= ~CPUID_7_0_ECX_CET_SHSTK;
+                }
+
+                if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx
+                    & CPUID_7_0_ECX_OSPKE) {
+                    reg_values[2].Reg32 |= CPUID_7_0_ECX_OSPKE;
+                } else {
+                    reg_values[2].Reg32 &= ~CPUID_7_0_ECX_OSPKE;
+                }
+            }
+
+            /* CPUID[0xD,{1,2}].EBX are dynamic depending on guest features. */
+            if (vcpu->exit_ctx.CpuidAccess.Rax == 0xd) {
+                if (vcpu->exit_ctx.CpuidAccess.Rcx == 1
+                    || vcpu->exit_ctx.CpuidAccess.Rcx == 2) {
+                    reg_values[4].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
+                }
+            }
+
+            /* OSXSAVE is dynamic. Do this instead of syncing CR4 */
+            if (vcpu->exit_ctx.CpuidAccess.Rax == 1) {
+                if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx
+                    & CPUID_EXT_OSXSAVE) {
+                    reg_values[2].Reg32 |= CPUID_EXT_OSXSAVE;
+                } else {
+                    reg_values[2].Reg32 &= ~CPUID_EXT_OSXSAVE;
+                }
             }
 
             hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
@@ -2409,6 +2464,45 @@ error:
     return ret;
 }
 
+static void whpx_cpu_xsave_init(void)
+{
+    static bool first = true;
+    int i;
+
+    if (!first) {
+        return;
+    }
+    first = false;
+
+    /* x87 and SSE states are in the legacy region of the XSAVE area. */
+    x86_ext_save_areas[XSTATE_FP_BIT].offset = 0;
+    x86_ext_save_areas[XSTATE_SSE_BIT].offset = 0;
+
+    for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) {
+        ExtSaveArea *esa = &x86_ext_save_areas[i];
+
+        if (esa->size) {
+            int sz = whpx_get_supported_cpuid(0xd, i, R_EAX);
+            if (sz != 0) {
+                assert(esa->size == sz);
+                esa->offset = whpx_get_supported_cpuid(0xd, i, R_EBX);
+            }
+        }
+    }
+}
+
+static void whpx_cpu_max_instance_init(X86CPU *cpu)
+{
+    CPUX86State *env = &cpu->env;
+
+    env->cpuid_min_level =
+        whpx_get_supported_cpuid(0x0, 0, R_EAX);
+    env->cpuid_min_xlevel =
+        whpx_get_supported_cpuid(0x80000000, 0, R_EAX);
+    env->cpuid_min_xlevel2 =
+        whpx_get_supported_cpuid(0xC0000000, 0, R_EAX);
+}
+
 static PropValue whpx_default_props[] = {
     { "x2apic", "on" },
     { NULL, NULL },
@@ -2418,9 +2512,18 @@ static PropValue whpx_default_props[] = {
 void whpx_cpu_instance_init(CPUState *cs)
 {
     X86CPU *cpu = X86_CPU(cs);
+    X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
 
     host_cpu_instance_init(cpu);
     x86_cpu_apply_props(cpu, whpx_default_props);
+
+    if (xcc->max_features) {
+        whpx_cpu_max_instance_init(cpu);
+    }
+
+    if (whpx_has_xsave()) {
+        whpx_cpu_xsave_init();
+    }
 }
 
 /*
@@ -2438,8 +2541,11 @@ int whpx_accel_init(AccelState *as, MachineState *ms)
     WHV_CAPABILITY_FEATURES features = {0};
     WHV_PROCESSOR_FEATURES_BANKS processor_features;
     WHV_PROCESSOR_PERFMON_FEATURES perfmon_features;
-    UINT32 cpuidExitList[] = {1};
-    UINT32 cpuidExitList_nohyperv[] = {1, 0x40000000, 0x40000001, 0x40000010};
+
+    UINT32 cpuidExitList[] = {0x0, 0x1, 0x6, 0x7, 0xb, 0xd, 0x14, 0x24, 0x29, 0x1E,
+        0x40000000, 0x40000001, 0x40000010, 0x80000000, 0x80000001,
+        0x80000002, 0x80000003, 0x80000004, 0x80000007, 0x80000008,
+        0x8000000A, 0x80000021, 0x80000022, 0xC0000000, 0xC0000001};
 
     whpx = &whpx_global;
 
@@ -2698,7 +2804,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)
     hr = whp_dispatch.WHvSetPartitionProperty(
         whpx->partition,
         WHvPartitionPropertyCodeCpuidExitList,
-        whpx->hyperv_enlightenments_enabled ? cpuidExitList : cpuidExitList_nohyperv,
+        cpuidExitList,
         RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32));
 
     if (FAILED(hr)) {
diff --git a/target/i386/whpx/whpx-cpu-legacy.c b/target/i386/whpx/whpx-cpu-legacy.c
index 477429b460..d341e6f4fd 100644
--- a/target/i386/whpx/whpx-cpu-legacy.c
+++ b/target/i386/whpx/whpx-cpu-legacy.c
@@ -4,20 +4,7 @@
  *  Copyright (c) 2003 Fabrice Bellard
  *  Copyright (c) 2017 Google Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- * cpuid
+ * SPDX-License-Identifier: LGPL-2.1-or-later
  */
 
 #include "qemu/osdep.h"
-- 
2.50.1 (Apple Git-155)



  parent reply	other threads:[~2026-04-22 21:43 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-22 21:41 [PATCH v3 00/37] WHPX x86 updates for QEMU 11.1 Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 01/37] target/i386: emulate: include name of unhandled instruction Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 02/37] whpx: i386: x2apic emulation Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 03/37] whpx: i386: wire up feature probing Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 04/37] whpx: i386: disable TbFlushHypercalls for emulated LAPIC Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 05/37] whpx: i386: enable x2apic by default for user-mode LAPIC Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 06/37] whpx: i386: reintroduce enlightenments for Windows 10 Mohamed Mediouni
2026-04-22 21:41 ` Mohamed Mediouni [this message]
2026-04-22 21:41 ` [PATCH v3 08/37] whpx: i386: kernel-irqchip=off fixes Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 09/37] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 10/37] whpx: i386: disable kernel-irqchip on Windows 10 when PIC enabled Mohamed Mediouni
2026-04-22 21:41 ` [PATCH v3 11/37] whpx: i386: IO port fast path cleanup Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 12/37] whpx: i386: disable enlightenments and LAPIC for isapc Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 13/37] whpx: i386: interrupt priority support Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 14/37] hw/intc: apic: disallow APIC reads when disabled Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 15/37] whpx: i386: fix CPUID[1:EDX].APIC reporting Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 16/37] whpx: i386: set apicbase value only on success Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 17/37] whpx: i386: unknown MSR configurability Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 18/37] whpx: i386: enable GuestIdleReg enlightenment Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 19/37] whpx: i386: tighten APIC base validity check Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 20/37] whpx: i386: ignore vpassist when kernel-irqchip=off Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 21/37] target: i386: HLT type that ignores EFLAGS.IF Mohamed Mediouni
2026-04-30 13:43   ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 22/37] whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip Mohamed Mediouni
2026-04-30 13:21   ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 23/37] whpx: i386: some x2APIC awareness Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 24/37] whpx: i386: set WHvX64RegisterInitialApicId Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 25/37] whpx: i386: Pause VM on fatal exception to be able to inspect state Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 26/37] target/i386: emulate: use exception_payload for fault address Mohamed Mediouni
2026-04-30 13:24   ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 27/37] target/i386: make xsave_buf present unconditionally Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 28/37] target/i386: add de/compaction to xsave_helper Mohamed Mediouni
2026-04-30 13:31   ` Paolo Bonzini
2026-04-22 21:42 ` [PATCH v3 29/37] whpx: xsave support Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 30/37] whpx: i386: set APIC ID only when APIC present Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 31/37] whpx: i386: update migration blocker message Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 32/37] whpx: i386: don't increment eip on MSR access raising GPF Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 33/37] target/i386: emulate, hvf: rdmsr/wrmsr GPF handling Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 34/37] whpx: i386: add feature to intercept #GP MSR accesses Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 35/37] whpx: i386: nested virt settings Mohamed Mediouni
2026-04-30 13:44   ` Paolo Bonzini
2026-04-30 17:52     ` Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 36/37] whpx: i386: add SeparateSecurityDomain flag and make default Mohamed Mediouni
2026-04-22 21:42 ` [PATCH v3 37/37] whpx: i386: documentation update Mohamed Mediouni
2026-04-23 11:10 ` [PATCH v3 00/37] WHPX x86 updates for QEMU 11.1 Paolo Bonzini

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