From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "peterx@redhat.com" <peterx@redhat.com>,
"philmd@linaro.org" <philmd@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Kane Chen" <kane_chen@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Laurent Vivier" <laurent@vivier.eu>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
"Cornelia Huck" <cohuck@redhat.com>,
"Eric Farman" <farman@linux.ibm.com>,
"Matthew Rosato" <mjrosato@linux.ibm.com>,
"Halil Pasic" <pasic@linux.ibm.com>,
"Christian Borntraeger" <borntraeger@linux.ibm.com>,
"Ilya Leoshkevich" <iii@linux.ibm.com>,
"David Hildenbrand" <david@kernel.org>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:sPAPR pseries" <qemu-ppc@nongnu.org>,
"open list:S390 general arch..." <qemu-s390x@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
Troy Lee <troy_lee@aspeedtech.com>,
"farosas@suse.de" <farosas@suse.de>,
"flwu@google.com" <flwu@google.com>,
"nabihestefan@google.com" <nabihestefan@google.com>
Subject: [PATCH v5 12/18] hw/usb/hcd-ehci: Implement 64-bit qTD descriptor addressing
Date: Fri, 24 Apr 2026 08:05:25 +0000 [thread overview]
Message-ID: <20260424080508.53992-13-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260424080508.53992-1-jamin_lin@aspeedtech.com>
EHCI supports 64-bit addressing when the 64-bit Addressing Capability
bit in HCCPARAMS is set. In that mode, the CTRLDSSEGMENT register
provides the upper 32 bits that are concatenated with 32-bit link
pointer values to form 64-bit control data structure addresses
(EHCI 1.0, section 2.3.5 and Appendix B).
qTD link pointers (current_qtd/next_qtd/altnext_qtd and qTD.next)
are stored as 32-bit values in the data structures and must be
expanded to full 64-bit descriptor addresses when 64-bit mode is
enabled. Update the qTD traversal paths to use ehci_get_desc_addr()
when following link pointers.
Appendix B also defines high dword fields for qTD buffer pointers.
Add bufptr_hi[5] to EHCIqtd and extend qTD fetch and QH overlay
handling to load and propagate the high buffer pointer fields.
When 64-bit capability is disabled, descriptor and buffer addresses
remain 32-bit and existing behaviour is unchanged.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/usb/hcd-ehci.h | 1 +
hw/usb/hcd-ehci.c | 19 ++++++++++++-------
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 3428839ec6..fc66aacd9f 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -139,6 +139,7 @@ typedef struct EHCIqtd {
uint32_t bufptr[5]; /* Standard buffer pointer */
#define QTD_BUFPTR_MASK 0xfffff000
#define QTD_BUFPTR_SH 12
+ uint32_t bufptr_hi[5];
} EHCIqtd;
/* QH overlay: altnext_qtd, token, bufptr[5], bufptr_hi[5] */
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 5ffd4c9885..e82e0f625c 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -472,7 +472,8 @@ static bool ehci_verify_qtd(EHCIPacket *p, EHCIqtd *qtd)
(p->qtd.next != qtd->next)) ||
(!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd->altnext)) ||
p->qtd.token != qtd->token ||
- p->qtd.bufptr[0] != qtd->bufptr[0]) {
+ p->qtd.bufptr[0] != qtd->bufptr[0] ||
+ p->qtd.bufptr_hi[0] != qtd->bufptr_hi[0]) {
return false;
} else {
return true;
@@ -1200,6 +1201,7 @@ static int ehci_qh_do_overlay(EHCIQueue *q)
for (i = 0; i < 5; i++) {
q->qh.bufptr[i] = p->qtd.bufptr[i];
+ q->qh.bufptr_hi[i] = p->qtd.bufptr_hi[i];
}
if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
@@ -1233,7 +1235,8 @@ static int ehci_init_transfer(EHCIPacket *p)
return -1;
}
- page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
+ page = ehci_get_buf_addr(p->queue->ehci, p->qtd.bufptr_hi[cpage],
+ p->qtd.bufptr[cpage], QTD_BUFPTR_MASK);
page += offset;
plen = bytes;
if (plen > 4096 - offset) {
@@ -1727,7 +1730,7 @@ static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
} else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
(NLPTR_TBIT(q->qh.current_qtd) == 0) &&
(q->qh.current_qtd != 0)) {
- q->qtdaddr = q->qh.current_qtd;
+ q->qtdaddr = ehci_get_desc_addr(ehci, q->qh.current_qtd);
ehci_set_state(ehci, async, EST_FETCHQTD);
} else {
@@ -1805,14 +1808,14 @@ static int ehci_state_advqueue(EHCIQueue *q)
*/
if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
(NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
- q->qtdaddr = q->qh.altnext_qtd;
+ q->qtdaddr = ehci_get_desc_addr(q->ehci, q->qh.altnext_qtd);
ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
/*
* next qTD is valid
*/
} else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
- q->qtdaddr = q->qh.next_qtd;
+ q->qtdaddr = ehci_get_desc_addr(q->ehci, q->qh.next_qtd);
ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
/*
@@ -1841,7 +1844,9 @@ static int ehci_state_fetchqtd(EHCIQueue *q)
if (get_dwords(q->ehci, addr + 0, &qtd.next, 1) < 0 ||
get_dwords(q->ehci, addr + 4, &qtd.altnext, 1) < 0 ||
get_dwords(q->ehci, addr + 12, qtd.bufptr,
- ARRAY_SIZE(qtd.bufptr)) < 0) {
+ ARRAY_SIZE(qtd.bufptr)) < 0 ||
+ get_dwords(q->ehci, addr + 32, qtd.bufptr_hi,
+ ARRAY_SIZE(qtd.bufptr_hi)) < 0) {
return 0;
}
ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
@@ -1922,7 +1927,7 @@ static int ehci_fill_queue(EHCIPacket *p)
if (NLPTR_TBIT(qtd.next) != 0) {
break;
}
- qtdaddr = qtd.next;
+ qtdaddr = ehci_get_desc_addr(q->ehci, qtd.next);
/*
* Detect circular td lists, Windows creates these, counting on the
* active bit going low after execution to make the queue stop.
--
2.43.0
next prev parent reply other threads:[~2026-04-24 8:07 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-24 8:05 [PATCH v5 00/18] hw/usb/ehci: Add 64-bit descriptor addressing support Jamin Lin
2026-04-24 8:05 ` [PATCH v5 01/18] tests/functional/arm/test_aspeed_ast2600_sdk: Add USB EHCI test for AST2600 SDK Jamin Lin
2026-04-24 8:05 ` [PATCH v5 02/18] hw/usb/hcd-ehci: Remove unused EHCIfstn structure and dead code Jamin Lin
2026-04-24 8:05 ` [PATCH v5 03/18] hw/usb/hcd-ehci.h: Fix coding style issues reported by checkpatch Jamin Lin
2026-04-24 8:05 ` [PATCH v5 04/18] hw/usb/hcd-ehci.c: " Jamin Lin
2026-04-24 8:05 ` [PATCH v5 05/18] hw/usb/hcd-ehci.c: Replace fprintf(stderr, ...) with qemu_log_mask(LOG_GUEST_ERROR) Jamin Lin
2026-04-24 8:05 ` [PATCH v5 06/18] hw/usb/hcd-ehci: Replace DPRINTF debug logs with trace events Jamin Lin
2026-04-24 8:05 ` [PATCH v5 07/18] hw/usb/hcd-ehci: Introduce common properties macro for sysbus and pci Jamin Lin
2026-04-24 15:23 ` Philippe Mathieu-Daudé
2026-04-24 8:05 ` [PATCH v5 08/18] hw/core: Add 11.0 machine compatibility properties Jamin Lin
2026-04-24 8:05 ` [PATCH v5 09/18] hw/usb/hcd-ehci: Change descriptor addresses to 64-bit with migration compatibility Jamin Lin
2026-04-24 11:35 ` Peter Xu
2026-05-03 20:20 ` Cédric Le Goater
2026-05-04 2:25 ` Jamin Lin
2026-04-24 8:05 ` [PATCH v5 10/18] hw/usb/hcd-ehci: Add property to advertise 64-bit addressing capability Jamin Lin
2026-05-03 20:18 ` Cédric Le Goater
2026-05-04 2:10 ` Jamin Lin
2026-04-24 8:05 ` [PATCH v5 11/18] hw/usb/hcd-ehci: Implement 64-bit QH descriptor addressing Jamin Lin
2026-04-24 8:05 ` Jamin Lin [this message]
2026-04-24 8:05 ` [PATCH v5 13/18] hw/usb/hcd-ehci: Implement 64-bit iTD " Jamin Lin
2026-04-24 8:05 ` [PATCH v5 14/18] hw/usb/hcd-ehci: Implement 64-bit siTD " Jamin Lin
2026-04-24 8:05 ` [PATCH v5 15/18] hw/usb/hcd-ehci: Add ctrldssegment-default property Jamin Lin
2026-04-24 8:05 ` [PATCH v5 16/18] hw/arm/aspeed_ast27x0: Set EHCI ctrldssegment-default Jamin Lin
2026-05-03 20:18 ` Cédric Le Goater
2026-05-04 2:19 ` Jamin Lin
2026-04-24 8:05 ` [PATCH v5 17/18] hw/arm/aspeed_ast27x0: Enable 64-bit EHCI DMA addressing Jamin Lin
2026-04-24 8:05 ` [PATCH v5 18/18] tests/functional/aarch64/test_aspeed_ast2700: Add USB EHCI test for AST2700 A1/A2 Jamin Lin
2026-05-03 20:23 ` [PATCH v5 00/18] hw/usb/ehci: Add 64-bit descriptor addressing support Cédric Le Goater
2026-05-04 2:48 ` Jamin Lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260424080508.53992-13-jamin_lin@aspeedtech.com \
--to=jamin_lin@aspeedtech.com \
--cc=andrew@codeconstruct.com.au \
--cc=borntraeger@linux.ibm.com \
--cc=clg@kaod.org \
--cc=cohuck@redhat.com \
--cc=david@kernel.org \
--cc=farman@linux.ibm.com \
--cc=farosas@suse.de \
--cc=flwu@google.com \
--cc=harshpb@linux.ibm.com \
--cc=iii@linux.ibm.com \
--cc=joel@jms.id.au \
--cc=kane_chen@aspeedtech.com \
--cc=laurent@vivier.eu \
--cc=leetroy@gmail.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=mjrosato@linux.ibm.com \
--cc=mst@redhat.com \
--cc=nabihestefan@google.com \
--cc=npiggin@gmail.com \
--cc=pasic@linux.ibm.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=peterx@redhat.com \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=steven_lee@aspeedtech.com \
--cc=troy_lee@aspeedtech.com \
--cc=wangyanan55@huawei.com \
--cc=zhao1.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.