From: 54weasels <54weasels@gmail.com>
To: qemu-devel@nongnu.org
Cc: laurent@vivier.eu, thuth@redhat.com, 54weasels <54weasels@gmail.com>
Subject: [PATCH 1/7] target/m68k: Implement Physical Bus Error exception handling
Date: Sat, 2 May 2026 18:57:50 -0700 [thread overview]
Message-ID: <20260503015756.99176-2-54weasels@gmail.com> (raw)
In-Reply-To: <20260503015756.99176-1-54weasels@gmail.com>
The M68020 natively maps hardware Bus Error (BERR) timeouts into a Long Bus Cycle Fault (Format 0xB). This commit adds the memory exception routing to natively synthesize these EXCP_ACCESS cycle faults. It also implements the double-fault / watchdog reset behavior required for Sun-3 hardware diagnostics, properly handles FSAVE/FRESTORE for 68881 FPU stubs, and properly constructs the 84-byte internal bus fault frame.
Signed-off-by: 54weasels <54weasels@gmail.com>
---
target/m68k/cpu.c | 5 +-
target/m68k/cpu.h | 18 +++-
target/m68k/helper.c | 130 ++++++++++++++++++++++++++++-
target/m68k/op_helper.c | 176 ++++++++++++++++++++++++++--------------
target/m68k/translate.c | 31 +++++--
5 files changed, 283 insertions(+), 77 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index d849a4a90f..af375f0bce 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QEMU Motorola 68k CPU
*
@@ -51,8 +52,8 @@ static TCGTBCPUState m68k_get_tb_cpu_state(CPUState *cs)
flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
if (env->sr & SR_S) {
flags |= TB_FLAGS_MSR_S;
- flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
- flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
+ flags |= (env->sfc << TB_FLAGS_SFC_S_BIT) & TB_FLAGS_SFC_S;
+ flags |= (env->dfc << TB_FLAGS_DFC_S_BIT) & TB_FLAGS_DFC_S;
}
if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
flags |= TB_FLAGS_TRACE;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 7911ab9de3..426ef6a6e1 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -149,10 +149,18 @@ typedef struct CPUArchState {
int pending_vector;
int pending_level;
+ bool nmi_pending;
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
+ /* Custom MMU intercept logic, if any (e.g. for Sun-3) */
+ void *custom_mmu_opaque;
+ int (*custom_mmu_get_physical_address)(void *env, hwaddr *physical,
+ int *prot, vaddr address,
+ int access_type,
+ hwaddr *page_size);
+
/* Fields from here on are preserved across CPU reset. */
uint64_t features;
} CPUM68KState;
@@ -601,12 +609,14 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
#define TB_FLAGS_MSR_S_BIT 13
#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT)
#define TB_FLAGS_SFC_S_BIT 14
-#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
-#define TB_FLAGS_DFC_S_BIT 15
-#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
-#define TB_FLAGS_TRACE 16
+#define TB_FLAGS_SFC_S (7 << TB_FLAGS_SFC_S_BIT) /* 3 Bits reserved */
+#define TB_FLAGS_DFC_S_BIT 17
+#define TB_FLAGS_DFC_S (7 << TB_FLAGS_DFC_S_BIT) /* 3 Bits reserved */
+#define TB_FLAGS_TRACE 20
#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)
+#define MMU_MOVES_FC_BASE 2 /* mmu_idx 2-9 correspond to FC 0-7 */
+
void dump_mmu(CPUM68KState *env);
#endif
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 9bab184389..997c2616f4 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -28,6 +28,7 @@
#include "system/memory.h"
#include "gdbstub/helpers.h"
#include "fpu/softfloat.h"
+#include "qemu/log.h"
#include "qemu/qemu-print.h"
#define SIGNBIT (1u << 31)
@@ -280,8 +281,10 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
return;
}
break;
- /* Unimplemented Registers */
+ /* Dummy implementation for CAAR */
case M68K_CR_CAAR:
+ return;
+ /* Unimplemented Registers */
case M68K_CR_PCR:
case M68K_CR_BUSCR:
cpu_abort(env_cpu(env),
@@ -384,8 +387,10 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
return env->mmu.ttr[M68K_DTTR1];
}
break;
- /* Unimplemented Registers */
+ /* Dummy implementation for CAAR */
case M68K_CR_CAAR:
+ return 0;
+ /* Unimplemented Registers */
case M68K_CR_PCR:
case M68K_CR_BUSCR:
cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
@@ -915,6 +920,21 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int access_type;
target_ulong page_size;
+ access_type = ACCESS_DATA | ACCESS_DEBUG;
+ if (env->sr & SR_S) {
+ access_type |= ACCESS_SUPER;
+ }
+
+ if (env->custom_mmu_get_physical_address) {
+ hwaddr custom_page_size;
+ if (env->custom_mmu_get_physical_address(env, &phys_addr, &prot, addr,
+ access_type,
+ &custom_page_size) == 0) {
+ return phys_addr;
+ }
+ return -1;
+ }
+
if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
/* MMU disabled */
return addr;
@@ -944,6 +964,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
CPUState *cs = CPU(cpu);
CPUM68KState *env = &cpu->env;
+ if (level == 7 && env->pending_level != 7) {
+ env->nmi_pending = true;
+ } else if (level != 7) {
+ env->nmi_pending = false;
+ }
+
env->pending_level = level;
env->pending_vector = vector;
if (level) {
@@ -964,6 +990,106 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
int ret;
target_ulong page_size;
+ if (qemu_access_type == MMU_INST_FETCH) {
+ access_type = ACCESS_CODE;
+ } else {
+ access_type = ACCESS_DATA;
+ if (qemu_access_type == MMU_DATA_STORE) {
+ access_type |= ACCESS_STORE;
+ }
+ }
+
+ /* Decode explicit Function Codes from moves instructions */
+ if (mmu_idx >= MMU_MOVES_FC_BASE) {
+ uint8_t fc = mmu_idx - MMU_MOVES_FC_BASE;
+ access_type |= (fc << 8); /* Pack explicit FC into access type */
+ if (fc != 1 && fc != 2) {
+ access_type |= ACCESS_SUPER;
+ }
+ } else {
+ /* Standard memory accesses map logically to normal M68K FCs */
+ if (mmu_idx == MMU_KERNEL_IDX) {
+ access_type |= ACCESS_SUPER;
+ access_type |= ((qemu_access_type == MMU_INST_FETCH ? 6 : 5) << 8);
+ } else {
+ access_type |= ((qemu_access_type == MMU_INST_FETCH ? 2 : 1) << 8);
+ }
+ }
+
+ if (env->custom_mmu_get_physical_address) {
+ hwaddr custom_page_size;
+
+ /* Delegate translation to external board-specific MMU if registered */
+ ret = env->custom_mmu_get_physical_address(env, &physical, &prot,
+ address, access_type,
+ &custom_page_size);
+
+ if (likely(ret == 0)) {
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot,
+ mmu_idx, custom_page_size);
+ return true;
+ }
+
+ if (probe) {
+ return false;
+ }
+
+ /* page fault */
+ cs->exception_index = EXCP_ACCESS;
+ env->mmu.ar = address;
+
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ env->mmu.ssw = M68K_ATC_040;
+ switch (size) {
+ case 1:
+ env->mmu.ssw |= M68K_BA_SIZE_BYTE;
+ break;
+ case 2:
+ env->mmu.ssw |= M68K_BA_SIZE_WORD;
+ break;
+ case 4:
+ env->mmu.ssw |= M68K_BA_SIZE_LONG;
+ break;
+ }
+ env->mmu.ssw |= M68K_TM_040_DATA;
+ } else {
+ /* M68020/030 Special Status Word (SSW) */
+ uint16_t ssw = 0x0100; /* DF - Data Fault */
+ switch (size) {
+ case 1:
+ ssw |= 0x0010;
+ break;
+ case 2:
+ ssw |= 0x0020;
+ break;
+ case 3:
+ ssw |= 0x0030;
+ break;
+ case 4:
+ ssw |= 0x0000;
+ break;
+ }
+ if (qemu_access_type != MMU_DATA_STORE) {
+ ssw |= 0x0040; /* RW - Read */
+ }
+ /* Function Code */
+ uint8_t fc;
+ if (mmu_idx >= MMU_MOVES_FC_BASE) {
+ fc = mmu_idx - MMU_MOVES_FC_BASE;
+ } else {
+ if (mmu_idx == MMU_KERNEL_IDX) {
+ fc = (qemu_access_type == MMU_INST_FETCH) ? 6 : 5;
+ } else {
+ fc = (qemu_access_type == MMU_INST_FETCH) ? 2 : 1;
+ }
+ }
+ ssw |= (fc & 7);
+ env->mmu.ssw = ssw;
+ }
+ cpu_loop_exit_restore(cs, retaddr);
+ }
+
if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
/* MMU disabled */
tlb_set_page(cs, address & TARGET_PAGE_MASK,
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 8148a8852e..84d5270767 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* M68K helper routines
*
@@ -25,6 +26,7 @@
#include "qemu/plugin.h"
#if !defined(CONFIG_USER_ONLY)
+#include "system/runstate.h"
static void cf_rte(CPUM68KState *env)
{
@@ -73,6 +75,12 @@ throwaway:
case 7:
sp += 52;
break;
+ case 0xa: /* Short Bus Cycle Fault (Format 0xA) */
+ sp += 32 - 8; /* 32 bytes total - 8 bytes header = 24 bytes */
+ break;
+ case 0xb: /* Long Bus Cycle Fault (Format 0xB) */
+ sp += 92 - 8; /* 92 bytes total - 8 bytes header = 84 bytes */
+ break;
}
}
env->aregs[7] = sp;
@@ -342,56 +350,80 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
switch (cs->exception_index) {
case EXCP_ACCESS:
if (env->mmu.fault) {
- cpu_abort(cs, "DOUBLE MMU FAULT\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "M68K: Double MMU Fault. Halting CPU and requesting reset.\n");
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ cs->halted = 1;
+ cs->exception_index = EXCP_HLT;
+ cpu_loop_exit(cs);
}
env->mmu.fault = true;
- /* push data 3 */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* push data 2 */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* push data 1 */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 1 / push data 0 */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 1 address */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 2 data */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 2 address */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 3 data */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 3 address */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
- /* fault address */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
- /* write back 1 status */
- sp -= 2;
- cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 2 status */
- sp -= 2;
- cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* write back 3 status */
- sp -= 2;
- cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
- /* special status word */
- sp -= 2;
- cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
- /* effective address */
- sp -= 4;
- cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
-
- do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);
+
+ if (m68k_feature(env, M68K_FEATURE_M68040)) {
+ /* push data 3 */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* push data 2 */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* push data 1 */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 1 / push data 0 */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 1 address */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 2 data */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 2 address */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 3 data */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 3 address */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+ /* fault address */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+ /* write back 1 status */
+ sp -= 2;
+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 2 status */
+ sp -= 2;
+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* write back 3 status */
+ sp -= 2;
+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ /* special status word */
+ sp -= 2;
+ cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
+ /* effective address */
+ sp -= 4;
+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+
+ do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);
+ } else {
+ /* M68020 Long Bus Cycle Fault (Format 0xB) */
+ /*
+ * 84 bytes of internal state are pushed before the generic
+ * 8-byte header
+ */
+ sp -= 84;
+ for (int i = 0; i < 84; i += 4) {
+ cpu_stl_be_mmuidx_ra(env, sp + i, 0, MMU_KERNEL_IDX, 0);
+ }
+ /* Offset 0x02 from internal frame: SSW */
+ cpu_stw_be_mmuidx_ra(env, sp + 2, env->mmu.ssw, MMU_KERNEL_IDX, 0);
+ /* Offset 0x08 from internal frame: Fault Address */
+ cpu_stl_be_mmuidx_ra(env, sp + 8, env->mmu.ar, MMU_KERNEL_IDX, 0);
+
+ do_stack_frame(env, &sp, 0xb, oldsr, 0, env->pc);
+ }
env->mmu.fault = false;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
qemu_log(" "
@@ -437,7 +469,9 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
env->aregs[7] = sp;
/* Jump to vector. */
+ env->mmu.fault = true;
env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
+ env->mmu.fault = false;
do_plugin_vcpu_interrupt_cb(cs, last_pc);
}
@@ -509,26 +543,46 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
if (access_type != MMU_DATA_STORE) {
env->mmu.ssw |= M68K_RW_040;
}
-
- env->mmu.ar = addr;
-
- cs->exception_index = EXCP_ACCESS;
- cpu_loop_exit(cs);
+ } else if (m68k_feature(env, M68K_FEATURE_M68020)) {
+ /*
+ * M68020 Long Bus Cycle Fault (Format 0xB).
+ * The Motorola 68020 hardware intrinsically generates a physical
+ * Bus Error exception whenever the system bus flags a transaction
+ * timeout or failure (e.g., attempting to read an unpopulated bus
+ * address). This natively injects the EXCP_ACCESS cycle to build
+ * the generic 84-byte exception stack frame.
+ */
+ env->mmu.ssw = 0;
+ if (access_type == MMU_INST_FETCH) {
+ env->mmu.ssw |= 0x1000;
+ } else if (access_type == MMU_DATA_STORE) {
+ env->mmu.ssw |= 0x0040;
+ } else {
+ env->mmu.ssw |= 0x0080;
+ }
+ } else {
+ /*
+ * Older architectures (e.g. 68000) do not currently support
+ * hardware-injected transaction failures in QEMU.
+ */
+ return;
}
+
+ env->mmu.ar = addr;
+ cs->exception_index = EXCP_ACCESS;
+ cpu_loop_exit(cs);
}
bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUM68KState *env = cpu_env(cs);
- if (interrupt_request & CPU_INTERRUPT_HARD
- && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) {
- /*
- * Real hardware gets the interrupt vector via an IACK cycle
- * at this point. Current emulated hardware doesn't rely on
- * this, so we provide/save the vector when the interrupt is
- * first signalled.
- */
+ if (env->nmi_pending) {
+ env->nmi_pending = false;
+ cs->exception_index = env->pending_vector;
+ do_interrupt_m68k_hardirq(env);
+ return true;
+ } else if (((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) {
cs->exception_index = env->pending_vector;
do_interrupt_m68k_hardirq(env);
return true;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index abc1c79f3c..d6fcd6c4d9 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* m68k translation
*
@@ -163,10 +164,12 @@ static void do_writebacks(DisasContext *s)
#define IS_USER(s) 1
#else
#define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
-#define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
- MMU_KERNEL_IDX : MMU_USER_IDX)
-#define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
- MMU_KERNEL_IDX : MMU_USER_IDX)
+#define SFC_INDEX(s) (MMU_MOVES_FC_BASE + \
+ (((s)->base.tb->flags & TB_FLAGS_SFC_S) >> \
+ TB_FLAGS_SFC_S_BIT))
+#define DFC_INDEX(s) (MMU_MOVES_FC_BASE + \
+ (((s)->base.tb->flags & TB_FLAGS_DFC_S) >> \
+ TB_FLAGS_DFC_S_BIT))
#endif
typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
@@ -5364,11 +5367,19 @@ DISAS_INSN(frestore)
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
- if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
+ if (m68k_feature(s->env, M68K_FEATURE_M68040) ||
+ m68k_feature(s->env, M68K_FEATURE_FPU)) {
SRC_EA(env, addr, OS_LONG, 0, NULL);
- /* FIXME: check the state frame */
+ if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
+ /* FIXME: check the state frame */
+ } else {
+ /*
+ * 68881/68882 FRESTORE: read the state frame
+ * (NULL frame is 4 bytes)
+ */
+ }
} else {
- disas_undef(env, s, insn);
+ disas_undef_fpu(env, s, insn);
}
}
@@ -5383,8 +5394,12 @@ DISAS_INSN(fsave)
/* always write IDLE */
TCGv idle = tcg_constant_i32(0x41000000);
DEST_EA(env, insn, OS_LONG, idle, NULL);
+ } else if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
+ /* 68881/68882 FSAVE: always write NULL frame */
+ TCGv null_frame = tcg_constant_i32(0x00000000);
+ DEST_EA(env, insn, OS_LONG, null_frame, NULL);
} else {
- disas_undef(env, s, insn);
+ disas_undef_fpu(env, s, insn);
}
}
#endif
--
2.50.1 (Apple Git-155)
next prev parent reply other threads:[~2026-05-03 5:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-03 1:57 [PATCH 0/7] m68k: Add Sun-3 Machine Emulation 54weasels
2026-05-03 1:57 ` 54weasels [this message]
2026-05-10 5:40 ` [PATCH 1/7] target/m68k: Implement Physical Bus Error exception handling Thomas Huth
2026-05-11 6:38 ` Purr Box
2026-05-03 1:57 ` [PATCH 2/7] hw/net/lance: Add Sun-3 Native DMA byte-swapping support 54weasels
2026-05-03 1:57 ` [PATCH 3/7] hw/char/escc: Expose diagnostic RS232 I/O routing 54weasels
2026-05-03 1:57 ` [PATCH 4/7] hw/timer: Introduce Intersil 7170 RTC implementation 54weasels
2026-05-03 1:57 ` [PATCH 5/7] hw/m68k: Overhaul Sun-3 MMU and Boot PROM mapping 54weasels
2026-05-03 1:57 ` [PATCH 6/7] tests/qtest: Add Sun-3 hardware interaction tests 54weasels
2026-05-03 1:57 ` [PATCH 7/7] tests/functional: Add Sun-3 firmware boot and diagnostic test 54weasels
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