* [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup
@ 2026-05-06 12:34 Michael Walle
2026-05-06 12:34 ` [PATCH v2 01/11] powerpc: fix call to cpu_init_r Michael Walle
` (11 more replies)
0 siblings, 12 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
While working on an ancient P2041 based board, I've encountered
several issues.
cpu_init_r wasn't called anymore, but u-boot was still somehow
working. CAAM was reading/writing on address 0 because pamu_init()
is never called if secure boot isn't enabled.
Since legacy ethernet was removed, board_eth_init() and
fdt_fixup_board_enet() won't be called anymore, but the functions
are still defined. I've just removed the ones for the NXP boards,
though I think the code there did something useful. But given that
it wasn't called for two years now and nobody complained, it can't
be that important.
Lastly, because I have a p2041rdb, move that to a upstream DTS.
Keep in mind, that the uboot dts doesn't define an UART, so any
output was broken since the move to DM provided serial support.
v2:
- new patch
p2041rdb: convert README to rst
- fix build errors, tested all commits with buildman
Michael Walle (11):
powerpc: fix call to cpu_init_r
caam: don't write memory at 0 on PPC
spi: fsl_espi: fix read transactions
boards: remove dead fman code
boards/nxp: remove board_eth_init()
boards/nxp: remove empty fdt_fixup_board_enet()
p2041rdb: use the upstream device tree
p2041rdb: support SDcard boot
p2041rdb: update README and fix typos
p2041rdb: remove NAND defconfig
p2041rdb: convert README to rst
arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +-
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/p2041.dtsi | 138 ----
arch/powerpc/dts/p2041rdb-u-boot.dtsi | 19 +
arch/powerpc/dts/p2041rdb.dts | 127 ---
arch/powerpc/dts/p2041si-post.dtsi | 43 --
board/nxp/ls1012afrdm/eth.c | 10 -
board/nxp/ls1012ardb/eth.c | 12 -
board/nxp/ls1021atsn/ls1021atsn.c | 5 -
board/nxp/ls1021atwr/ls1021atwr.c | 5 -
board/nxp/ls1028a/ls1028a.c | 5 -
board/nxp/ls1043aqds/Makefile | 3 -
board/nxp/ls1043aqds/eth.c | 501 ------------
board/nxp/ls1043aqds/ls1043aqds.c | 4 -
board/nxp/ls1043ardb/Makefile | 1 -
board/nxp/ls1043ardb/eth.c | 77 --
board/nxp/ls1046afrwy/eth.c | 57 --
board/nxp/ls1046aqds/Makefile | 3 -
board/nxp/ls1046aqds/eth.c | 431 -----------
board/nxp/ls1046aqds/ls1046aqds.c | 4 -
board/nxp/ls1046ardb/eth.c | 71 --
board/nxp/ls2080ardb/eth_ls2080rdb.c | 19 -
board/nxp/lx2160a/eth_lx2160aqds.c | 18 -
board/nxp/lx2160a/eth_lx2160ardb.c | 17 -
board/nxp/lx2160a/eth_lx2162aqds.c | 18 -
board/nxp/m5253demo/m5253demo.c | 7 -
board/nxp/mx6sxsabreauto/mx6sxsabreauto.c | 52 --
board/nxp/mx6sxsabresd/mx6sxsabresd.c | 78 --
board/nxp/p2041rdb/Makefile | 1 -
board/nxp/p2041rdb/README | 138 ----
board/nxp/p2041rdb/README.rst | 147 ++++
board/nxp/p2041rdb/eth.c | 210 -----
board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg | 11 +
...{rcw_p2041rdb.cfg => p2041rdb_rcw_spi.cfg} | 0
board/nxp/t102xrdb/Makefile | 1 -
board/nxp/t102xrdb/eth_t102xrdb.c | 149 ----
board/nxp/t102xrdb/t102xrdb.c | 1 -
board/nxp/t102xrdb/t102xrdb.h | 1 -
board/nxp/t104xrdb/Makefile | 1 -
board/nxp/t104xrdb/eth.c | 91 ---
board/nxp/t104xrdb/t104xrdb.h | 1 -
board/nxp/t208xqds/Makefile | 2 +-
board/nxp/t208xqds/eth_t208xqds.c | 723 ------------------
board/nxp/t208xqds/t208xqds.c | 1 -
board/nxp/t208xqds/t208xqds.h | 1 -
board/nxp/t208xrdb/eth_t208xrdb.c | 5 -
board/nxp/t208xrdb/t208xrdb.c | 1 -
board/nxp/t208xrdb/t208xrdb.h | 1 -
board/nxp/t4rdb/Makefile | 1 -
board/nxp/t4rdb/eth.c | 152 ----
board/nxp/t4rdb/t4240rdb.c | 1 -
board/nxp/t4rdb/t4rdb.h | 1 -
common/board_r.c | 2 +-
configs/P2041RDB_NAND_defconfig | 117 ---
configs/P2041RDB_SDCARD_defconfig | 6 +-
configs/P2041RDB_SPIFLASH_defconfig | 6 +-
configs/P2041RDB_defconfig | 4 +-
drivers/spi/fsl_espi.c | 6 +-
include/configs/P2041RDB.h | 2 +
59 files changed, 200 insertions(+), 3316 deletions(-)
delete mode 100644 arch/powerpc/dts/p2041.dtsi
create mode 100644 arch/powerpc/dts/p2041rdb-u-boot.dtsi
delete mode 100644 arch/powerpc/dts/p2041rdb.dts
delete mode 100644 arch/powerpc/dts/p2041si-post.dtsi
delete mode 100644 board/nxp/ls1043aqds/eth.c
delete mode 100644 board/nxp/ls1043ardb/eth.c
delete mode 100644 board/nxp/ls1046aqds/eth.c
delete mode 100644 board/nxp/p2041rdb/README
create mode 100644 board/nxp/p2041rdb/README.rst
delete mode 100644 board/nxp/p2041rdb/eth.c
create mode 100644 board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg
rename board/nxp/p2041rdb/{rcw_p2041rdb.cfg => p2041rdb_rcw_spi.cfg} (100%)
delete mode 100644 board/nxp/t102xrdb/eth_t102xrdb.c
delete mode 100644 board/nxp/t104xrdb/eth.c
delete mode 100644 board/nxp/t208xqds/eth_t208xqds.c
delete mode 100644 board/nxp/t4rdb/eth.c
delete mode 100644 configs/P2041RDB_NAND_defconfig
--
2.47.3
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 01/11] powerpc: fix call to cpu_init_r
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 02/11] caam: don't write memory at 0 on PPC Michael Walle
` (10 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
Commit 6c171f7a184c ("common: board: make initcalls static") broke the
call to cpu_init_r. That is because PPC is already defined to 1, see:
powerpc-linux-gnu-gcc -dM -E - < /dev/null
This will conflict with the CONFIG_IS_ENABLED(PPC). Change it to
IS_ENABLED(CONFIG_PPC).
Fixes: 6c171f7a184c ("common: board: make initcalls static")
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
common/board_r.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/board_r.c b/common/board_r.c
index 5d37345ca09..9b6ba9d8e56 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -687,7 +687,7 @@ static void initcall_run_r(void)
INITCALL(initr_flash);
#endif
WATCHDOG_RESET();
-#if CONFIG_IS_ENABLED(PPC) || CONFIG_IS_ENABLED(M68K) || CONFIG_IS_ENABLED(X86)
+#if IS_ENABLED(CONFIG_PPC) || CONFIG_IS_ENABLED(M68K) || CONFIG_IS_ENABLED(X86)
/* initialize higher level parts of CPU like time base and timers */
INITCALL(cpu_init_r);
#endif
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 02/11] caam: don't write memory at 0 on PPC
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
2026-05-06 12:34 ` [PATCH v2 01/11] powerpc: fix call to cpu_init_r Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 03/11] spi: fsl_espi: fix read transactions Michael Walle
` (9 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
For non-secure boot environments pamu_init() isn't called but the CAAM
will still call sec_config_pamu_table() -> config_pamu() which then uses
an uninitialized ppaact variable. In fact, that variable is initialized
with 0, so the config_pamu() will happily assume the structure is there
and will operate on that memory. Call pamu_init() in the non-secure boot
case, too.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 739d14f8002..414782c835f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -41,10 +41,12 @@
#ifdef CONFIG_FSL_CAAM
#include <fsl_sec.h>
#endif
-#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_FSL_CORENET)
#include <asm/fsl_pamu.h>
+#if defined(CONFIG_NXP_ESBC)
#include <fsl_secboot_err.h>
#endif
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
@@ -899,6 +901,8 @@ int cpu_init_r(void)
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
if (pamu_init() < 0)
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#elif defined(CONFIG_FSL_CORENET)
+ pamu_init();
#endif
#ifdef CONFIG_FSL_CAAM
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 03/11] spi: fsl_espi: fix read transactions
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
2026-05-06 12:34 ` [PATCH v2 01/11] powerpc: fix call to cpu_init_r Michael Walle
2026-05-06 12:34 ` [PATCH v2 02/11] caam: don't write memory at 0 on PPC Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 04/11] boards: remove dead fman code Michael Walle
` (8 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
Since commit 7917c2e35604 ("spi: fsl_espi: fix din offset") MTD is
basically broken because any read transaction will get wrong data. While
the commit in question will fix simple transfers (where both
SPI_XFER_BEGIN and SPI_XFER_END is set), it will break the most common
case, where opcode and address is send first and then data comes as a
second transfer.
This basically reverts commit 7917c2e35604 ("spi: fsl_espi: fix din
offset") and make the fix particular for this simple case. Instead of
providing two buffers for reading and writing, just malloc one which is
used for both. This will work because the data is first written on the
SPI bus and then it will be read (and overwite the written data) into
the same buffer.
Suggested-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
Fixes: 7917c2e35604 ("spi: fsl_espi: fix din offset")
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
drivers/spi/fsl_espi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 117e36376b7..c5bc603b5c0 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -216,13 +216,13 @@ int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
break;
case SPI_XFER_BEGIN | SPI_XFER_END:
len = data_len;
- buffer = (unsigned char *)malloc(len * 2);
+ buffer = (unsigned char *)malloc(len);
if (!buffer) {
debug("SF: Failed to malloc memory.\n");
return 1;
}
memcpy(buffer, data_out, len);
- rx_offset = len;
+ rx_offset = 0;
cmd_len = 0;
break;
}
@@ -275,7 +275,7 @@ int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
}
}
if (data_in) {
- memcpy(data_in, buffer + rx_offset, tran_len);
+ memcpy(data_in, buffer + 2 * cmd_len, tran_len);
if (*buffer == 0x0b) {
data_in += tran_len;
data_len -= tran_len;
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 04/11] boards: remove dead fman code
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (2 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 03/11] spi: fsl_espi: fix read transactions Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 05/11] boards/nxp: remove board_eth_init() Michael Walle
` (7 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
Commit cc2bf624eb71 ("net: fm: Remove non-DM_ETH code") removed the call
to board_ft_fman_fixup_port(). Thus remove the dead code in the board
files.
I'm not sure, all that DT shenanigans are covered by the new DM-version
of the fman code, but it seems no one complained for the past 4 years.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
board/nxp/ls1043aqds/eth.c | 99 -------------
board/nxp/ls1046aqds/eth.c | 81 -----------
board/nxp/p2041rdb/eth.c | 71 +---------
board/nxp/t102xrdb/eth_t102xrdb.c | 15 --
board/nxp/t208xqds/eth_t208xqds.c | 225 ------------------------------
5 files changed, 1 insertion(+), 490 deletions(-)
diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c
index 5a8ca27b327..5680fd2d377 100644
--- a/board/nxp/ls1043aqds/eth.c
+++ b/board/nxp/ls1043aqds/eth.c
@@ -159,105 +159,6 @@ static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
return mdio_register(bus);
}
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- struct fixed_link f_link;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- if (port == FM1_DTSEC9) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii-riser-s1-p1");
- } else if (port == FM1_DTSEC2) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii-riser-s2-p1");
- } else if (port == FM1_DTSEC5) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii-riser-s3-p1");
- } else if (port == FM1_DTSEC6) {
- fdt_set_phy_handle(fdt, compat, addr,
- "sgmii-riser-s4-p1");
- }
- } else if (fm_info_get_enet_if(port) ==
- PHY_INTERFACE_MODE_2500BASEX) {
- /* 2.5G SGMII interface */
- f_link.phy_id = cpu_to_fdt32(port);
- f_link.duplex = cpu_to_fdt32(1);
- f_link.link_speed = cpu_to_fdt32(1000);
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for 2.5G SGMII */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "2500base-x");
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
- switch (mdio_mux[port]) {
- case EMI1_SLOT1:
- switch (port) {
- case FM1_DTSEC1:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s1-p1");
- break;
- case FM1_DTSEC2:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s1-p2");
- break;
- case FM1_DTSEC5:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s1-p3");
- break;
- case FM1_DTSEC6:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s1-p4");
- break;
- default:
- break;
- }
- break;
- case EMI1_SLOT2:
- switch (port) {
- case FM1_DTSEC1:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s2-p1");
- break;
- case FM1_DTSEC2:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s2-p2");
- break;
- case FM1_DTSEC5:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s2-p3");
- break;
- case FM1_DTSEC6:
- fdt_set_phy_handle(fdt, compat, addr,
- "qsgmii-s2-p4");
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- fdt_delprop(fdt, offset, "phy-connection-type");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "qsgmii");
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
- port == FM1_10GEC1) {
- /* 10GBase-R interface */
- f_link.phy_id = cpu_to_fdt32(port);
- f_link.duplex = cpu_to_fdt32(1);
- f_link.link_speed = cpu_to_fdt32(10000);
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for 10GBase-R */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
- }
-}
-
void fdt_fixup_board_enet(void *fdt)
{
int i;
diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c
index cd3500c2e96..8446f438d3c 100644
--- a/board/nxp/ls1046aqds/eth.c
+++ b/board/nxp/ls1046aqds/eth.c
@@ -155,87 +155,6 @@ static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
return mdio_register(bus);
}
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- struct fixed_link f_link;
- const char *phyconn;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- switch (port) {
- case FM1_DTSEC9:
- fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1");
- break;
- case FM1_DTSEC10:
- fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2");
- break;
- case FM1_DTSEC5:
- fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3");
- break;
- case FM1_DTSEC6:
- fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4");
- break;
- case FM1_DTSEC2:
- fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1");
- break;
- default:
- break;
- }
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
- /* 2.5G SGMII interface */
- f_link.phy_id = cpu_to_fdt32(port);
- f_link.duplex = cpu_to_fdt32(1);
- f_link.link_speed = cpu_to_fdt32(1000);
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for 2.5G SGMII on QDS */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "2500base-x");
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
- switch (port) {
- case FM1_DTSEC1:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4");
- break;
- case FM1_DTSEC5:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2");
- break;
- case FM1_DTSEC6:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1");
- break;
- case FM1_DTSEC10:
- fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3");
- break;
- default:
- break;
- }
- fdt_delprop(fdt, offset, "phy-connection-type");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "qsgmii");
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
- (port == FM1_10GEC1 || port == FM1_10GEC2)) {
- phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
- if (is_backplane_mode(phyconn)) {
- /* Backplane KR mode: skip fixups */
- printf("Interface %d in backplane KR mode\n", port);
- } else {
- /* 10GBase-R interface */
- f_link.phy_id = cpu_to_fdt32(port);
- f_link.duplex = cpu_to_fdt32(1);
- f_link.link_speed = cpu_to_fdt32(10000);
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for 10GBase-R */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link,
- sizeof(f_link));
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "xgmii");
- }
- }
-}
-
void fdt_fixup_board_enet(void *fdt)
{
int i;
diff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c
index 65850866777..d51b579b8b0 100644
--- a/board/nxp/p2041rdb/eth.c
+++ b/board/nxp/p2041rdb/eth.c
@@ -56,76 +56,6 @@ static void initialize_lane_to_slot(void)
lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
}
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- phy_interface_t intf = fm_info_get_enet_if(port);
- char phy[16];
- int lane;
- u8 slot;
-
- switch (intf) {
- /* The RGMII PHY is identified by the MAC connected to it */
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- break;
- /* The SGMII PHY is identified by the MAC connected to it */
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
- if (lane < 0)
- return;
- slot = lane_to_slot[lane];
- if (slot) {
- sprintf(phy, "phy_sgmii_%x",
- CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
- + (port - FM1_DTSEC1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- } else {
- sprintf(phy, "phy_sgmii_%x",
- CFG_SYS_FM1_DTSEC1_PHY_ADDR
- + (port - FM1_DTSEC1));
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- break;
- case PHY_INTERFACE_MODE_XGMII:
- /* XAUI */
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- /* The XAUI PHY is identified by the slot */
- sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
- fdt_set_phy_handle(fdt, compat, addr, phy);
- }
- break;
- default:
- break;
- }
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_FMAN_ENET
@@ -208,3 +138,4 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
+#endif /* #ifdef CONFIG_FMAN_ENET */
diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c
index 7185a0abd52..91f87983dc5 100644
--- a/board/nxp/t102xrdb/eth_t102xrdb.c
+++ b/board/nxp/t102xrdb/eth_t102xrdb.c
@@ -129,21 +129,6 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
-#if defined(CONFIG_TARGET_T1024RDB)
- if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
- (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
- (port == FM1_DTSEC3)) {
- fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
- fdt_setprop_string(fdt, offset, "phy-connection-type",
- "2500base-x");
- fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
- }
-#endif
-}
-
void fdt_fixup_board_enet(void *fdt)
{
}
diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c
index b55078c8fe1..12951df591e 100644
--- a/board/nxp/t208xqds/eth_t208xqds.c
+++ b/board/nxp/t208xqds/eth_t208xqds.c
@@ -177,231 +177,6 @@ static int t208xqds_mdio_init(char *realbusname, u8 muxval)
return mdio_register(bus);
}
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
- enum fm_port port, int offset)
-{
- int phy;
- char alias[20];
- char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
- char buf[32] = "serdes-1,";
- struct fixed_link f_link;
- int media_type = 0;
- const char *phyconn;
- int off;
-
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_TARGET_T2080QDS
- serdes_corenet_t *srds_regs =
- (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
-#endif
- u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
- phy = fm_info_get_phy_address(port);
- switch (port) {
-#if defined(CONFIG_TARGET_T2080QDS)
- case FM1_DTSEC1:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx1");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
- strcat(buf, "lane-c,");
- strcat(buf, (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIH_KX_MASK);
- break;
- }
- case FM1_DTSEC2:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx2");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
- strcat(buf, "lane-d,");
- strcat(buf, (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIG_KX_MASK);
- break;
- }
- case FM1_DTSEC9:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx9");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
- strcat(buf, "lane-a,");
- strcat(buf, (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIE_KX_MASK);
- break;
- }
- case FM1_DTSEC10:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx10");
- fdt_status_okay_by_alias(fdt,
- "1gkx_pcs_mdio10");
- strcat(buf, "lane-b,");
- strcat(buf, (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIF_KX_MASK);
- break;
- }
- if (mdio_mux[port] == EMI1_SLOT2) {
- sprintf(alias, "phy_sgmii_s2_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- } else if (mdio_mux[port] == EMI1_SLOT3) {
- sprintf(alias, "phy_sgmii_s3_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
- }
- break;
- case FM1_DTSEC5:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx5");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
- strcat(buf, "lane-g,");
- strcat(buf, (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIIC_KX_MASK);
- break;
- }
- case FM1_DTSEC6:
- if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_1gkx6");
- fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
- strcat(buf, "lane-h,");
- strcat(buf, (char *)lane_mode[0]);
- out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
- PCCR1_SGMIID_KX_MASK);
- break;
- }
- if (mdio_mux[port] == EMI1_SLOT1) {
- sprintf(alias, "phy_sgmii_s1_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot1");
- } else if (mdio_mux[port] == EMI1_SLOT2) {
- sprintf(alias, "phy_sgmii_s2_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot2");
- }
- break;
-#endif
- default:
- break;
- }
- if (media_type) {
- /* set property for 1000BASE-KX in dtb */
- off = fdt_node_offset_by_compat_reg(fdt,
- "fsl,fman-memac-mdio", addr + 0x1000);
- fdt_setprop_string(fdt, off, "lane-instance", buf);
- }
-
- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
- switch (srds_s1) {
- case 0x66: /* 10GBase-R interface */
- case 0x6b:
- case 0x6c:
- case 0x6d:
- case 0x71:
- /*
- * Check hwconfig to see what is the media type, there
- * are two types, fiber or copper, fix the dtb
- * accordingly.
- */
- switch (port) {
- case FM1_10GEC1:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
- /* it's MAC9 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi9");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
- strcat(buf, "lane-a,");
- strcat(buf, (char *)lane_mode[1]);
- }
- break;
- case FM1_10GEC2:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
- /* it's MAC10 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi10");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
- strcat(buf, "lane-b,");
- strcat(buf, (char *)lane_mode[1]);
- }
- break;
- case FM1_10GEC3:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
- /* it's MAC1 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi1");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
- strcat(buf, "lane-c,");
- strcat(buf, (char *)lane_mode[1]);
- }
- break;
- case FM1_10GEC4:
- if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
- /* it's MAC2 */
- media_type = 1;
- fdt_set_phy_handle(fdt, compat, addr,
- "phy_xfi2");
- fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
- strcat(buf, "lane-d,");
- strcat(buf, (char *)lane_mode[1]);
- }
- break;
- default:
- return;
- }
-
- if (!media_type) {
- phyconn = fdt_getprop(fdt, offset,
- "phy-connection-type",
- NULL);
- if (is_backplane_mode(phyconn)) {
- /* Backplane KR mode: skip fixups */
- printf("Interface %d in backplane KR mode\n",
- port);
- } else {
- /* fixed-link for 10GBase-R fiber cable */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link",
- &f_link, sizeof(f_link));
- }
- } else {
- /* set property for copper cable */
- off = fdt_node_offset_by_compat_reg(fdt,
- "fsl,fman-memac-mdio", addr + 0x1000);
- fdt_setprop_string(fdt, off,
- "lane-instance", buf);
- }
- break;
- default:
- break;
- }
- }
-}
-
void fdt_fixup_board_enet(void *fdt)
{
return;
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 05/11] boards/nxp: remove board_eth_init()
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (3 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 04/11] boards: remove dead fman code Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 06/11] boards/nxp: remove empty fdt_fixup_board_enet() Michael Walle
` (6 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
board_eth_init() is dead code since commit e524f3a449f5 ("net: Remove
eth_legacy.c"). Remove it.
I'm not sure, all the shenanigans are covered by the new DM-version. The
MDIO mux and iomux controls probably are. The fman configuration
probably isn't. OTOH, nobody cared for years and the called
fm_info_set_phy_address() was also removed years ago.
This also removes fdt_fixup_board_enet() for the ls1043a and ls1046a
because it relies on the local variable "mdio_mux" being initialized by
the board_eth_init().
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
board/nxp/ls1012afrdm/eth.c | 10 -
board/nxp/ls1012ardb/eth.c | 12 -
board/nxp/ls1021atsn/ls1021atsn.c | 5 -
board/nxp/ls1021atwr/ls1021atwr.c | 5 -
board/nxp/ls1028a/ls1028a.c | 5 -
board/nxp/ls1043aqds/eth.c | 391 ------------------
board/nxp/ls1043ardb/Makefile | 1 -
board/nxp/ls1043ardb/eth.c | 77 ----
board/nxp/ls1046afrwy/eth.c | 57 ---
board/nxp/ls1046aqds/eth.c | 339 ----------------
board/nxp/ls1046ardb/eth.c | 71 ----
board/nxp/ls2080ardb/eth_ls2080rdb.c | 19 -
board/nxp/lx2160a/eth_lx2160aqds.c | 18 -
board/nxp/lx2160a/eth_lx2160ardb.c | 17 -
board/nxp/lx2160a/eth_lx2162aqds.c | 18 -
board/nxp/m5253demo/m5253demo.c | 7 -
board/nxp/mx6sxsabreauto/mx6sxsabreauto.c | 52 ---
board/nxp/mx6sxsabresd/mx6sxsabresd.c | 78 ----
board/nxp/p2041rdb/Makefile | 1 -
board/nxp/p2041rdb/eth.c | 141 -------
board/nxp/t102xrdb/eth_t102xrdb.c | 103 -----
board/nxp/t104xrdb/Makefile | 1 -
board/nxp/t104xrdb/eth.c | 91 -----
board/nxp/t208xqds/eth_t208xqds.c | 460 ----------------------
board/nxp/t4rdb/eth.c | 115 ------
25 files changed, 2094 deletions(-)
delete mode 100644 board/nxp/ls1043ardb/eth.c
delete mode 100644 board/nxp/p2041rdb/eth.c
delete mode 100644 board/nxp/t104xrdb/eth.c
diff --git a/board/nxp/ls1012afrdm/eth.c b/board/nxp/ls1012afrdm/eth.c
index c431e5e611b..8761ec7845e 100644
--- a/board/nxp/ls1012afrdm/eth.c
+++ b/board/nxp/ls1012afrdm/eth.c
@@ -7,16 +7,6 @@
#include <dm.h>
#include <net.h>
#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <asm/types.h>
-#include <fsl_dtsec.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/config.h>
-#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-#include <asm/arch/fsl_serdes.h>
#include <linux/delay.h>
#include <net/pfe_eth/pfe_eth.h>
#include <dm/platform_data/pfe_dm_eth.h>
diff --git a/board/nxp/ls1012ardb/eth.c b/board/nxp/ls1012ardb/eth.c
index 71cb2988a56..6a6f4608fd1 100644
--- a/board/nxp/ls1012ardb/eth.c
+++ b/board/nxp/ls1012ardb/eth.c
@@ -6,18 +6,6 @@
#include <config.h>
#include <dm.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <asm/types.h>
-#include <fsl_dtsec.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/config.h>
-#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-#include <asm/arch/fsl_serdes.h>
#include <linux/delay.h>
#include <net/pfe_eth/pfe_eth.h>
#include <dm/platform_data/pfe_dm_eth.h>
diff --git a/board/nxp/ls1021atsn/ls1021atsn.c b/board/nxp/ls1021atsn/ls1021atsn.c
index c92430c0896..277506fdbb8 100644
--- a/board/nxp/ls1021atsn/ls1021atsn.c
+++ b/board/nxp/ls1021atsn/ls1021atsn.c
@@ -123,11 +123,6 @@ int dram_init(void)
return 0;
}
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
diff --git a/board/nxp/ls1021atwr/ls1021atwr.c b/board/nxp/ls1021atwr/ls1021atwr.c
index 0758e5eae25..135497f7c5d 100644
--- a/board/nxp/ls1021atwr/ls1021atwr.c
+++ b/board/nxp/ls1021atwr/ls1021atwr.c
@@ -239,11 +239,6 @@ int dram_init(void)
return 0;
}
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void convert_serdes_mux(int type, int need_reset)
{
diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c
index db94d9c1fa8..007125358bd 100644
--- a/board/nxp/ls1028a/ls1028a.c
+++ b/board/nxp/ls1028a/ls1028a.c
@@ -103,11 +103,6 @@ int board_init(void)
return 0;
}
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c
index 5680fd2d377..d62cf74732c 100644
--- a/board/nxp/ls1043aqds/eth.c
+++ b/board/nxp/ls1043aqds/eth.c
@@ -4,399 +4,8 @@
* Copyright 2019 NXP
*/
-#include <config.h>
-#include <log.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
#include <fdt_support.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <fsl_dtsec.h>
-#include <linux/libfdt.h>
-#include <malloc.h>
-#include <asm/arch/fsl_serdes.h>
-
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "ls1043aqds_qixis.h"
-
-#define EMI_NONE 0xFF
-#define EMI1_RGMII1 0
-#define EMI1_RGMII2 1
-#define EMI1_SLOT1 2
-#define EMI1_SLOT2 3
-#define EMI1_SLOT3 4
-#define EMI1_SLOT4 5
-#define EMI2 6
-
-static const char * const mdio_names[] = {
- "LS1043AQDS_MDIO_RGMII1",
- "LS1043AQDS_MDIO_RGMII2",
- "LS1043AQDS_MDIO_SLOT1",
- "LS1043AQDS_MDIO_SLOT2",
- "LS1043AQDS_MDIO_SLOT3",
- "LS1043AQDS_MDIO_SLOT4",
- "NULL",
-};
-
-/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
-#ifdef CONFIG_FMAN_ENET
-static int mdio_mux[NUM_FM_PORTS];
-
-static u8 lane_to_slot[] = {1, 2, 3, 4};
-#endif
-
-static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name;
-
- if (muxval > EMI2)
- return NULL;
-
- name = ls1043aqds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-#ifdef CONFIG_FMAN_ENET
-struct ls1043aqds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void ls1043aqds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
-
- if (muxval < 7) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct ls1043aqds_mdio *priv = bus->priv;
-
- ls1043aqds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct ls1043aqds_mdio *priv = bus->priv;
-
- ls1043aqds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad,
- regnum, value);
-}
-
-static int ls1043aqds_mdio_reset(struct mii_dev *bus)
-{
- struct ls1043aqds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
-{
- struct ls1043aqds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate ls1043aqds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate ls1043aqds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = ls1043aqds_mdio_read;
- bus->write = ls1043aqds_mdio_write;
- bus->reset = ls1043aqds_mdio_reset;
- strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
- return mdio_register(bus);
-}
void fdt_fixup_board_enet(void *fdt)
{
- int i;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- switch (mdio_mux[i]) {
- case EMI1_SLOT1:
- fdt_status_okay_by_alias(fdt, "emi1-slot1");
- break;
- case EMI1_SLOT2:
- fdt_status_okay_by_alias(fdt, "emi1-slot2");
- break;
- case EMI1_SLOT3:
- fdt_status_okay_by_alias(fdt, "emi1-slot3");
- break;
- case EMI1_SLOT4:
- fdt_status_okay_by_alias(fdt, "emi1-slot4");
- break;
- default:
- break;
- }
- break;
- case PHY_INTERFACE_MODE_XGMII:
- break;
- default:
- break;
- }
- }
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- switch (srds_s1) {
- case 0x2555:
- /* 2.5G SGMII on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_DTSEC9, 9);
- break;
- case 0x4555:
- case 0x4558:
- /* QSGMII on lane A, MAC 1/2/5/6 */
- fm_info_set_phy_address(FM1_DTSEC1,
- QSGMII_CARD_PORT1_PHY_ADDR_S1);
- fm_info_set_phy_address(FM1_DTSEC2,
- QSGMII_CARD_PORT2_PHY_ADDR_S1);
- fm_info_set_phy_address(FM1_DTSEC5,
- QSGMII_CARD_PORT3_PHY_ADDR_S1);
- fm_info_set_phy_address(FM1_DTSEC6,
- QSGMII_CARD_PORT4_PHY_ADDR_S1);
- break;
- case 0x1355:
- /* SGMII on lane B, MAC 2*/
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x2355:
- /* 2.5G SGMII on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_DTSEC9, 9);
- /* SGMII on lane B, MAC 2*/
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x3335:
- /* SGMII on lane C, MAC 5 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- case 0x3355:
- case 0x3358:
- /* SGMII on lane B, MAC 2 */
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
- case 0x3555:
- case 0x3558:
- /* SGMII on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- break;
- case 0x1455:
- /* QSGMII on lane B, MAC 1/2/5/6 */
- fm_info_set_phy_address(FM1_DTSEC1,
- QSGMII_CARD_PORT1_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC2,
- QSGMII_CARD_PORT2_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC5,
- QSGMII_CARD_PORT3_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC6,
- QSGMII_CARD_PORT4_PHY_ADDR_S2);
- break;
- case 0x2455:
- /* 2.5G SGMII on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_DTSEC9, 9);
- /* QSGMII on lane B, MAC 1/2/5/6 */
- fm_info_set_phy_address(FM1_DTSEC1,
- QSGMII_CARD_PORT1_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC2,
- QSGMII_CARD_PORT2_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC5,
- QSGMII_CARD_PORT3_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC6,
- QSGMII_CARD_PORT4_PHY_ADDR_S2);
- break;
- case 0x2255:
- /* 2.5G SGMII on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_DTSEC9, 9);
- /* 2.5G SGMII on lane B, MAC 2 */
- fm_info_set_phy_address(FM1_DTSEC2, 2);
- break;
- case 0x3333:
- /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
- fm_info_set_phy_address(FM1_DTSEC9,
- SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2,
- SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5,
- SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6,
- SGMII_CARD_PORT1_PHY_ADDR);
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
- srds_s1);
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_2500BASEX:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_SGMII) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- } else if (interface == PHY_INTERFACE_MODE_2500BASEX) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_2500_FM1_DTSEC1 + idx);
- } else {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_A);
- }
-
- if (lane < 0)
- break;
-
- slot = lane_to_slot[lane];
- debug("FM1@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
-
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- default:
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- if (i == FM1_DTSEC3)
- mdio_mux[i] = EMI1_RGMII1;
- else if (i == FM1_DTSEC4)
- mdio_mux[i] = EMI1_RGMII2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-
- return pci_eth_init(bis);
}
-#endif /* CONFIG_FMAN_ENET */
diff --git a/board/nxp/ls1043ardb/Makefile b/board/nxp/ls1043ardb/Makefile
index 95745bf3a9c..13e0411c1ba 100644
--- a/board/nxp/ls1043ardb/Makefile
+++ b/board/nxp/ls1043ardb/Makefile
@@ -5,6 +5,5 @@
obj-y += ddr.o
obj-y += ls1043ardb.o
ifndef CONFIG_XPL_BUILD
-obj-$(CONFIG_NET) += eth.o
obj-y += cpld.o
endif
diff --git a/board/nxp/ls1043ardb/eth.c b/board/nxp/ls1043ardb/eth.c
deleted file mode 100644
index cacc49c0584..00000000000
--- a/board/nxp/ls1043ardb/eth.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include <config.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- int i;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- /* QSGMII on lane B, MAC 1/2/5/6 */
- fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
-
- switch (srds_s1) {
- case 0x1455:
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
- srds_s1);
- break;
- }
-
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
- fm_info_set_mdio(i, dev);
-
- /* 10GBase-R on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(FM1_10GEC1, dev);
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/nxp/ls1046afrwy/eth.c b/board/nxp/ls1046afrwy/eth.c
index 8efc7f68424..d76841c6ab4 100644
--- a/board/nxp/ls1046afrwy/eth.c
+++ b/board/nxp/ls1046afrwy/eth.c
@@ -4,64 +4,7 @@
*/
#include <config.h>
#include <fdt_support.h>
-#include <net.h>
#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info dtsec_mdio_info;
- struct mii_dev *dev;
- u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- /* QSGMII on lane B, MAC 6/5/10/1 */
- fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
-
- switch (srds_s1) {
- case 0x3040:
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
- srds_s1);
- break;
- }
-
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(FM1_DTSEC6, dev);
- fm_info_set_mdio(FM1_DTSEC5, dev);
- fm_info_set_mdio(FM1_DTSEC10, dev);
- fm_info_set_mdio(FM1_DTSEC1, dev);
-
- fm_disable_port(FM1_DTSEC9);
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
#ifdef CONFIG_FMAN_ENET
int fdt_update_ethernet_dt(void *blob)
diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c
index 8446f438d3c..24e6c93aece 100644
--- a/board/nxp/ls1046aqds/eth.c
+++ b/board/nxp/ls1046aqds/eth.c
@@ -4,347 +4,8 @@
* Copyright 2018-2020 NXP
*/
-#include <config.h>
-#include <log.h>
-#include <net.h>
-#include <asm/io.h>
-#include <netdev.h>
#include <fdt_support.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <fsl_dtsec.h>
-#include <malloc.h>
-#include <asm/arch/fsl_serdes.h>
-
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "ls1046aqds_qixis.h"
-
-#define EMI_NONE 0xFF
-#define EMI1_RGMII1 0
-#define EMI1_RGMII2 1
-#define EMI1_SLOT1 2
-#define EMI1_SLOT2 3
-#define EMI1_SLOT4 4
-
-static const char * const mdio_names[] = {
- "LS1046AQDS_MDIO_RGMII1",
- "LS1046AQDS_MDIO_RGMII2",
- "LS1046AQDS_MDIO_SLOT1",
- "LS1046AQDS_MDIO_SLOT2",
- "LS1046AQDS_MDIO_SLOT4",
- "NULL",
-};
-
-/* Map SerDes 1 & 2 lanes to default slot. */
-#ifdef CONFIG_FMAN_ENET
-static int mdio_mux[NUM_FM_PORTS];
-
-static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
-#endif
-
-static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name;
-
- if (muxval > EMI1_SLOT4)
- return NULL;
-
- name = ls1046aqds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-#ifdef CONFIG_FMAN_ENET
-struct ls1046aqds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void ls1046aqds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
-
- if (muxval < 7) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct ls1046aqds_mdio *priv = bus->priv;
-
- ls1046aqds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct ls1046aqds_mdio *priv = bus->priv;
-
- ls1046aqds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad,
- regnum, value);
-}
-
-static int ls1046aqds_mdio_reset(struct mii_dev *bus)
-{
- struct ls1046aqds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
-{
- struct ls1046aqds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate ls1046aqds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate ls1046aqds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = ls1046aqds_mdio_read;
- bus->write = ls1046aqds_mdio_write;
- bus->reset = ls1046aqds_mdio_reset;
- sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
- return mdio_register(bus);
-}
void fdt_fixup_board_enet(void *fdt)
{
- int i;
-
- for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- switch (mdio_mux[i]) {
- case EMI1_SLOT1:
- fdt_status_okay_by_alias(fdt, "emi1-slot1");
- break;
- case EMI1_SLOT2:
- fdt_status_okay_by_alias(fdt, "emi1-slot2");
- break;
- case EMI1_SLOT4:
- fdt_status_okay_by_alias(fdt, "emi1-slot4");
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- }
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1, srds_s2;
- u8 brdcfg12;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- srds_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
- srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- switch (srds_s1) {
- case 0x3333:
- /* SGMII on slot 1, MAC 9 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- case 0x1333:
- case 0x2333:
- /* SGMII on slot 1, MAC 10 */
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- case 0x1133:
- case 0x2233:
- /* SGMII on slot 1, MAC 5/6 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- case 0x1040:
- case 0x2040:
- /* QSGMII on lane B, MAC 6/5/10/1 */
- fm_info_set_phy_address(FM1_DTSEC6,
- QSGMII_CARD_PORT1_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC5,
- QSGMII_CARD_PORT2_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC10,
- QSGMII_CARD_PORT3_PHY_ADDR_S2);
- fm_info_set_phy_address(FM1_DTSEC1,
- QSGMII_CARD_PORT4_PHY_ADDR_S2);
- break;
- case 0x3363:
- /* SGMII on slot 1, MAC 9/10 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- case 0x1163:
- case 0x2263:
- case 0x2223:
- /* SGMII on slot 1, MAC 6 */
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
- srds_s1);
- break;
- }
-
- if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
- /* SGMII on slot 4, MAC 2 */
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- if (interface == PHY_INTERFACE_MODE_SGMII) {
- if (i == FM1_DTSEC5) {
- /* route lane 2 to slot1 so to have
- * one sgmii riser card supports
- * MAC5 and MAC6.
- */
- brdcfg12 = QIXIS_READ(brdcfg[12]);
- QIXIS_WRITE(brdcfg[12],
- brdcfg12 | 0x80);
- }
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- } else {
- /* clear the bit 7 to route lane B on slot2. */
- brdcfg12 = QIXIS_READ(brdcfg[12]);
- QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
-
- lane = serdes_get_first_lane(FSL_SRDS_1,
- QSGMII_FM1_A);
- lane_to_slot[lane] = 2;
- }
-
- if (i == FM1_DTSEC2)
- lane = 5;
-
- if (lane < 0)
- break;
-
- slot = lane_to_slot[lane];
- debug("FM1@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
-
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 4:
- mdio_mux[i] = EMI1_SLOT4;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- default:
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- if (i == FM1_DTSEC3)
- mdio_mux[i] = EMI1_RGMII1;
- else if (i == FM1_DTSEC4)
- mdio_mux[i] = EMI1_RGMII2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-
- return pci_eth_init(bis);
}
-#endif /* CONFIG_FMAN_ENET */
diff --git a/board/nxp/ls1046ardb/eth.c b/board/nxp/ls1046ardb/eth.c
index fee8e0e21d4..ce9b7b81e3d 100644
--- a/board/nxp/ls1046ardb/eth.c
+++ b/board/nxp/ls1046ardb/eth.c
@@ -4,78 +4,7 @@
*/
#include <config.h>
#include <fdt_support.h>
-#include <net.h>
#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- int i;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- /* Set the two on-board SGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
-
- /* Set the on-board AQ PHY address */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-
- switch (srds_s1) {
- case 0x1133:
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
- srds_s1);
- break;
- }
-
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
- fm_info_set_mdio(i, dev);
-
- /* 10GBase-R on lane A, MAC 9 */
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(FM1_10GEC1, dev);
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
#ifdef CONFIG_FMAN_ENET
int fdt_update_ethernet_dt(void *blob)
diff --git a/board/nxp/ls2080ardb/eth_ls2080rdb.c b/board/nxp/ls2080ardb/eth_ls2080rdb.c
index 7d5beb32417..6a8859fd0c5 100644
--- a/board/nxp/ls2080ardb/eth_ls2080rdb.c
+++ b/board/nxp/ls2080ardb/eth_ls2080rdb.c
@@ -9,25 +9,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_eth_init(struct bd_info *bis)
-{
-
-#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD)
- /*
- * Export functions to be used by AQ firmware
- * upload application
- */
- gd->jt->strcpy = strcpy;
- gd->jt->mdelay = mdelay;
- gd->jt->mdio_get_current_dev = mdio_get_current_dev;
- gd->jt->phy_find_by_mask = phy_find_by_mask;
- gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
- gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
-
- return 0;
-}
-
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
diff --git a/board/nxp/lx2160a/eth_lx2160aqds.c b/board/nxp/lx2160a/eth_lx2160aqds.c
index 9939bb6f89e..4c16f565b69 100644
--- a/board/nxp/lx2160a/eth_lx2160aqds.c
+++ b/board/nxp/lx2160a/eth_lx2160aqds.c
@@ -11,24 +11,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_PHY_AQUANTIA
- /*
- * Export functions to be used by AQ firmware
- * upload application
- */
- gd->jt->strcpy = strcpy;
- gd->jt->mdelay = mdelay;
- gd->jt->mdio_get_current_dev = mdio_get_current_dev;
- gd->jt->phy_find_by_mask = phy_find_by_mask;
- gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
- gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
-
- return 0;
-}
-
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
diff --git a/board/nxp/lx2160a/eth_lx2160ardb.c b/board/nxp/lx2160a/eth_lx2160ardb.c
index 90e7c9100e1..31bbac6310e 100644
--- a/board/nxp/lx2160a/eth_lx2160ardb.c
+++ b/board/nxp/lx2160a/eth_lx2160ardb.c
@@ -11,23 +11,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_PHY_AQUANTIA
- /*
- * Export functions to be used by AQ firmware
- * upload application
- */
- gd->jt->strcpy = strcpy;
- gd->jt->mdelay = mdelay;
- gd->jt->mdio_get_current_dev = mdio_get_current_dev;
- gd->jt->phy_find_by_mask = phy_find_by_mask;
- gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
- gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
- return pci_eth_init(bis);
-}
-
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
diff --git a/board/nxp/lx2160a/eth_lx2162aqds.c b/board/nxp/lx2160a/eth_lx2162aqds.c
index 805aa705be9..81b81d47978 100644
--- a/board/nxp/lx2160a/eth_lx2162aqds.c
+++ b/board/nxp/lx2160a/eth_lx2162aqds.c
@@ -11,24 +11,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_PHY_AQUANTIA
- /*
- * Export functions to be used by AQ firmware
- * upload application
- */
- gd->jt->strcpy = strcpy;
- gd->jt->mdelay = mdelay;
- gd->jt->mdio_get_current_dev = mdio_get_current_dev;
- gd->jt->phy_find_by_mask = phy_find_by_mask;
- gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
- gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
-
- return 0;
-}
-
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
diff --git a/board/nxp/m5253demo/m5253demo.c b/board/nxp/m5253demo/m5253demo.c
index 50c5320b55c..7d4b60b283e 100644
--- a/board/nxp/m5253demo/m5253demo.c
+++ b/board/nxp/m5253demo/m5253demo.c
@@ -133,10 +133,3 @@ void ide_set_reset(int idereset)
}
}
#endif /* CONFIG_IDE */
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(struct bd_info *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c
index ac91da3f4f6..036deb464b5 100644
--- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c
@@ -33,16 +33,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
@@ -55,48 +45,6 @@ int dram_init(void)
return 0;
}
-static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static int setup_fec(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
-
- return enable_fec_anatop_clock(1, ENET_125MHZ);
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int ret;
-
- imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
- setup_fec();
-
- ret = fecmxc_initialize_multi(bis, 1,
- CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
- if (ret)
- printf("FEC%d MXC: %s:failed\n", 1, __func__);
-
- return ret;
-}
-
int board_phy_config(struct phy_device *phydev)
{
/*
diff --git a/board/nxp/mx6sxsabresd/mx6sxsabresd.c b/board/nxp/mx6sxsabresd/mx6sxsabresd.c
index e3353feec68..cab0892affc 100644
--- a/board/nxp/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/nxp/mx6sxsabresd/mx6sxsabresd.c
@@ -40,16 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
@@ -71,84 +61,16 @@ static iomux_v3_cfg_t const uart1_pads[] = {
static iomux_v3_cfg_t const wdog_b_pad = {
MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
static iomux_v3_cfg_t const peri_3v3_pads[] = {
MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-static iomux_v3_cfg_t const phy_control_pads[] = {
- /* 25MHz Ethernet PHY Clock */
- MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-
- /* ENET PHY Power */
- MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
- /* AR8031 PHY Reset */
- MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
-static int setup_fec(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg, ret;
-
- /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
-
- ret = enable_fec_anatop_clock(0, ENET_125MHZ);
- if (ret)
- return ret;
-
- imx_iomux_v3_setup_multiple_pads(phy_control_pads,
- ARRAY_SIZE(phy_control_pads));
-
- /* Enable the ENET power, active low */
- gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
- gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
-
- /* Reset AR8031 PHY */
- gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
- gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
- mdelay(10);
- gpio_set_value(IMX_GPIO_NR(2, 7), 1);
-
- reg = readl(&anatop->pll_enet);
- reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
- writel(reg, &anatop->pll_enet);
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
- setup_fec();
-
- return cpu_eth_init(bis);
-}
-
int power_init_board(void)
{
struct udevice *dev;
diff --git a/board/nxp/p2041rdb/Makefile b/board/nxp/p2041rdb/Makefile
index ebd0982b5db..5512458832d 100644
--- a/board/nxp/p2041rdb/Makefile
+++ b/board/nxp/p2041rdb/Makefile
@@ -7,4 +7,3 @@
obj-y += p2041rdb.o
obj-y += cpld.o
obj-y += ddr.o
-obj-y += eth.o
diff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c
deleted file mode 100644
index d51b579b8b0..00000000000
--- a/board/nxp/p2041rdb/eth.c
+++ /dev/null
@@ -1,141 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Author: Mingkai Hu <Mingkai.hu@freescale.com>
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
- * are provided by the three on-board PHY or by the standard Freescale
- * four-port SGMII riser card. We need to change the phy-handle in the
- * kernel dts file to point to the correct PHY according to serdes mux
- * and serdes protocol selection.
- */
-
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-
-#include "cpld.h"
-#include "../common/fman.h"
-
-#ifdef CONFIG_FMAN_ENET
-/*
- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
- 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
-};
-
-static int riser_phy_addr[] = {
- CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
- CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
- CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
- CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the P2040RDB board the mapping is controlled by CPLD register.
- */
-static void initialize_lane_to_slot(void)
-{
- u8 mux = CPLD_READ(serdes_mux);
-
- lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
- lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
- lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
- lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
- struct tgec_mdio_info tgec_mdio_info;
- unsigned int i, slot;
- int lane;
-
- printf("Initializing Fman\n");
-
- initialize_lane_to_slot();
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the real 10G MDIO bus */
- fm_tgec_mdio_init(bis, &tgec_mdio_info);
-
- /*
- * Program the three on-board SGMII PHY addresses. If the SGMII Riser
- * card used, we'll override the PHY address later. For any DTSEC that
- * is RGMII, we'll also override its PHY address later. We assume that
- * DTSEC4 and DTSEC5 are used for RGMII.
- */
- fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- if (slot)
- fm_info_set_phy_address(i, riser_phy_addr[i]);
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
- fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
- CFG_SYS_FM1_DTSEC5_PHY_ADDR :
- CFG_SYS_FM1_DTSEC4_PHY_ADDR);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- break;
- }
-
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
- }
-
- lane = serdes_get_first_lane(XAUI_FM1);
- if (lane >= 0) {
- slot = lane_to_slot[lane];
- if (slot)
- fm_info_set_phy_address(FM1_10GEC1,
- CFG_SYS_FM1_10GEC1_PHY_ADDR);
- }
-
- fm_info_set_mdio(FM1_10GEC1,
- miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c
index 91f87983dc5..a07d242c1eb 100644
--- a/board/nxp/t102xrdb/eth_t102xrdb.c
+++ b/board/nxp/t102xrdb/eth_t102xrdb.c
@@ -26,109 +26,6 @@
#include <asm/fsl_serdes.h>
#include "../common/fman.h"
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
-
- switch (srds_s1) {
-#ifdef CONFIG_TARGET_T1024RDB
- case 0x95:
- /* set the on-board RGMII2 PHY */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
-
- /* set 10GBase-R with Aquantia AQR105 PHY */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- break;
-#endif
- case 0x6a:
- case 0x6b:
- case 0x77:
- case 0x135:
- /* set the on-board 2.5G SGMII AQR105 PHY */
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_TARGET_T1023RDB
- /* set the on-board 1G SGMII RTL8211F PHY */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
-#endif
- break;
- default:
- printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
- srds_s1);
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_TARGET_T1023RDB)
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_TARGET_T1024RDB)
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-#endif
- fm_info_set_mdio(i, dev);
- break;
- case PHY_INTERFACE_MODE_2500BASEX:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
-
void fdt_fixup_board_enet(void *fdt)
{
}
diff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile
index 9bca1a1fbcc..cee574aabb9 100644
--- a/board/nxp/t104xrdb/Makefile
+++ b/board/nxp/t104xrdb/Makefile
@@ -7,7 +7,6 @@ obj-y += spl.o
else
obj-y += t104xrdb.o
obj-y += cpld.o
-obj-y += eth.o
endif
obj-y += ddr.o
obj-y += law.o
diff --git a/board/nxp/t104xrdb/eth.c b/board/nxp/t104xrdb/eth.c
deleted file mode 100644
index c35ec368a45..00000000000
--- a/board/nxp/t104xrdb/eth.c
+++ /dev/null
@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-#include <vsc9953.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info memac_mdio_info;
- unsigned int i;
- int phy_addr = 0;
-
- printf("Initializing Fman\n");
-
- memac_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
- memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fm_memac_mdio_init(bis, &memac_mdio_info);
-
- /*
- * Program on board RGMII, SGMII PHY addresses.
- */
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1;
-
- switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_TARGET_T1042D4RDB
- case PHY_INTERFACE_MODE_SGMII:
- /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
- * & DTSEC3
- */
- if (FM1_DTSEC1 == i)
- phy_addr = CFG_SYS_SGMII1_PHY_ADDR;
- if (FM1_DTSEC2 == i)
- phy_addr = CFG_SYS_SGMII2_PHY_ADDR;
- if (FM1_DTSEC3 == i)
- phy_addr = CFG_SYS_SGMII3_PHY_ADDR;
- fm_info_set_phy_address(i, phy_addr);
- break;
-#endif
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- if (FM1_DTSEC4 == i)
- phy_addr = CFG_SYS_RGMII1_PHY_ADDR;
- if (FM1_DTSEC5 == i)
- phy_addr = CFG_SYS_RGMII2_PHY_ADDR;
- fm_info_set_phy_address(i, phy_addr);
- break;
- case PHY_INTERFACE_MODE_QSGMII:
- fm_info_set_phy_address(i, 0);
- break;
- case PHY_INTERFACE_MODE_NA:
- fm_info_set_phy_address(i, 0);
- break;
- default:
- printf("Fman1: DTSEC%u set to unknown interface %i\n",
- idx + 1, fm_info_get_enet_if(i));
- fm_info_set_phy_address(i, 0);
- break;
- }
- if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
- fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA)
- fm_info_set_mdio(i, NULL);
- else
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(
- DEFAULT_FM_MDIO_NAME));
- }
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c
index 12951df591e..e6aeb9bb66f 100644
--- a/board/nxp/t208xqds/eth_t208xqds.c
+++ b/board/nxp/t208xqds/eth_t208xqds.c
@@ -32,467 +32,7 @@
#include "t208xqds_qixis.h"
#include <linux/libfdt.h>
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_RGMII1 0
-#define EMI1_RGMII2 1
-#define EMI1_SLOT1 2
-#if defined(CONFIG_TARGET_T2080QDS)
-#define EMI1_SLOT2 6
-#define EMI1_SLOT3 3
-#define EMI1_SLOT4 4
-#define EMI1_SLOT5 5
-#define EMI2 7
-#endif
-
-#define PCCR1_SGMIIA_KX_MASK 0x00008000
-#define PCCR1_SGMIIB_KX_MASK 0x00004000
-#define PCCR1_SGMIIC_KX_MASK 0x00002000
-#define PCCR1_SGMIID_KX_MASK 0x00001000
-#define PCCR1_SGMIIE_KX_MASK 0x00000800
-#define PCCR1_SGMIIF_KX_MASK 0x00000400
-#define PCCR1_SGMIIG_KX_MASK 0x00000200
-#define PCCR1_SGMIIH_KX_MASK 0x00000100
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-#if defined(CONFIG_TARGET_T2080QDS)
- "T2080QDS_MDIO_RGMII1",
- "T2080QDS_MDIO_RGMII2",
- "T2080QDS_MDIO_SLOT1",
- "T2080QDS_MDIO_SLOT3",
- "T2080QDS_MDIO_SLOT4",
- "T2080QDS_MDIO_SLOT5",
- "T2080QDS_MDIO_SLOT2",
- "T2080QDS_MDIO_10GC",
-#endif
-};
-
-/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_TARGET_T2080QDS)
-static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#endif
-
-static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = t208xqds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-struct t208xqds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void t208xqds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
- if (muxval < 8) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
- int regnum)
-{
- struct t208xqds_mdio *priv = bus->priv;
-
- t208xqds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct t208xqds_mdio *priv = bus->priv;
-
- t208xqds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t208xqds_mdio_reset(struct mii_dev *bus)
-{
- struct t208xqds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int t208xqds_mdio_init(char *realbusname, u8 muxval)
-{
- struct t208xqds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate t208xqds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate t208xqds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = t208xqds_mdio_read;
- bus->write = t208xqds_mdio_write;
- bus->reset = t208xqds_mdio_reset;
- strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
- return mdio_register(bus);
-}
-
void fdt_fixup_board_enet(void *fdt)
{
return;
}
-
-/*
- * This function reads RCW to check if Serdes1{A:H} is configured
- * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- switch (srds_s1) {
-#if defined(CONFIG_TARGET_T2080QDS)
- case 0x51:
- case 0x5f:
- case 0x65:
- case 0x6b:
- case 0x71:
- lane_to_slot[5] = 2;
- lane_to_slot[6] = 2;
- lane_to_slot[7] = 2;
- break;
- case 0xa6:
- case 0x8e:
- case 0x8f:
- case 0x82:
- case 0x83:
- case 0xd3:
- case 0xd9:
- case 0xcb:
- lane_to_slot[6] = 2;
- lane_to_slot[7] = 2;
- break;
- case 0xda:
- lane_to_slot[4] = 3;
- lane_to_slot[5] = 3;
- lane_to_slot[6] = 3;
- lane_to_slot[7] = 3;
- break;
-#endif
- default:
- break;
- }
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, idx, lane, slot, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- initialize_lane_to_slot();
-
- /* Initialize the mdio_mux array so we can recognize empty elements */
- for (i = 0; i < NUM_FM_PORTS; i++)
- mdio_mux[i] = EMI_NONE;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_TARGET_T2080QDS)
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-#endif
- t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
- FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
- else
- fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
-
- switch (srds_s1) {
- case 0x1b:
- case 0x1c:
- case 0x95:
- case 0xa2:
- case 0x94:
- /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- case 0x50:
- case 0x51:
- case 0x5e:
- case 0x5f:
- case 0x64:
- case 0x65:
- /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- case 0x66:
- case 0x67:
- /*
- * 10GBase-R does not need a PHY to work, but to avoid U-Boot
- * use default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to 10GBase-R
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the 10GBase-R MAC, which will cause
- * error.
- */
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_10GEC2, 5);
- fm_info_set_phy_address(FM1_10GEC3, 6);
- fm_info_set_phy_address(FM1_10GEC4, 7);
- break;
- case 0x6a:
- case 0x6b:
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_10GEC2, 5);
- fm_info_set_phy_address(FM1_10GEC3, 6);
- fm_info_set_phy_address(FM1_10GEC4, 7);
- /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
- case 0x6c:
- case 0x6d:
- fm_info_set_phy_address(FM1_10GEC1, 4);
- fm_info_set_phy_address(FM1_10GEC2, 5);
- /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- case 0x70:
- case 0x71:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
- case 0xa6:
- case 0x8e:
- case 0x8f:
- case 0x82:
- case 0x83:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
- case 0xa4:
- case 0x96:
- case 0x8a:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- break;
-#if defined(CONFIG_TARGET_T2080QDS)
- case 0xd9:
- case 0xd3:
- case 0xcb:
- /* SGMII in Slot3 */
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- break;
-#endif
- case 0xf2:
- /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
- break;
- default:
- break;
- }
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
- idx = i - FM1_DTSEC1;
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
- SGMII_FM1_DTSEC1 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot[lane];
- debug("FM1@DTSEC%u expects SGMII in slot %u\n",
- idx + 1, slot);
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
-
- switch (slot) {
- case 1:
- mdio_mux[i] = EMI1_SLOT1;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 2:
- mdio_mux[i] = EMI1_SLOT2;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- case 3:
- mdio_mux[i] = EMI1_SLOT3;
- fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
- break;
- }
- break;
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- if (i == FM1_DTSEC3)
- mdio_mux[i] = EMI1_RGMII1;
- else if (i == FM1_DTSEC4 || FM1_DTSEC10)
- mdio_mux[i] = EMI1_RGMII2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
- idx = i - FM1_10GEC1;
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- if (srds_s1 == 0x51) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XAUI_FM1_MAC9 + idx);
- } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
- lane = serdes_get_first_lane(FSL_SRDS_1,
- HIGIG_FM1_MAC9 + idx);
- } else {
- if (i == FM1_10GEC1 || i == FM1_10GEC2)
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XFI_FM1_MAC9 + idx);
- else
- lane = serdes_get_first_lane(FSL_SRDS_1,
- XFI_FM1_MAC1 + idx);
- }
-
- if (lane < 0)
- break;
- mdio_mux[i] = EMI2;
- fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-
- if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
- (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
- (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
- (srds_s1 == 0x71)) {
- /* As 10GBase-R is in cage intead of a slot, so
- * ensure doesn't disable the corresponding port
- */
- break;
- }
-
- slot = lane_to_slot[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
- break;
- default:
- break;
- }
- }
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c
index e7646365d7d..dc2390f1003 100644
--- a/board/nxp/t4rdb/eth.c
+++ b/board/nxp/t4rdb/eth.c
@@ -35,118 +35,3 @@ void fdt_fixup_board_enet(void *fdt)
{
return;
}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
- /* SGMII */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
- fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
- } else {
- puts("Invalid SerDes1 protocol for T4240RDB\n");
- }
-
- fm_disable_port(FM1_DTSEC5);
- fm_disable_port(FM1_DTSEC6);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
-#if (CFG_SYS_NUM_FMAN == 2)
- if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
- /* SGMII && 10GBase-R */
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
- } else {
- puts("Invalid SerDes2 protocol for T4240RDB\n");
- }
-
- fm_disable_port(FM2_DTSEC5);
- fm_disable_port(FM2_DTSEC6);
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-#endif /* CFG_SYS_NUM_FMAN */
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 06/11] boards/nxp: remove empty fdt_fixup_board_enet()
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (4 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 05/11] boards/nxp: remove board_eth_init() Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 07/11] p2041rdb: use the upstream device tree Michael Walle
` (5 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
Remove any empty function which is just called by the board code. There
is no need to define this function at all.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
board/nxp/ls1043aqds/Makefile | 3 ---
board/nxp/ls1043aqds/eth.c | 11 ---------
board/nxp/ls1043aqds/ls1043aqds.c | 4 ----
board/nxp/ls1046aqds/Makefile | 3 ---
board/nxp/ls1046aqds/eth.c | 11 ---------
board/nxp/ls1046aqds/ls1046aqds.c | 4 ----
board/nxp/t102xrdb/Makefile | 1 -
board/nxp/t102xrdb/eth_t102xrdb.c | 31 -------------------------
board/nxp/t102xrdb/t102xrdb.c | 1 -
board/nxp/t102xrdb/t102xrdb.h | 1 -
board/nxp/t104xrdb/t104xrdb.h | 1 -
board/nxp/t208xqds/Makefile | 2 +-
board/nxp/t208xqds/eth_t208xqds.c | 38 -------------------------------
board/nxp/t208xqds/t208xqds.c | 1 -
board/nxp/t208xqds/t208xqds.h | 1 -
board/nxp/t208xrdb/eth_t208xrdb.c | 5 ----
board/nxp/t208xrdb/t208xrdb.c | 1 -
board/nxp/t208xrdb/t208xrdb.h | 1 -
board/nxp/t4rdb/Makefile | 1 -
board/nxp/t4rdb/eth.c | 37 ------------------------------
board/nxp/t4rdb/t4240rdb.c | 1 -
board/nxp/t4rdb/t4rdb.h | 1 -
22 files changed, 1 insertion(+), 159 deletions(-)
delete mode 100644 board/nxp/ls1043aqds/eth.c
delete mode 100644 board/nxp/ls1046aqds/eth.c
delete mode 100644 board/nxp/t102xrdb/eth_t102xrdb.c
delete mode 100644 board/nxp/t208xqds/eth_t208xqds.c
delete mode 100644 board/nxp/t4rdb/eth.c
diff --git a/board/nxp/ls1043aqds/Makefile b/board/nxp/ls1043aqds/Makefile
index ff830788fd7..98ad49f6f0c 100644
--- a/board/nxp/ls1043aqds/Makefile
+++ b/board/nxp/ls1043aqds/Makefile
@@ -5,7 +5,4 @@
#
obj-y += ddr.o
-ifndef CONFIG_XPL_BUILD
-obj-y += eth.o
-endif
obj-y += ls1043aqds.o
diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c
deleted file mode 100644
index d62cf74732c..00000000000
--- a/board/nxp/ls1043aqds/eth.c
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
- */
-
-#include <fdt_support.h>
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}
diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c
index f043599fbb8..0f115c16232 100644
--- a/board/nxp/ls1043aqds/ls1043aqds.c
+++ b/board/nxp/ls1043aqds/ls1043aqds.c
@@ -550,10 +550,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_FMAN_ENET
- fdt_fixup_board_enet(blob);
-#endif
-
fdt_fixup_icid(blob);
reg = QIXIS_READ(brdcfg[0]);
diff --git a/board/nxp/ls1046aqds/Makefile b/board/nxp/ls1046aqds/Makefile
index 365247d92bc..8292726b0e4 100644
--- a/board/nxp/ls1046aqds/Makefile
+++ b/board/nxp/ls1046aqds/Makefile
@@ -5,7 +5,4 @@
#
obj-y += ddr.o
-ifndef CONFIG_XPL_BUILD
-obj-y += eth.o
-endif
obj-y += ls1046aqds.o
diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c
deleted file mode 100644
index 24e6c93aece..00000000000
--- a/board/nxp/ls1046aqds/eth.c
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018-2020 NXP
- */
-
-#include <fdt_support.h>
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}
diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c
index 7df12550868..679b0b2235f 100644
--- a/board/nxp/ls1046aqds/ls1046aqds.c
+++ b/board/nxp/ls1046aqds/ls1046aqds.c
@@ -434,10 +434,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_FMAN_ENET
- fdt_fixup_board_enet(blob);
-#endif
-
fdt_fixup_icid(blob);
reg = QIXIS_READ(brdcfg[0]);
diff --git a/board/nxp/t102xrdb/Makefile b/board/nxp/t102xrdb/Makefile
index b0f27c47191..2a360227418 100644
--- a/board/nxp/t102xrdb/Makefile
+++ b/board/nxp/t102xrdb/Makefile
@@ -9,7 +9,6 @@ obj-y += spl.o
else
obj-y += t102xrdb.o
obj-$(CONFIG_TARGET_T1024RDB) += cpld.o
-obj-y += eth_t102xrdb.o
endif
obj-y += ddr.o
obj-y += law.o
diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c
deleted file mode 100644
index a07d242c1eb..00000000000
--- a/board/nxp/t102xrdb/eth_t102xrdb.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <config.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include "../common/fman.h"
-
-void fdt_fixup_board_enet(void *fdt)
-{
-}
diff --git a/board/nxp/t102xrdb/t102xrdb.c b/board/nxp/t102xrdb/t102xrdb.c
index 0a29e27b42c..02223497dd3 100644
--- a/board/nxp/t102xrdb/t102xrdb.c
+++ b/board/nxp/t102xrdb/t102xrdb.c
@@ -207,7 +207,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
- fdt_fixup_board_enet(blob);
#endif
#ifdef CONFIG_TARGET_T1023RDB
diff --git a/board/nxp/t102xrdb/t102xrdb.h b/board/nxp/t102xrdb/t102xrdb.h
index 33df0f24df8..71e2cfea22e 100644
--- a/board/nxp/t102xrdb/t102xrdb.h
+++ b/board/nxp/t102xrdb/t102xrdb.h
@@ -6,7 +6,6 @@
#ifndef __T1024_RDB_H__
#define __T1024_RDB_H__
-void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
#ifdef CONFIG_TARGET_T1023RDB
static u32 t1023rdb_ctrl(u32 ctrl_type);
diff --git a/board/nxp/t104xrdb/t104xrdb.h b/board/nxp/t104xrdb/t104xrdb.h
index 678724c7e2b..5825e69cdb4 100644
--- a/board/nxp/t104xrdb/t104xrdb.h
+++ b/board/nxp/t104xrdb/t104xrdb.h
@@ -6,7 +6,6 @@
#ifndef __T104x_RDB_H__
#define __T104x_RDB_H__
-void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
#endif
diff --git a/board/nxp/t208xqds/Makefile b/board/nxp/t208xqds/Makefile
index eb99d921b4a..4bfd2b50d8f 100644
--- a/board/nxp/t208xqds/Makefile
+++ b/board/nxp/t208xqds/Makefile
@@ -7,7 +7,7 @@
ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o
endif
obj-y += ddr.o
diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c
deleted file mode 100644
index e6aeb9bb66f..00000000000
--- a/board/nxp/t208xqds/eth_t208xqds.c
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- *
- * Shengzhou Liu <Shengzhou.Liu@freescale.com>
- */
-
-#include <config.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t208xqds_qixis.h"
-#include <linux/libfdt.h>
-
-void fdt_fixup_board_enet(void *fdt)
-{
- return;
-}
diff --git a/board/nxp/t208xqds/t208xqds.c b/board/nxp/t208xqds/t208xqds.c
index 5e71da0e163..329cf59793f 100644
--- a/board/nxp/t208xqds/t208xqds.c
+++ b/board/nxp/t208xqds/t208xqds.c
@@ -419,7 +419,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
- fdt_fixup_board_enet(blob);
#endif
return 0;
diff --git a/board/nxp/t208xqds/t208xqds.h b/board/nxp/t208xqds/t208xqds.h
index 50ebb6f6f98..4086f8c010a 100644
--- a/board/nxp/t208xqds/t208xqds.h
+++ b/board/nxp/t208xqds/t208xqds.h
@@ -6,7 +6,6 @@
#ifndef __CORENET_DS_H__
#define __CORENET_DS_H__
-void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
#endif
diff --git a/board/nxp/t208xrdb/eth_t208xrdb.c b/board/nxp/t208xrdb/eth_t208xrdb.c
index 5223eccb280..c9e415bc446 100644
--- a/board/nxp/t208xrdb/eth_t208xrdb.c
+++ b/board/nxp/t208xrdb/eth_t208xrdb.c
@@ -93,8 +93,3 @@ void fdt_fixup_board_phy(void *fdt)
printf("Unable to rename node ethernet-phy@1: %s\n",
fdt_strerror(ret));
}
-
-void fdt_fixup_board_enet(void *fdt)
-{
- return;
-}
diff --git a/board/nxp/t208xrdb/t208xrdb.c b/board/nxp/t208xrdb/t208xrdb.c
index d93edf007ad..d47ec91e7d0 100644
--- a/board/nxp/t208xrdb/t208xrdb.c
+++ b/board/nxp/t208xrdb/t208xrdb.c
@@ -160,7 +160,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_board_fman_ethernet(blob);
- fdt_fixup_board_enet(blob);
fdt_fixup_board_phy(blob);
#endif
diff --git a/board/nxp/t208xrdb/t208xrdb.h b/board/nxp/t208xrdb/t208xrdb.h
index 26998898e82..e800270a0e2 100644
--- a/board/nxp/t208xrdb/t208xrdb.h
+++ b/board/nxp/t208xrdb/t208xrdb.h
@@ -10,7 +10,6 @@
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000
-void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
void fdt_fixup_board_fman_ethernet(void *blob);
void fdt_fixup_board_phy(void *blob);
diff --git a/board/nxp/t4rdb/Makefile b/board/nxp/t4rdb/Makefile
index 8d94faaba1c..6d9b8df2fc1 100644
--- a/board/nxp/t4rdb/Makefile
+++ b/board/nxp/t4rdb/Makefile
@@ -9,7 +9,6 @@ obj-y += spl.o
else
obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
obj-y += cpld.o
-obj-y += eth.o
endif
obj-y += ddr.o
diff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c
deleted file mode 100644
index dc2390f1003..00000000000
--- a/board/nxp/t4rdb/eth.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <config.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-
-#include "../common/fman.h"
-#include "t4rdb.h"
-
-void fdt_fixup_board_enet(void *fdt)
-{
- return;
-}
diff --git a/board/nxp/t4rdb/t4240rdb.c b/board/nxp/t4rdb/t4240rdb.c
index 5cacfd27380..11e2c0f78b7 100644
--- a/board/nxp/t4rdb/t4240rdb.c
+++ b/board/nxp/t4rdb/t4240rdb.c
@@ -128,7 +128,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
- fdt_fixup_board_enet(blob);
#endif
return 0;
diff --git a/board/nxp/t4rdb/t4rdb.h b/board/nxp/t4rdb/t4rdb.h
index bb3ce216d7d..9ec190c03cb 100644
--- a/board/nxp/t4rdb/t4rdb.h
+++ b/board/nxp/t4rdb/t4rdb.h
@@ -14,7 +14,6 @@
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000
-void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
#endif
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 07/11] p2041rdb: use the upstream device tree
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (5 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 06/11] boards/nxp: remove empty fdt_fixup_board_enet() Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 08/11] p2041rdb: support SDcard boot Michael Walle
` (4 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
Switch to the upstream device tree, which already includes the UART
nodes we need for the DM.
We also need to increase malloc area before relocation otherwise you'll
get the following error and the board panics:
DRAM: Initializing....using SPD
alloc space exhausted ptr 414 limit 400
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/p2041.dtsi | 138 --------------------------
arch/powerpc/dts/p2041rdb-u-boot.dtsi | 19 ++++
arch/powerpc/dts/p2041rdb.dts | 127 ------------------------
arch/powerpc/dts/p2041si-post.dtsi | 43 --------
configs/P2041RDB_SPIFLASH_defconfig | 4 +-
configs/P2041RDB_defconfig | 4 +-
include/configs/P2041RDB.h | 2 +
8 files changed, 27 insertions(+), 311 deletions(-)
delete mode 100644 arch/powerpc/dts/p2041.dtsi
create mode 100644 arch/powerpc/dts/p2041rdb-u-boot.dtsi
delete mode 100644 arch/powerpc/dts/p2041rdb.dts
delete mode 100644 arch/powerpc/dts/p2041si-post.dtsi
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 766b0c05951..4fd3478ac2f 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
-dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
deleted file mode 100644
index ad09b138fc8..00000000000
--- a/arch/powerpc/dts/p2041.dtsi
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2041 Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-/include/ "e500mc_power_isa.dtsi"
-
-/ {
- compatible = "fsl,P2041";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: PowerPC,e500mc@0 {
- device_type = "cpu";
- reg = <0>;
- fsl,portid-mapping = <0x80000000>;
- };
- cpu1: PowerPC,e500mc@1 {
- device_type = "cpu";
- reg = <1>;
- fsl,portid-mapping = <0x40000000>;
- };
- cpu2: PowerPC,e500mc@2 {
- device_type = "cpu";
- reg = <2>;
- fsl,portid-mapping = <0x20000000>;
- };
- cpu3: PowerPC,e500mc@3 {
- device_type = "cpu";
- reg = <3>;
- fsl,portid-mapping = <0x10000000>;
- };
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <4>;
- reg = <0x40000 0x40000>;
- compatible = "fsl,mpic", "chrp,open-pic";
- device_type = "open-pic";
- clock-frequency = <0x0>;
- };
-
- espi0: spi@110000 {
- compatible = "fsl,mpc8536-espi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x110000 0x1000>;
- fsl,espi-num-chipselects = <4>;
- status = "disabled";
- };
-
- usb0: usb@210000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "utmi";
- };
-
- usb1: usb@211000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "utmi";
- };
-
- sata: sata@220000 {
- compatible = "fsl,pq-sata-v2";
- reg = <0x220000 0x1000>;
- interrupts = <68 0x2 0 0>;
- sata-offset = <0x1000>;
- sata-number = <2>;
- sata-fpdma = <0>;
- };
-
- esdhc: esdhc@114000 {
- compatible = "fsl,esdhc";
- reg = <0x114000 0x1000>;
- clock-frequency = <0>;
- };
-
- /include/ "qoriq-i2c-0.dtsi"
- /include/ "qoriq-i2c-1.dtsi"
- };
-
- pcie@ffe200000 {
- compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
- law_trgt_if = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe201000 {
- compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
- law_trgt_if = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe202000 {
- compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
- law_trgt_if = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-};
diff --git a/arch/powerpc/dts/p2041rdb-u-boot.dtsi b/arch/powerpc/dts/p2041rdb-u-boot.dtsi
new file mode 100644
index 00000000000..1dc83cf846b
--- /dev/null
+++ b/arch/powerpc/dts/p2041rdb-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&serial0 {
+ bootph-all;
+};
+
+&soc {
+ i2c@118000 {
+ bootph-all;
+ };
+
+ spi@110000 {
+ flash@0 {
+ spi-max-frequency = <10000000>;
+ };
+ };
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts
deleted file mode 100644
index 0fa1f098524..00000000000
--- a/arch/powerpc/dts/p2041rdb.dts
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2041RDB Device Tree Source
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/include/ "p2041.dtsi"
-
-/ {
- model = "fsl,P2041RDB";
- compatible = "fsl,P2041RDB";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- aliases {
- phy_rgmii_0 = &phy_rgmii_0;
- phy_rgmii_1 = &phy_rgmii_1;
- phy_sgmii_2 = &phy_sgmii_2;
- phy_sgmii_3 = &phy_sgmii_3;
- phy_sgmii_4 = &phy_sgmii_4;
- phy_sgmii_1c = &phy_sgmii_1c;
- phy_sgmii_1d = &phy_sgmii_1d;
- phy_sgmii_1e = &phy_sgmii_1e;
- phy_sgmii_1f = &phy_sgmii_1f;
- phy_xgmii_2 = &phy_xgmii_2;
- spi0 = &espi0;
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
-
- fman@400000 {
- ethernet@e0000 {
- phy-handle = <&phy_sgmii_2>;
- phy-connection-type = "sgmii";
- };
-
- mdio@e1120 {
- phy_rgmii_0: ethernet-phy@0 {
- reg = <0x0>;
- };
-
- phy_rgmii_1: ethernet-phy@1 {
- reg = <0x1>;
- };
-
- phy_sgmii_2: ethernet-phy@2 {
- reg = <0x2>;
- };
-
- phy_sgmii_3: ethernet-phy@3 {
- reg = <0x3>;
- };
-
- phy_sgmii_4: ethernet-phy@4 {
- reg = <0x4>;
- };
-
- phy_sgmii_1c: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy_sgmii_1d: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy_sgmii_1e: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy_sgmii_1f: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
-
- ethernet@e2000 {
- phy-handle = <&phy_sgmii_3>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-handle = <&phy_sgmii_4>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-handle = <&phy_rgmii_1>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@e8000 {
- phy-handle = <&phy_rgmii_0>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@f0000 {
- phy-handle = <&phy_xgmii_2>;
- phy-connection-type = "xgmii";
- };
-
- mdio@f1000 {
- phy_xgmii_2: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- };
- };
- };
- };
-};
-
-&espi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- /* input clock */
- spi-max-frequency = <10000000>;
- };
-};
-
-/include/ "p2041si-post.dtsi"
diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi
deleted file mode 100644
index 8819199646f..00000000000
--- a/arch/powerpc/dts/p2041si-post.dtsi
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * P2041/P2040 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2020 NXP
- *
- */
-
-&soc {
-
-/include/ "qoriq-clockgen1.dtsi"
-/include/ "qoriq-gpio-0.dtsi"
-/include/ "qoriq-sec4.2-0.dtsi"
-
-/* include used FMan blocks */
-/include/ "qoriq-fman-0.dtsi"
-/include/ "qoriq-fman-0-1g-0.dtsi"
-/include/ "qoriq-fman-0-1g-1.dtsi"
-/include/ "qoriq-fman-0-1g-2.dtsi"
-/include/ "qoriq-fman-0-1g-3.dtsi"
-/include/ "qoriq-fman-0-1g-4.dtsi"
-/include/ "qoriq-fman-0-10g-0.dtsi"
- fman@400000 {
- enet0: ethernet@e0000 {
- };
-
- enet1: ethernet@e2000 {
- };
-
- enet2: ethernet@e4000 {
- };
-
- enet3: ethernet@e6000 {
- };
-
- enet4: ethernet@e8000 {
- };
-
- enet5: ethernet@f0000 {
- };
- };
-};
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 1b7389178be..465b3ee7dc7 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -1,11 +1,12 @@
CONFIG_PPC=y
CONFIG_TEXT_BASE=0xFFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
+CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
@@ -56,6 +57,7 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index b6c28db4f10..9c3e95093bf 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -1,10 +1,11 @@
CONFIG_PPC=y
CONFIG_TEXT_BASE=0xEFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
+CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
@@ -52,6 +53,7 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_USE_BOOTFILE=y
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f88fb9cdb9a..3525e29acc4 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -149,6 +149,8 @@
* shorted - index 1
*/
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 08/11] p2041rdb: support SDcard boot
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (6 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 07/11] p2041rdb: use the upstream device tree Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 09/11] p2041rdb: update README and fix typos Michael Walle
` (3 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
The RCW was just supporting SPI boot. Add a second one for the SDcard
boot. While at it, use the same naming scheme as for the other NXP
boards.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg | 11 +++++++++++
.../{rcw_p2041rdb.cfg => p2041rdb_rcw_spi.cfg} | 0
configs/P2041RDB_SDCARD_defconfig | 6 ++++--
configs/P2041RDB_SPIFLASH_defconfig | 2 +-
4 files changed, 16 insertions(+), 3 deletions(-)
create mode 100644 board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg
rename board/nxp/p2041rdb/{rcw_p2041rdb.cfg => p2041rdb_rcw_spi.cfg} (100%)
diff --git a/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg
new file mode 100644
index 00000000000..f22f3335e73
--- /dev/null
+++ b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P2041RDB.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+649FA0C1 C3C02000 68000000 40000000
+00000000 00000000 00000000 D0030F07
+00000000 00000000 00000000 00000000
diff --git a/board/nxp/p2041rdb/rcw_p2041rdb.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg
similarity index 100%
rename from board/nxp/p2041rdb/rcw_p2041rdb.cfg
rename to board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index ad04e2a1172..88695e1cabe 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -1,10 +1,11 @@
CONFIG_PPC=y
CONFIG_TEXT_BASE=0xFFF40000
CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SYS_MALLOC_F_LEN=0x600
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xCF400
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
+CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MPC85xx=y
CONFIG_SYS_INIT_RAM_LOCK=y
@@ -28,7 +29,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg"
CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -54,6 +55,7 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 465b3ee7dc7..fc187eb311c 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -31,7 +31,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg"
CONFIG_BOOTDELAY=10
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 09/11] p2041rdb: update README and fix typos
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (7 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 08/11] p2041rdb: support SDcard boot Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 10/11] p2041rdb: remove NAND defconfig Michael Walle
` (2 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
Nowadays, u-boot can build the pbl image itself. Refer to that image in
the documentation. Also fix some typos.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
board/nxp/p2041rdb/README | 34 ++++++++++++----------------------
1 file changed, 12 insertions(+), 22 deletions(-)
diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README
index ae770277372..c2a2f0ed9e5 100644
--- a/board/nxp/p2041rdb/README
+++ b/board/nxp/p2041rdb/README
@@ -43,20 +43,16 @@ Boot from SDCard
make P2041RDB_SDCARD_config
make all
-2. Generate PBL imge
- Use PE tool to produce a image used to be programed to
- SDCard which contains RCW and U-Boot image.
-
-3. Program the PBL image to SDCard
- => tftp 1000000 pbl_sd.bin
- => mmcinfo
+2. Program the PBL image to SDCard
+ => tftp 1000000 u-boot.pbl
+ => mmc info
=> mmc write 1000000 8 672
-4. Program FMAN Firmware ucode
+3. Program FMAN Firmware ucode
=> tftp 1000000 ucode.bin
=> mmc write 1000000 690 10
-5. Change DIP-switch
+4. Change DIP-switch
SW1[1-5] = 01100
Note: 1 stands for 'on', 0 stands for 'off'
@@ -66,22 +62,16 @@ Boot from SPI flash
make P2041RDB_SPIFLASH_config
make all
-2. Generate PBL imge
- Use PE tool to produce a image used to be programed to
- SPI flash which contains RCW and U-Boot image.
+2. Program the PBL image to SPI flash
+ => tftp 1000000 u-boot.pbl
+ => sf probe 0
+ => sf update $fileaddr 0 $filesize
-3. Program the PBL image to SPI flash
- => tftp 1000000 pbl_spi.bin
- => spi probe 0
- => sf erase 0 100000
- => sf write 1000000 0 $filesize
-
-4. Program FMAN Firmware ucode
+3. Program FMAN Firmware ucode
=> tftp 1000000 ucode.bin
- => sf erase 110000 10000
- => sf write 1000000 110000 $filesize
+ => sf update $fileaddr 110000 $filesize
-5. Change DIP-switch
+4. Change DIP-switch
SW1[1-5] = 10100
Note: 1 stands for 'on', 0 stands for 'off'
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 10/11] p2041rdb: remove NAND defconfig
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (8 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 09/11] p2041rdb: update README and fix typos Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-06 12:34 ` [PATCH v2 11/11] p2041rdb: convert README to rst Michael Walle
2026-05-15 4:30 ` [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Peng Fan
11 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
The RDB doesn't support NAND boot at all, remove the config for it.
Apparently, it was introduced by commit dd84058d24ff ("kconfig: add
board Kconfig and defconfig files") which ran some scripts. Maybe that
script was wrong or the source boards.cfg was wrong. In any case, there
is no NAND flash on the RDB.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
configs/P2041RDB_NAND_defconfig | 117 --------------------------------
1 file changed, 117 deletions(-)
delete mode 100644 configs/P2041RDB_NAND_defconfig
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
deleted file mode 100644
index 1bef841990f..00000000000
--- a/configs/P2041RDB_NAND_defconfig
+++ /dev/null
@@ -1,117 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0xFFF40000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_SYS_SRIO=y
-CONFIG_SRIO1=y
-CONFIG_SRIO2=y
-CONFIG_SRIO_PCIE_BOOT_MASTER=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_CACHE_STASHING=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=2
-CONFIG_MP=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg"
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_ID_EEPROM=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC1"
-CONFIG_USE_ROOTPATH=y
-CONFIG_FSL_SATA_V2=y
-CONFIG_SYS_SATA_MAX_DEVICE=2
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFFA00C21
-CONFIG_SYS_OR0_PRELIM=0xFFFC0796
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8001001
-CONFIG_SYS_OR1_PRELIM=0xF8000F85
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_ELBC=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x100000
-CONFIG_MII=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_MAX_CONTROLLER_COUNT=2
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_POST=y
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 11/11] p2041rdb: convert README to rst
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (9 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 10/11] p2041rdb: remove NAND defconfig Michael Walle
@ 2026-05-06 12:34 ` Michael Walle
2026-05-08 12:25 ` Quentin Schulz
2026-05-15 4:30 ` [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Peng Fan
11 siblings, 1 reply; 14+ messages in thread
From: Michael Walle @ 2026-05-06 12:34 UTC (permalink / raw)
To: Marek Behún, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot, Michael Walle
Convert the README to reST format.
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
board/nxp/p2041rdb/README | 128 -----------------------------
board/nxp/p2041rdb/README.rst | 147 ++++++++++++++++++++++++++++++++++
2 files changed, 147 insertions(+), 128 deletions(-)
delete mode 100644 board/nxp/p2041rdb/README
create mode 100644 board/nxp/p2041rdb/README.rst
diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README
deleted file mode 100644
index c2a2f0ed9e5..00000000000
--- a/board/nxp/p2041rdb/README
+++ /dev/null
@@ -1,128 +0,0 @@
-Overview
-=========
-The P2041 Processor combines four Power Architecture processor cores
-with high-performance datapath acceleration architecture(DPAA), CoreNet
-fabric infrastructure, as well as network and peripheral bus interfaces
-required for networking, telecom/datacom, wireless infrastructure, and
-military/aerospace applications.
-
-P2041RDB board is a quad core platform supporting the P2041 processor
-of QorIQ DPAA series.
-
-Boot from NOR flash
-===================
-1. Build image
- make P2041RDB_config
- make all
-
-2. Program image
- => tftp 1000000 u-boot.bin
- => protect off all
- => erase eff40000 efffffff
- => cp.b 1000000 eff40000 c0000
-
-3. Program RCW
- => tftp 1000000 rcw.bin
- => protect off all
- => erase e8000000 e801ffff
- => cp.b 1000000 e8000000 50
-
-4. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => protect off all
- => erase eff00000 eff3ffff
- => cp.b 1000000 eff00000 2000
-
-5. Change DIP-switch
- SW1[1-5] = 10110
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SDCard
-===================
-1. Build image
- make P2041RDB_SDCARD_config
- make all
-
-2. Program the PBL image to SDCard
- => tftp 1000000 u-boot.pbl
- => mmc info
- => mmc write 1000000 8 672
-
-3. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => mmc write 1000000 690 10
-
-4. Change DIP-switch
- SW1[1-5] = 01100
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Boot from SPI flash
-===================
-1. Build image
- make P2041RDB_SPIFLASH_config
- make all
-
-2. Program the PBL image to SPI flash
- => tftp 1000000 u-boot.pbl
- => sf probe 0
- => sf update $fileaddr 0 $filesize
-
-3. Program FMAN Firmware ucode
- => tftp 1000000 ucode.bin
- => sf update $fileaddr 110000 $filesize
-
-4. Change DIP-switch
- SW1[1-5] = 10100
- Note: 1 stands for 'on', 0 stands for 'off'
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for p2041rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CFG_RESET_VECTOR_ADDRESS - 0xffc
-
-CPLD command
-============
-The CPLD is used to control the power sequence and some serdes lane
-mux function.
-
-cpld reset - hard reset to default bank
-cpld reset altbank - reset to alternate bank
-cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
- lane 6: 0 -> slot1 (Default)
- 1 -> SGMII
- lane a: 0 -> slot2 (Default)
- 1 -> AURORA
- lane c: 0 -> slot2 (Default)
- 1 -> SATA0
- lane d: 0 -> slot2 (Default)
- 1 -> SATA1
-
-Using the Device Tree Source File
-=================================
-To create the DTB (Device Tree Binary) image file, use a command
-similar to this:
- dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
-
-Or use the following command:
- {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
-
-then the dtb file will be generated under the following directory:
- {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
-
-Booting Linux
-=============
-Place a linux uImage in the TFTP disk area.
- tftp 1000000 uImage
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp 3000000 p2041rdb.dtb
- bootm 1000000 2000000 3000000
diff --git a/board/nxp/p2041rdb/README.rst b/board/nxp/p2041rdb/README.rst
new file mode 100644
index 00000000000..8b8214adc57
--- /dev/null
+++ b/board/nxp/p2041rdb/README.rst
@@ -0,0 +1,147 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+P2041-RDB Board Overview
+========================
+
+The P2041 Processor combines four Power Architecture processor cores
+with high-performance datapath acceleration architecture(DPAA), CoreNet
+fabric infrastructure, as well as network and peripheral bus interfaces
+required for networking, telecom/datacom, wireless infrastructure, and
+military/aerospace applications.
+
+P2041RDB board is a quad core platform supporting the P2041 processor
+of QorIQ DPAA series.
+
+Boot from NOR flash
+===================
+
+1. Build image::
+
+ make P2041RDB_config
+ make all
+
+2. Program image::
+
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff40000 efffffff
+ => cp.b 1000000 eff40000 c0000
+
+3. Program RCW::
+
+ => tftp 1000000 rcw.bin
+ => protect off all
+ => erase e8000000 e801ffff
+ => cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode::
+
+ => tftp 1000000 ucode.bin
+ => protect off all
+ => erase eff00000 eff3ffff
+ => cp.b 1000000 eff00000 2000
+
+5. Change DIP-switch to SW1[1-5] = 10110. Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SDCard
+================
+
+1. Build image::
+
+ make P2041RDB_SDCARD_config
+ make all
+
+2. Program the PBL image to SDCard::
+
+ => tftp 1000000 u-boot.pbl
+ => mmc info
+ => mmc write 1000000 8 672
+
+3. Program FMAN Firmware ucode::
+
+ => tftp 1000000 ucode.bin
+ => mmc write 1000000 690 10
+
+4. Change DIP-switch to SW1[1-5] = 01100. Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SPI flash
+===================
+
+1. Build image::
+
+ make P2041RDB_SPIFLASH_config
+ make all
+
+2. Program the PBL image to SPI flash::
+
+ => tftp 1000000 u-boot.pbl
+ => sf probe 0
+ => sf update $fileaddr 0 $filesize
+
+3. Program FMAN Firmware ucode::
+
+ => tftp 1000000 ucode.bin
+ => sf update $fileaddr 110000 $filesize
+
+4. Change DIP-switch SW1[1-5] = 10100. Note: 1 stands for 'on', 0 stands for 'off'
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+
+Device tree support is available for p2041rdb for below mentioned boot,
+
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+
+1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CFG_RESET_VECTOR_ADDRESS - 0xffc
+
+CPLD command
+============
+
+The CPLD is used to control the power sequence and some serdes lane
+mux function::
+
+ cpld reset - hard reset to default bank
+ cpld reset altbank - reset to alternate bank
+ cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
+ lane 6: 0 -> slot1 (Default)
+ 1 -> SGMII
+ lane a: 0 -> slot2 (Default)
+ 1 -> AURORA
+ lane c: 0 -> slot2 (Default)
+ 1 -> SATA0
+ lane d: 0 -> slot2 (Default)
+ 1 -> SATA1
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this::
+
+ dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
+
+Or use the following command::
+
+ {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory::
+
+ {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
+
+Booting Linux
+=============
+
+Place a linux uImage in the TFTP disk area::
+
+ => tftp 1000000 uImage
+ => tftp 2000000 rootfs.ext2.gz.uboot
+ => tftp 3000000 p2041rdb.dtb
+ => bootm 1000000 2000000 3000000
--
2.47.3
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 11/11] p2041rdb: convert README to rst
2026-05-06 12:34 ` [PATCH v2 11/11] p2041rdb: convert README to rst Michael Walle
@ 2026-05-08 12:25 ` Quentin Schulz
0 siblings, 0 replies; 14+ messages in thread
From: Quentin Schulz @ 2026-05-08 12:25 UTC (permalink / raw)
To: Michael Walle, Marek Behún, Tom Rini, Pramod Kumar,
Vladimir Oltean, Alison Wang, Tang Yuantian, Mingkai Hu,
Priyanka Jain, Wasim Khan, Meenakshi Aggarwal, TsiChung Liew,
Stefano Babic, Fabio Estevam, NXP i . MX U-Boot Team, Peng Fan,
Shengzhou Liu
Cc: Tomas Alvarez Vanoli, Jerome Forissier, u-boot
Hi Michael,
On 5/6/26 2:34 PM, Michael Walle wrote:
> Convert the README to reST format.
>
Any reason we can't have it in doc/board/nxp/ (with an update to
index.rst there)? That way it would be available at
https://docs.u-boot.org/en/latest/board/nxp/index.html.
Cheers,
Quentin
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
` (10 preceding siblings ...)
2026-05-06 12:34 ` [PATCH v2 11/11] p2041rdb: convert README to rst Michael Walle
@ 2026-05-15 4:30 ` Peng Fan
11 siblings, 0 replies; 14+ messages in thread
From: Peng Fan @ 2026-05-15 4:30 UTC (permalink / raw)
To: Michael Walle
Cc: Marek Beh??n, Tom Rini, Pramod Kumar, Vladimir Oltean,
Alison Wang, Tang Yuantian, Mingkai Hu, Priyanka Jain, Wasim Khan,
Meenakshi Aggarwal, TsiChung Liew, Stefano Babic, Fabio Estevam,
NXP i . MX U-Boot Team, Peng Fan, Shengzhou Liu,
Tomas Alvarez Vanoli, Jerome Forissier, u-boot
Hi Michael,
On Wed, May 06, 2026 at 02:34:09PM +0200, Michael Walle wrote:
>While working on an ancient P2041 based board, I've encountered
>several issues.
>
>
>Michael Walle (11):
> powerpc: fix call to cpu_init_r
> caam: don't write memory at 0 on PPC
> spi: fsl_espi: fix read transactions
> boards: remove dead fman code
> boards/nxp: remove board_eth_init()
> boards/nxp: remove empty fdt_fixup_board_enet()
> p2041rdb: use the upstream device tree
> p2041rdb: support SDcard boot
> p2041rdb: update README and fix typos
> p2041rdb: remove NAND defconfig
> p2041rdb: convert README to rst
I applied this patchset. There are some conflicts that I fixed,
it would be good if base-commit could be added in the patchset.
For the last patch, you could use a follow up patch to move the rst
to doc.
Regards
Peng
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2026-05-15 3:13 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-06 12:34 [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Michael Walle
2026-05-06 12:34 ` [PATCH v2 01/11] powerpc: fix call to cpu_init_r Michael Walle
2026-05-06 12:34 ` [PATCH v2 02/11] caam: don't write memory at 0 on PPC Michael Walle
2026-05-06 12:34 ` [PATCH v2 03/11] spi: fsl_espi: fix read transactions Michael Walle
2026-05-06 12:34 ` [PATCH v2 04/11] boards: remove dead fman code Michael Walle
2026-05-06 12:34 ` [PATCH v2 05/11] boards/nxp: remove board_eth_init() Michael Walle
2026-05-06 12:34 ` [PATCH v2 06/11] boards/nxp: remove empty fdt_fixup_board_enet() Michael Walle
2026-05-06 12:34 ` [PATCH v2 07/11] p2041rdb: use the upstream device tree Michael Walle
2026-05-06 12:34 ` [PATCH v2 08/11] p2041rdb: support SDcard boot Michael Walle
2026-05-06 12:34 ` [PATCH v2 09/11] p2041rdb: update README and fix typos Michael Walle
2026-05-06 12:34 ` [PATCH v2 10/11] p2041rdb: remove NAND defconfig Michael Walle
2026-05-06 12:34 ` [PATCH v2 11/11] p2041rdb: convert README to rst Michael Walle
2026-05-08 12:25 ` Quentin Schulz
2026-05-15 4:30 ` [PATCH v2 00/11] Generic powerpc fixes and NXP board cleanup Peng Fan
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.