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From: Jason Gunthorpe <jgg@nvidia.com>
To: Pranjal Shrivastava <praan@google.com>
Cc: "Nicolin Chen" <nicolinc@nvidia.com>,
	"Will Deacon" <will@kernel.org>, "Joerg Roedel" <joro@8bytes.org>,
	"Jean-Philippe Brucker" <jpb@kernel.org>,
	"Robin Murphy" <robin.murphy@arm.com>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Mikołaj Lenczewski" <miko.lenczewski@arm.com>,
	linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits
Date: Fri, 8 May 2026 10:27:20 -0300	[thread overview]
Message-ID: <20260508132719.GC9254@nvidia.com> (raw)
In-Reply-To: <af3hWGp3etGOIdEn@google.com>

On Fri, May 08, 2026 at 01:12:56PM +0000, Pranjal Shrivastava wrote:

> Are we assuming that if the SMMU IDR presents HTTU capability the MMU
> would also have it? I think an unconditional enablement is risky as we
> may not have system-wide HTTU support.

Oh, yes! That is missing here it should not be turned on unless the
CPU side is also using it.

Jason


  reply	other threads:[~2026-05-08 13:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-03 13:54 [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits Nicolin Chen
2026-05-07 22:30 ` Pranjal Shrivastava
2026-05-08 12:35   ` Jason Gunthorpe
2026-05-08 13:12     ` Pranjal Shrivastava
2026-05-08 13:27       ` Jason Gunthorpe [this message]
2026-05-08 13:31       ` Robin Murphy
2026-05-08 13:57         ` Pranjal Shrivastava
2026-05-08 14:24           ` Robin Murphy
2026-05-09  7:56             ` Nicolin Chen
2026-05-11 13:22               ` Pranjal Shrivastava
2026-05-13 11:42                 ` Will Deacon
2026-05-13 14:27                   ` Pranjal Shrivastava
2026-05-13 14:32                     ` Jason Gunthorpe
2026-05-13 17:38                       ` Pranjal Shrivastava
2026-05-11 13:21             ` Pranjal Shrivastava
2026-05-19 15:23 ` Will Deacon

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