From: Jason Gunthorpe <jgg@nvidia.com>
To: Pranjal Shrivastava <praan@google.com>
Cc: "Will Deacon" <will@kernel.org>,
"Nicolin Chen" <nicolinc@nvidia.com>,
"Robin Murphy" <robin.murphy@arm.com>,
"Joerg Roedel" <joro@8bytes.org>,
"Jean-Philippe Brucker" <jpb@kernel.org>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Mikołaj Lenczewski" <miko.lenczewski@arm.com>,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits
Date: Wed, 13 May 2026 11:32:13 -0300 [thread overview]
Message-ID: <20260513143213.GA787748@nvidia.com> (raw)
In-Reply-To: <agSKZPJmFMLc0gno@google.com>
On Wed, May 13, 2026 at 02:27:48PM +0000, Pranjal Shrivastava wrote:
> Now, if we're work on an SVA page, with only SMMU supporting HTTU. A DMA
> writes to the page and the process (CPU) calls fsync(). IIUC, it performs
> a lookup in the Page Cache specifically for folios tagged as DIRTY.
> Since, vmscan didn't run yet, this could potentally drop the writes..
How does it work differently in the MM when the CPU has BBM support?
Jason
next prev parent reply other threads:[~2026-05-13 14:32 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-03 13:54 [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits Nicolin Chen
2026-05-07 22:30 ` Pranjal Shrivastava
2026-05-08 12:35 ` Jason Gunthorpe
2026-05-08 13:12 ` Pranjal Shrivastava
2026-05-08 13:27 ` Jason Gunthorpe
2026-05-08 13:31 ` Robin Murphy
2026-05-08 13:57 ` Pranjal Shrivastava
2026-05-08 14:24 ` Robin Murphy
2026-05-09 7:56 ` Nicolin Chen
2026-05-11 13:22 ` Pranjal Shrivastava
2026-05-13 11:42 ` Will Deacon
2026-05-13 14:27 ` Pranjal Shrivastava
2026-05-13 14:32 ` Jason Gunthorpe [this message]
2026-05-13 17:38 ` Pranjal Shrivastava
2026-05-11 13:21 ` Pranjal Shrivastava
2026-05-19 15:23 ` Will Deacon
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