Re: [PATCH 09/10] phy: qcom-qmp: pcs-pcie: Add v10.60 register offsets - sashiko-bot

From: sashiko-bot@kernel.org
To: "Matthew Leung" <matthew.leung@oss.qualcomm.com>
Cc: conor+dt@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	neil.armstrong@linaro.org, olteanv@gmail.com,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	vkoul@kernel.org
Subject: Re: [PATCH 09/10] phy: qcom-qmp: pcs-pcie: Add v10.60 register offsets
Date: Fri, 08 May 2026 23:38:01 +0000	[thread overview]
Message-ID: <20260508233802.20366C2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260508-hawi-phy-pcie-v1-9-237b894353fc@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The macro `QPHY_PCIE_V10_60_PCS_PCS_TX_RX_CONFIG` contains a redundant `PCS_` substring.
--

commit fa9d92bd2f41dd643566d490312c4a18a8a68214
Author: Matthew Leung <matthew.leung@oss.qualcomm.com>

phy: qcom-qmp: pcs-pcie: Add v10.60 register offsets

This commit adds a new header file containing the specific PCS PCIe register
offsets for the QMP phy version v10.60 used in Hawi SoCs.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h
> new file mode 100644
> index 0000000000000..e4a2bdc7c3f03
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h
> @@ -0,0 +1,26 @@
[ ... ]
> +#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
> +#define QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
> +
> +/* Only for QMP V10_60 PHY - PCIE PCS registers */
> +#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2		0x00c
> +#define QPHY_PCIE_V10_60_PCS_PCS_TX_RX_CONFIG			0x018

This isn't a bug, but there is a redundant "PCS_" substring in
QPHY_PCIE_V10_60_PCS_PCS_TX_RX_CONFIG.

Should this be named QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG to remain consistent
with older PHY version headers like QPHY_PCIE_V8_PCS_TX_RX_CONFIG?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com?part=9