Re: [PATCH 1/2] iommu/riscv: Map IMSIC addresses for paging domains

From: Jason Gunthorpe <jgg@nvidia.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: linux-riscv@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org, tjeznach@rivosinc.com,
	joro@8bytes.org, will@kernel.org, pjw@kernel.org,
	palmer@dabbelt.com, anup@brainfault.org
Subject: Re: [PATCH 1/2] iommu/riscv: Map IMSIC addresses for paging domains
Date: Tue, 12 May 2026 10:38:54 -0300	[thread overview]
Message-ID: <20260512133854.GA9129@nvidia.com> (raw)
In-Reply-To: <20260508212339.381933-2-andrew.jones@oss.qualcomm.com>

On Fri, May 08, 2026 at 04:23:38PM -0500, Andrew Jones wrote:
> +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_head *head)
> +{
> +	const struct imsic_global_config *imsic_global;
> +	unsigned int cpu;
> +
> +	if (!imsic_enabled())
> +		return;
> +
> +	imsic_global = imsic_get_global_config();
> +
> +	for_each_possible_cpu(cpu) {
> +		const struct imsic_local_config *local;
> +		struct iommu_resv_region *reg;
> +
> +		local = per_cpu_ptr(imsic_global->local, cpu);
> +		if (!local->msi_va)
> +			continue;
> +
> +		/*
> +		 * The device always writes to the host physical IMSIC address, so install
> +		 * identity mappings directly. Use IOMMU_RESV_DIRECT_RELAXABLE instead of
> +		 * IOMMU_RESV_DIRECT since these 1:1 mappings are not required for assigned
> +		 * devices.

Oh? Why not?

> +		reg = iommu_alloc_resv_region(local->msi_pa, IMSIC_MMIO_PAGE_SZ,
> +					      IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO,
> +					      IOMMU_RESV_DIRECT_RELAXABLE, GFP_KERNEL);
> +		if (reg)
> +			list_add_tail(&reg->list, head);

This seems like quite a hack, the ARM was seems much better, the
interrupt controller should be using the iommu_dma_prepare_msi() path
to obtain an appropriately translated MSI address for the aperture.

Then things will work correctly with VFIO too.

Jason