From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Yoshinori Sato" <yoshinori.sato@nifty.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 3/3] target/sh4: Inline UNALIGN() macro
Date: Wed, 13 May 2026 08:54:37 +0200 [thread overview]
Message-ID: <20260513065438.8680-4-philmd@linaro.org> (raw)
In-Reply-To: <20260513065438.8680-1-philmd@linaro.org>
Directly access DisasContext::mo_align in place.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sh4/translate.c | 34 ++++++++++++++++------------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 5957f294c22..dfe7330d95d 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -52,10 +52,8 @@ typedef struct DisasContext {
#if defined(CONFIG_USER_ONLY)
#define IS_USER(ctx) 1
-#define UNALIGN(C) ctx->mo_align
#else
#define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
-#define UNALIGN(C) ctx->mo_align
#endif
/* Target-specific values for ctx->base.is_jmp. */
@@ -496,7 +494,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
- MO_TEUL | UNALIGN(ctx));
+ MO_TEUL | ctx->mo_align);
}
return;
case 0x5000: /* mov.l @(disp,Rm),Rn */
@@ -504,7 +502,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
- MO_TESL | UNALIGN(ctx));
+ MO_TESL | ctx->mo_align);
}
return;
case 0xe000: /* mov #imm,Rn */
@@ -564,22 +562,22 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x2001: /* mov.w Rm,@Rn */
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
- MO_TEUW | UNALIGN(ctx));
+ MO_TEUW | ctx->mo_align);
return;
case 0x2002: /* mov.l Rm,@Rn */
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
- MO_TEUL | UNALIGN(ctx));
+ MO_TEUL | ctx->mo_align);
return;
case 0x6000: /* mov.b @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
return;
case 0x6001: /* mov.w @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
- MO_TESW | UNALIGN(ctx));
+ MO_TESW | ctx->mo_align);
return;
case 0x6002: /* mov.l @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
- MO_TESL | UNALIGN(ctx));
+ MO_TESL | ctx->mo_align);
return;
case 0x2004: /* mov.b Rm,@-Rn */
{
@@ -595,7 +593,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
- MO_TEUW | UNALIGN(ctx));
+ MO_TEUW | ctx->mo_align);
tcg_gen_mov_i32(REG(B11_8), addr);
}
return;
@@ -604,7 +602,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
- MO_TEUL | UNALIGN(ctx));
+ MO_TEUL | ctx->mo_align);
tcg_gen_mov_i32(REG(B11_8), addr);
}
return;
@@ -615,13 +613,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x6005: /* mov.w @Rm+,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
- MO_TESW | UNALIGN(ctx));
+ MO_TESW | ctx->mo_align);
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
return;
case 0x6006: /* mov.l @Rm+,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
- MO_TESL | UNALIGN(ctx));
+ MO_TESL | ctx->mo_align);
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
return;
@@ -637,7 +635,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
- MO_TEUW | UNALIGN(ctx));
+ MO_TEUW | ctx->mo_align);
}
return;
case 0x0006: /* mov.l Rm,@(R0,Rn) */
@@ -645,7 +643,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
- MO_TEUL | UNALIGN(ctx));
+ MO_TEUL | ctx->mo_align);
}
return;
case 0x000c: /* mov.b @(R0,Rm),Rn */
@@ -660,7 +658,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
- MO_TESW | UNALIGN(ctx));
+ MO_TESW | ctx->mo_align);
}
return;
case 0x000e: /* mov.l @(R0,Rm),Rn */
@@ -668,7 +666,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
- MO_TESL | UNALIGN(ctx));
+ MO_TESL | ctx->mo_align);
}
return;
case 0x6008: /* swap.b Rm,Rn */
@@ -1222,7 +1220,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx,
- MO_TEUW | UNALIGN(ctx));
+ MO_TEUW | ctx->mo_align);
}
return;
case 0x8400: /* mov.b @(disp,Rn),R0 */
@@ -1237,7 +1235,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx,
- MO_TESW | UNALIGN(ctx));
+ MO_TESW | ctx->mo_align);
}
return;
case 0xc700: /* mova @(disp,PC),R0 */
--
2.53.0
prev parent reply other threads:[~2026-05-13 6:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 6:54 [PATCH 0/3] target/sh4: Re-allow unaligned access on system emulation Philippe Mathieu-Daudé
2026-05-13 6:54 ` [PATCH 1/3] " Philippe Mathieu-Daudé
2026-05-13 18:24 ` Richard Henderson
2026-05-13 18:34 ` Guenter Roeck
2026-05-14 3:11 ` yoshinori.sato
2026-05-13 6:54 ` [PATCH 2/3] target/sh4: Hold alignment as DisasContext::mo_align Philippe Mathieu-Daudé
2026-05-13 6:54 ` Philippe Mathieu-Daudé [this message]
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