Re: [PATCH v18 2/3] riscv: dts: starfive: Correct pwm nodes

From: Conor Dooley <conor@kernel.org>
To: Hal Feng <hal.feng@starfivetech.com>
Cc: "Uwe Kleine-König" <ukleinek@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Emil Renner Berthing" <emil.renner.berthing@canonical.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <pjw@kernel.org>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Changhuang Liang" <changhuang.liang@starfivetech.com>,
	linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v18 2/3] riscv: dts: starfive: Correct pwm nodes
Date: Fri, 15 May 2026 14:09:42 +0100	[thread overview]
Message-ID: <20260515-dandruff-outpour-7b3b6b5480db@spud> (raw)
In-Reply-To: <20260515054723.25024-3-hal.feng@starfivetech.com>

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On Fri, May 15, 2026 at 01:47:21PM +0800, Hal Feng wrote:
> Each of the StarFive JH7100/JH7110 SoCs has 8 OpenCores PTC IP
> cores. One OpenCores PTC IP core can output one PWM channel.
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  .../boot/dts/starfive/jh7100-common.dtsi      | 28 ++++++--
>  arch/riscv/boot/dts/starfive/jh7100.dtsi      | 69 ++++++++++++++++++-
>  .../boot/dts/starfive/jh7110-common.dtsi      | 27 ++++++--
>  .../boot/dts/starfive/jh7110-milkv-mars.dts   |  6 +-
>  .../dts/starfive/jh7110-milkv-marscm.dtsi     |  6 +-
>  .../dts/starfive/jh7110-pine64-star64.dts     |  6 +-
>  .../jh7110-starfive-visionfive-2-lite.dtsi    |  6 +-
>  .../jh7110-starfive-visionfive-2.dtsi         |  6 +-
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 69 ++++++++++++++++++-
>  9 files changed, 200 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> index ae1a6aeb0aea..85106545090e 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> @@ -199,13 +199,23 @@ GPO_I2C2_PAD_SDA_OEN,
>  		};
>  	};
>  
> -	pwm_pins: pwm-0 {
> -		pwm-pins {
> +	pwm0_pins: pwm0-0 {
> +		pwm0-pins {
>  			pinmux = <GPIOMUX(7,
>  				  GPO_PWM_PAD_OUT_BIT0,
>  				  GPO_PWM_PAD_OE_N_BIT0,
> -				  GPI_NONE)>,
> -				 <GPIOMUX(5,
> +				  GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <35>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pwm1_pins: pwm1-0 {
> +		pwm1-pins {
> +			pinmux =  <GPIOMUX(5,
>  				  GPO_PWM_PAD_OUT_BIT1,
>  				  GPO_PWM_PAD_OE_N_BIT1,
>  				  GPI_NONE)>;
> @@ -359,9 +369,15 @@ &osc_aud {
>  	clock-frequency = <27000000>;
>  };
>  
> -&pwm {
> +&pwm0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pwm0_pins>;
> +	status = "okay";
> +};
> +
> +&pwm1 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&pwm_pins>;
> +	pinctrl-0 = <&pwm1_pins>;
>  	status = "okay";
>  };
>  
> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> index 7de0732b8eab..4629e9747307 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> @@ -360,9 +360,72 @@ watchdog@12480000 {
>  				 <&rstgen JH7100_RSTN_WDT>;
>  		};
>  
> -		pwm: pwm@12490000 {
> -			compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
> -			reg = <0x0 0x12490000 0x0 0x10000>;
> +		pwm0: pwm@12490000 {
> +			compatible = "opencores,pwm-v1";
> +			reg = <0x0 0x12490000 0x0 0x10>;

NAK on the compatibles front, but this also looks very suspect, given
the size of the register regions, but I think it is actually correct.
You need to explain why it is correct in the commit message.

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