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From: sashiko-bot@kernel.org
To: "Jia Wang via B4 Relay" <devnull+wangjia.ultrarisc.com@kernel.org>
Cc: krzk+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org,
	conor+dt@kernel.org
Subject: Re: [PATCH 1/9] dt-bindings: vendor-prefixes: add Rongda
Date: Fri, 15 May 2026 01:20:57 +0000	[thread overview]
Message-ID: <20260515012057.E06EDC2BCB3@smtp.kernel.org> (raw)
In-Reply-To: <20260515-ultrarisc-pinctrl-v1-1-bf559589ea8a@ultrarisc.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The new vendor prefix '^rongda,.*' is inserted in the wrong alphabetical order in `vendor-prefixes.yaml`.
--

commit dca4b6c39a857922a831a430a56bddfea711476c
Author: Jia Wang <wangjia@ultrarisc.com>

dt-bindings: vendor-prefixes: add Rongda

This commit adds Shenzhen Rongda Computer Co., Ltd. to the devicetree vendor
prefixes list.

Link: http://www.shenrongda.com/

> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 28784d66ae7ba..04e593c66c7c4 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -1407,6 +1407,8 @@ patternProperties:
>      description: Rockchip Electronics Co., Ltd.
>    "^rocktech,.*":
>      description: ROCKTECH DISPLAYS LIMITED
> +  "^rongda,.*":
> +    description: Shenzhen Rongda Computer Co., Ltd.
>    "^rohm,.*":
>      description: ROHM Semiconductor Co., Ltd
>    "^ronbo,.*":

This isn't a bug, but is this entry inserted in the correct alphabetical
order? Alphabetically, "rohm" and "ronbo" should appear before "rongda".

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com?part=1

  reply	other threads:[~2026-05-15  1:20 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-15  1:17 [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Jia Wang via B4 Relay
2026-05-15  1:17 ` Jia Wang via B4 Relay
2026-05-15  1:17 ` Jia Wang
2026-05-15  1:17 ` [PATCH 1/9] dt-bindings: vendor-prefixes: add Rongda Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang
2026-05-15  1:20   ` sashiko-bot [this message]
2026-05-15  1:25     ` Jia Wang
2026-05-15  1:17 ` [PATCH 2/9] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang
2026-05-15 10:06   ` Conor Dooley
2026-05-15 10:06     ` Conor Dooley
2026-05-15  1:17 ` [PATCH 3/9] dt-bindings: riscv: Add UltraRISC DP1000 bindings Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang
2026-05-15 10:08   ` Conor Dooley
2026-05-15 10:08     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 4/9] dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  1:49   ` sashiko-bot
2026-05-15  8:43     ` Jia Wang
2026-05-15 10:12   ` Conor Dooley
2026-05-15 10:12     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 5/9] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:02   ` sashiko-bot
2026-05-15 10:26   ` Conor Dooley
2026-05-15 10:26     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 6/9] pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:28   ` sashiko-bot
2026-05-15  1:18 ` [PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:37   ` sashiko-bot
2026-05-15 10:28   ` Conor Dooley
2026-05-15 10:28     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 8/9] riscv: dts: ultrarisc: add Milk-V Titan " Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:50   ` sashiko-bot
2026-05-15  1:18 ` [PATCH 9/9] riscv: defconfig: enable ARCH_ULTRARISC Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:59   ` sashiko-bot
2026-05-15 10:05 ` [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Conor Dooley
2026-05-15 10:05   ` Conor Dooley

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