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From: sashiko-bot@kernel.org
To: "Jia Wang via B4 Relay" <devnull+wangjia.ultrarisc.com@kernel.org>
Cc: robh@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org,
	conor+dt@kernel.org
Subject: Re: [PATCH 9/9] riscv: defconfig: enable ARCH_ULTRARISC
Date: Fri, 15 May 2026 02:59:34 +0000	[thread overview]
Message-ID: <20260515025935.36F07C2BCB3@smtp.kernel.org> (raw)
In-Reply-To: <20260515-ultrarisc-pinctrl-v1-9-bf559589ea8a@ultrarisc.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The Kconfig symbol `ARCH_ULTRARISC` is not defined anywhere in the kernel tree.
--

commit c77ace3a44699f903221665a56d7714a8cd6cf21
Author: Jia Wang <wangjia@ultrarisc.com>

riscv: defconfig: enable ARCH_ULTRARISC

This commit adds the CONFIG_ARCH_ULTRARISC symbol to the default RISC-V
defconfig file.

Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com/

> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index c2c37327b9877..9fdc4d1831ed9 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -32,6 +32,7 @@ CONFIG_SOC_STARFIVE=y
>  CONFIG_ARCH_SUNXI=y
>  CONFIG_ARCH_TENSTORRENT=y
>  CONFIG_ARCH_THEAD=y
> +CONFIG_ARCH_ULTRARISC=y

Is ARCH_ULTRARISC defined anywhere in the kernel tree?

It appears that the Kconfig entry for ARCH_ULTRARISC is missing. Adding an
undefined symbol to a defconfig has no effect because the Kconfig system will
silently discard it during .config generation, which would prevent the
intended components from being built.

Was a prerequisite patch that adds the ARCH_ULTRARISC definition accidentally
left out of this patch series?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com?part=9

  reply	other threads:[~2026-05-15  2:59 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-15  1:17 [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Jia Wang via B4 Relay
2026-05-15  1:17 ` Jia Wang via B4 Relay
2026-05-15  1:17 ` Jia Wang
2026-05-15  1:17 ` [PATCH 1/9] dt-bindings: vendor-prefixes: add Rongda Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang
2026-05-15  1:20   ` sashiko-bot
2026-05-15  1:25     ` Jia Wang
2026-05-15  1:17 ` [PATCH 2/9] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang
2026-05-15 10:06   ` Conor Dooley
2026-05-15 10:06     ` Conor Dooley
2026-05-15  1:17 ` [PATCH 3/9] dt-bindings: riscv: Add UltraRISC DP1000 bindings Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang via B4 Relay
2026-05-15  1:17   ` Jia Wang
2026-05-15 10:08   ` Conor Dooley
2026-05-15 10:08     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 4/9] dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  1:49   ` sashiko-bot
2026-05-15  8:43     ` Jia Wang
2026-05-15 10:12   ` Conor Dooley
2026-05-15 10:12     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 5/9] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:02   ` sashiko-bot
2026-05-15 10:26   ` Conor Dooley
2026-05-15 10:26     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 6/9] pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:28   ` sashiko-bot
2026-05-15  1:18 ` [PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:37   ` sashiko-bot
2026-05-15 10:28   ` Conor Dooley
2026-05-15 10:28     ` Conor Dooley
2026-05-15  1:18 ` [PATCH 8/9] riscv: dts: ultrarisc: add Milk-V Titan " Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:50   ` sashiko-bot
2026-05-15  1:18 ` [PATCH 9/9] riscv: defconfig: enable ARCH_ULTRARISC Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang via B4 Relay
2026-05-15  1:18   ` Jia Wang
2026-05-15  2:59   ` sashiko-bot [this message]
2026-05-15 10:05 ` [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Conor Dooley
2026-05-15 10:05   ` Conor Dooley

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