* [PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC @ 2026-05-15 8:00 muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:00 ` [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes muhammad.nazim.amirul.nazle.asmade 0 siblings, 2 replies; 13+ messages in thread From: muhammad.nazim.amirul.nazle.asmade @ 2026-05-15 8:00 UTC (permalink / raw) To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> This series enables the SMMU and adds DMA coherency support for the XGMAC nodes across the affected board device trees. Patch 1 enables the SMMU for the SoCFPGA board device trees where it was missing. The SoC uses a different memory-mapped base address for its peripherals, which requires the SMMU to be active so that the Secure Device Manager (SDM) can correctly access those regions through address translation. Patch 2 adds the dma-coherent property to the XGMAC nodes. The SMMU is enabled and transactions going through it are cache coherent. Adding dma-coherent prevents redundant cache flush/invalidate operations and potential stale data issues. Changes in v2: - Move SMMU enable into the base DTSI file instead of individual DTS files - Move dma-coherent property into the base DTSI file instead of individual DTS files - Improve commit messages and cover letter descriptions with more context on why the changes are needed Nazim Amirul (2): arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees arm64: dts: socfpga: Add dma-coherent to XGMAC nodes arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.43.7 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-05-15 8:00 [PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC muhammad.nazim.amirul.nazle.asmade @ 2026-05-15 8:00 ` muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:16 ` sashiko-bot ` (2 more replies) 2026-05-15 8:00 ` [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes muhammad.nazim.amirul.nazle.asmade 1 sibling, 3 replies; 13+ messages in thread From: muhammad.nazim.amirul.nazle.asmade @ 2026-05-15 8:00 UTC (permalink / raw) To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> Enable the SMMU on the SoCFPGA board device trees where it was missing. The SoC uses a different memory-mapped base address for its peripherals, which requires the System Memory Management Unit (SMMU) to be active so that the Secure Device Manager (SDM) can correctly access those regions through address translation. Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> --- Changes in v2: - Move SMMU enable into the base DTSI file instead of individual DTS files arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index b06c6d5d60ee..64f3739a0c33 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -385,7 +385,7 @@ smmu: iommu@16000000 { interrupt-names = "eventq", "gerror", "priq"; dma-coherent; #iommu-cells = <1>; - status = "disabled"; + status = "okay"; }; spi0: spi@10da4000 { -- 2.43.7 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-05-15 8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade @ 2026-05-15 8:16 ` sashiko-bot 2026-05-15 11:51 ` Dinh Nguyen 2026-05-30 11:11 ` Krzysztof Kozlowski 2 siblings, 0 replies; 13+ messages in thread From: sashiko-bot @ 2026-05-15 8:16 UTC (permalink / raw) To: muhammad.nazim.amirul.nazle.asmade; +Cc: devicetree, krzk+dt, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Incomplete Refactoring (Redundant Overrides) -- commit 1b8d9495374546485f67ed52546157ae1e006ba8 Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees This commit enables the SMMU on the SoCFPGA board device trees by setting its status to okay in the base dtsi file. This is needed so the Secure Device Manager can correctly access memory-mapped peripheral regions. > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > index 352c96d144a84..527a5ef54c837 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > @@ -385,7 +385,7 @@ smmu: iommu@16000000 { > interrupt-names = "eventq", "gerror", "priq"; > dma-coherent; > #iommu-cells = <1>; > - status = "disabled"; > + status = "okay"; This isn't a bug, but since the status is now set to okay in the base dtsi, does this make the existing overrides in the board specific device trees redundant? For example, socfpga_agilex5_socdk_modular.dts, socfpga_agilex5_socdk_013b.dts, and socfpga_agilex3_socdk.dts already contain: &smmu { status = "okay"; }; Could these board-level overrides be removed in this patch to maintain device tree cleanliness? > }; -- Sashiko AI review · https://sashiko.dev/#/patchset/20260515080014.6260-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=1 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-05-15 8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:16 ` sashiko-bot @ 2026-05-15 11:51 ` Dinh Nguyen 2026-05-30 11:11 ` Krzysztof Kozlowski 2 siblings, 0 replies; 13+ messages in thread From: Dinh Nguyen @ 2026-05-15 11:51 UTC (permalink / raw) To: muhammad.nazim.amirul.nazle.asmade Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel On 5/15/26 03:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote: > From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> > > Enable the SMMU on the SoCFPGA board device trees where it was > missing. The SoC uses a different memory-mapped base address for > its peripherals, which requires the System Memory Management Unit > (SMMU) to be active so that the Secure Device Manager (SDM) can > correctly access those regions through address translation. > > Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> > --- > Changes in v2: > - Move SMMU enable into the base DTSI file instead of individual DTS files > > arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > index b06c6d5d60ee..64f3739a0c33 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > @@ -385,7 +385,7 @@ smmu: iommu@16000000 { > interrupt-names = "eventq", "gerror", "priq"; > dma-coherent; > #iommu-cells = <1>; > - status = "disabled"; > + status = "okay"; > }; > > spi0: spi@10da4000 { Please make it a practice to see what formatting previous commits look like on the subsystem you're making changes to. For example, this commit header should be something like this: arm64: dts: socfpga: agilex5: Enable the SMMU Then in your commit message should not restate your commit header. So remove "Enable the SMMU on the SoCFPGA board device trees" Thanks, Dinh ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-05-15 8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:16 ` sashiko-bot 2026-05-15 11:51 ` Dinh Nguyen @ 2026-05-30 11:11 ` Krzysztof Kozlowski 2026-06-04 10:55 ` Nazle Asmade, Muhammad Nazim Amirul 2 siblings, 1 reply; 13+ messages in thread From: Krzysztof Kozlowski @ 2026-05-30 11:11 UTC (permalink / raw) To: muhammad.nazim.amirul.nazle.asmade, dinguyen Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote: > From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> > > Enable the SMMU on the SoCFPGA board device trees where it was > missing. The SoC uses a different memory-mapped base address for > its peripherals, which requires the System Memory Management Unit > (SMMU) to be active so that the Secure Device Manager (SDM) can > correctly access those regions through address translation. > > Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> > --- > Changes in v2: > - Move SMMU enable into the base DTSI file instead of individual DTS files > > arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > index b06c6d5d60ee..64f3739a0c33 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > @@ -385,7 +385,7 @@ smmu: iommu@16000000 { > interrupt-names = "eventq", "gerror", "priq"; > dma-coherent; > #iommu-cells = <1>; > - status = "disabled"; > + status = "okay"; Which file disabled it? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-05-30 11:11 ` Krzysztof Kozlowski @ 2026-06-04 10:55 ` Nazle Asmade, Muhammad Nazim Amirul 2026-06-04 11:15 ` Krzysztof Kozlowski 0 siblings, 1 reply; 13+ messages in thread From: Nazle Asmade, Muhammad Nazim Amirul @ 2026-06-04 10:55 UTC (permalink / raw) To: Krzysztof Kozlowski, dinguyen@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On 30/5/2026 7:11 pm, Krzysztof Kozlowski wrote: > [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote: >> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> >> >> Enable the SMMU on the SoCFPGA board device trees where it was >> missing. The SoC uses a different memory-mapped base address for >> its peripherals, which requires the System Memory Management Unit >> (SMMU) to be active so that the Secure Device Manager (SDM) can >> correctly access those regions through address translation. >> >> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> >> --- >> Changes in v2: >> - Move SMMU enable into the base DTSI file instead of individual DTS files >> >> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> index b06c6d5d60ee..64f3739a0c33 100644 >> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> @@ -385,7 +385,7 @@ smmu: iommu@16000000 { >> interrupt-names = "eventq", "gerror", "priq"; >> dma-coherent; >> #iommu-cells = <1>; >> - status = "disabled"; >> + status = "okay"; > > Which file disabled it? > > Best regards, > Krzysztof Hi Dinh, Krzysztof Thank you for the review and feedback! Addressing Dinh's comment — the commit header has been updated to follow the subsystem naming convention. Addressing Krzysztof's question — the SMMU was disabled in socfpga_agilex5.dtsi itself, where the node is defined with status = "disabled". This has been clarified in the updated commit message. https://lore.kernel.org/all/20260604105020.24782-1-muhammad.nazim.amirul.nazle.asmade@altera.com/ https://lore.kernel.org/all/20260604105020.24782-2-muhammad.nazim.amirul.nazle.asmade@altera.com/ https://lore.kernel.org/all/20260604105020.24782-3-muhammad.nazim.amirul.nazle.asmade@altera.com/ BR, Nazim ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-06-04 10:55 ` Nazle Asmade, Muhammad Nazim Amirul @ 2026-06-04 11:15 ` Krzysztof Kozlowski 2026-06-04 12:00 ` Nazle Asmade, Muhammad Nazim Amirul 0 siblings, 1 reply; 13+ messages in thread From: Krzysztof Kozlowski @ 2026-06-04 11:15 UTC (permalink / raw) To: Nazle Asmade, Muhammad Nazim Amirul, dinguyen@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On 04/06/2026 12:55, Nazle Asmade, Muhammad Nazim Amirul wrote: > On 30/5/2026 7:11 pm, Krzysztof Kozlowski wrote: >> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] >> >> On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote: >>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> >>> >>> Enable the SMMU on the SoCFPGA board device trees where it was >>> missing. The SoC uses a different memory-mapped base address for >>> its peripherals, which requires the System Memory Management Unit >>> (SMMU) to be active so that the Secure Device Manager (SDM) can >>> correctly access those regions through address translation. >>> >>> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> >>> --- >>> Changes in v2: >>> - Move SMMU enable into the base DTSI file instead of individual DTS files >>> >>> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >>> index b06c6d5d60ee..64f3739a0c33 100644 >>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 { >>> interrupt-names = "eventq", "gerror", "priq"; >>> dma-coherent; >>> #iommu-cells = <1>; >>> - status = "disabled"; >>> + status = "okay"; >> >> Which file disabled it? >> >> Best regards, >> Krzysztof > Hi Dinh, Krzysztof > > Thank you for the review and feedback! > > Addressing Dinh's comment — the commit header has been updated to follow > the subsystem naming convention. > > Addressing Krzysztof's question — the SMMU was disabled in > socfpga_agilex5.dtsi itself, where the node is defined with status = > "disabled". This has been clarified in the updated commit message. This makes no sense. I am asking which nod makes it disabled now, that you need to enable it. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-06-04 11:15 ` Krzysztof Kozlowski @ 2026-06-04 12:00 ` Nazle Asmade, Muhammad Nazim Amirul 2026-06-04 12:42 ` Krzysztof Kozlowski 0 siblings, 1 reply; 13+ messages in thread From: Nazle Asmade, Muhammad Nazim Amirul @ 2026-06-04 12:00 UTC (permalink / raw) To: Krzysztof Kozlowski, dinguyen@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On 4/6/2026 7:15 pm, Krzysztof Kozlowski wrote: > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > index b06c6d5d60ee..64f3739a0c33 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > @@ -385,7 +385,7 @@ smmu: iommu@16000000 { > interrupt-names = "eventq", "gerror", "priq"; > dma-coherent; > #iommu-cells = <1>; > - status = "disabled"; > + status = "okay"; Hi Krzysztof, The smmu: iommu@16000000 node in socfpga_agilex5.dtsi is defined with status = "disabled" as the default. It was not enabled during the initial Agilex5 bring-up. ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-06-04 12:00 ` Nazle Asmade, Muhammad Nazim Amirul @ 2026-06-04 12:42 ` Krzysztof Kozlowski 2026-06-05 2:31 ` Nazle Asmade, Muhammad Nazim Amirul 0 siblings, 1 reply; 13+ messages in thread From: Krzysztof Kozlowski @ 2026-06-04 12:42 UTC (permalink / raw) To: Nazle Asmade, Muhammad Nazim Amirul, dinguyen@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On 04/06/2026 14:00, Nazle Asmade, Muhammad Nazim Amirul wrote: > On 4/6/2026 7:15 pm, Krzysztof Kozlowski wrote: >> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> index b06c6d5d60ee..64f3739a0c33 100644 >> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >> @@ -385,7 +385,7 @@ smmu: iommu@16000000 { >> interrupt-names = "eventq", "gerror", "priq"; >> dma-coherent; >> #iommu-cells = <1>; >> - status = "disabled"; >> + status = "okay"; > Hi Krzysztof, > > The smmu: iommu@16000000 node in socfpga_agilex5.dtsi is defined with Which file are we discussing here? socfpga_agilex5.dtsi. Then why do you refer to the same file? > status = "disabled" as the default. It was not enabled during the > initial Agilex5 bring-up. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees 2026-06-04 12:42 ` Krzysztof Kozlowski @ 2026-06-05 2:31 ` Nazle Asmade, Muhammad Nazim Amirul 0 siblings, 0 replies; 13+ messages in thread From: Nazle Asmade, Muhammad Nazim Amirul @ 2026-06-05 2:31 UTC (permalink / raw) To: Krzysztof Kozlowski, dinguyen@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On 4/6/2026 8:42 pm, Krzysztof Kozlowski wrote: > On 04/06/2026 14:00, Nazle Asmade, Muhammad Nazim Amirul wrote: >> On 4/6/2026 7:15 pm, Krzysztof Kozlowski wrote: >>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >>> index b06c6d5d60ee..64f3739a0c33 100644 >>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi >>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 { >>> interrupt-names = "eventq", "gerror", "priq"; >>> dma-coherent; >>> #iommu-cells = <1>; >>> - status = "disabled"; >>> + status = "okay"; >> Hi Krzysztof, >> >> The smmu: iommu@16000000 node in socfpga_agilex5.dtsi is defined with > > Which file are we discussing here? socfpga_agilex5.dtsi. Then why do you > refer to the same file? > >> status = "disabled" as the default. It was not enabled during the >> initial Agilex5 bring-up. > > > Best regards, > Krzysztof Hi Krzysztof, Apologies for the confusion. I was referring to socfpga_agilex5.dtsi itself, and I believe that is what you meant as well — we should simply remove the status = "disabled" line only, since the default status is "okay" when not specified. BR, Nazim ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes 2026-05-15 8:00 [PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade @ 2026-05-15 8:00 ` muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:23 ` sashiko-bot 2026-05-15 11:52 ` Dinh Nguyen 1 sibling, 2 replies; 13+ messages in thread From: muhammad.nazim.amirul.nazle.asmade @ 2026-05-15 8:00 UTC (permalink / raw) To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> The SMMU is enabled and transactions going through it are cache coherent. Add the dma-coherent property to the XGMAC nodes to prevent redundant cache flush/invalidate operations and potential stale data issues. Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> --- Changes in v2: - Move dma-coherent property into the base DTSI file instead of individual DTS files arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 64f3739a0c33..bef386cb2fcc 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -577,6 +577,7 @@ gmac0: ethernet@10810000 { altr,sysmgr-syscon = <&sysmgr 0x44 0>; snps,clk-csr = <0>; iommus = <&smmu 1>; + dma-coherent; status = "disabled"; stmmac_axi_emac0_setup: stmmac-axi-config { @@ -690,6 +691,7 @@ gmac1: ethernet@10820000 { altr,sysmgr-syscon = <&sysmgr 0x48 0>; snps,clk-csr = <0>; iommus = <&smmu 2>; + dma-coherent; status = "disabled"; stmmac_axi_emac1_setup: stmmac-axi-config { @@ -803,6 +805,7 @@ gmac2: ethernet@10830000 { altr,sysmgr-syscon = <&sysmgr 0x4c 0>; snps,clk-csr = <0>; iommus = <&smmu 3>; + dma-coherent; status = "disabled"; stmmac_axi_emac2_setup: stmmac-axi-config { -- 2.43.7 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes 2026-05-15 8:00 ` [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes muhammad.nazim.amirul.nazle.asmade @ 2026-05-15 8:23 ` sashiko-bot 2026-05-15 11:52 ` Dinh Nguyen 1 sibling, 0 replies; 13+ messages in thread From: sashiko-bot @ 2026-05-15 8:23 UTC (permalink / raw) To: muhammad.nazim.amirul.nazle.asmade; +Cc: krzk+dt, conor+dt, robh, devicetree Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] Missing dma-coherent property on other SMMU clients causes data corruption -- commit be9ce7db4922ed7d48488efa182130301cfa9435 Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> arm64: dts: socfpga: Add dma-coherent to XGMAC nodes The commit asserts that SMMU transactions are cache coherent and adds dma-coherent to the XGMAC nodes. This prevents redundant cache flush and invalidate operations and potential stale data issues. > The SMMU is enabled and transactions going through it are cache > coherent. Add the dma-coherent property to the XGMAC nodes to prevent > redundant cache flush/invalidate operations and potential stale data > issues. This problem wasn't introduced by this patch, but the patch provides an incomplete fix. The commit message asserts that "transactions going through it are cache coherent" and correctly notes that missing the dma-coherent property causes "potential stale data issues". On ARM64, if a hardware-coherent device is treated as non-coherent, the kernel will execute cache invalidation (dcache_inval_poc -> dc ivac via arch_sync_dma_for_cpu) for DMA_FROM_DEVICE transfers. If the device wrote data directly into the CPU caches, the dc ivac instruction will discard those dirty cache lines without writing them back to RAM. This destroys the DMA writes and causes the CPU to read stale data from memory, resulting in reproducible data corruption. If the SMMU provides coherency for all transactions, do other major DMA masters that also route through the SMMU need the dma-coherent property? For example, usb0, dmac0, and dmac1 use the SMMU but lack the property: arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi: usb0: usb@10b00000 { ... iommus = <&smmu 6>; ... }; dmac0: dma-controller@0 { ... iommus = <&smmu 8>; ... }; dmac1: dma-controller@10000 { ... iommus = <&smmu 9>; ... }; If coherency is specific only to XGMAC, could the commit message be clarified to avoid a blanket statement about the SMMU? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260515080014.6260-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes 2026-05-15 8:00 ` [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:23 ` sashiko-bot @ 2026-05-15 11:52 ` Dinh Nguyen 1 sibling, 0 replies; 13+ messages in thread From: Dinh Nguyen @ 2026-05-15 11:52 UTC (permalink / raw) To: muhammad.nazim.amirul.nazle.asmade Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel On 5/15/26 03:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote: > From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> > > The SMMU is enabled and transactions going through it are cache > coherent. Add the dma-coherent property to the XGMAC nodes to prevent > redundant cache flush/invalidate operations and potential stale data > issues. > > Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> > --- > Changes in v2: > - Move dma-coherent property into the base DTSI file instead of individual DTS files > > arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > index 64f3739a0c33..bef386cb2fcc 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi > @@ -577,6 +577,7 @@ gmac0: ethernet@10810000 { > altr,sysmgr-syscon = <&sysmgr 0x44 0>; > snps,clk-csr = <0>; > iommus = <&smmu 1>; > + dma-coherent; > status = "disabled"; > > stmmac_axi_emac0_setup: stmmac-axi-config { > @@ -690,6 +691,7 @@ gmac1: ethernet@10820000 { > altr,sysmgr-syscon = <&sysmgr 0x48 0>; > snps,clk-csr = <0>; > iommus = <&smmu 2>; > + dma-coherent; > status = "disabled"; > > stmmac_axi_emac1_setup: stmmac-axi-config { > @@ -803,6 +805,7 @@ gmac2: ethernet@10830000 { > altr,sysmgr-syscon = <&sysmgr 0x4c 0>; > snps,clk-csr = <0>; > iommus = <&smmu 3>; > + dma-coherent; > status = "disabled"; > > stmmac_axi_emac2_setup: stmmac-axi-config { Same comment from patch [1/2]. Also, can you add the dma-coherent to the other IPs using the SMMU as well? Thanks, Dinh ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-06-05 2:31 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-15 8:00 [PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:16 ` sashiko-bot 2026-05-15 11:51 ` Dinh Nguyen 2026-05-30 11:11 ` Krzysztof Kozlowski 2026-06-04 10:55 ` Nazle Asmade, Muhammad Nazim Amirul 2026-06-04 11:15 ` Krzysztof Kozlowski 2026-06-04 12:00 ` Nazle Asmade, Muhammad Nazim Amirul 2026-06-04 12:42 ` Krzysztof Kozlowski 2026-06-05 2:31 ` Nazle Asmade, Muhammad Nazim Amirul 2026-05-15 8:00 ` [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes muhammad.nazim.amirul.nazle.asmade 2026-05-15 8:23 ` sashiko-bot 2026-05-15 11:52 ` Dinh Nguyen
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