From: Nicholas Piggin <npiggin@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Andrew Jones" <andrew.jones@oss.qualcomm.com>,
"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
"Chao Liu" <chao.liu.zevorn@gmail.com>,
"Michael Ellerman" <mpe@kernel.org>,
"Joel Stanley" <jms@oss.tenstorrent.com>,
"Anirudh Srinivasan" <asrinivasan@oss.tenstorrent.com>,
"Portia Stephens" <portias@oss.tenstorrent.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Joel Stanley" <joel@jms.id.au>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v6 06/10] hw/riscv/atlantis: Provide a simple halting payload
Date: Fri, 15 May 2026 17:42:01 -0700 [thread overview]
Message-ID: <20260516004206.169035-7-npiggin@gmail.com> (raw)
In-Reply-To: <20260516004206.169035-1-npiggin@gmail.com>
OpenSBI hangs before any console output if the domain init code sees the
next stage is not in an executable region.
If no kernel payload is provided to QEMU, the next stage address is
NULL, and the riscv virt machine memory map ends up covering the 0
address with the catch all S-mode RWX region and so OpenSBI prints
console messages and does not hang until the next stage boot.
The Tenstorrent Atlantis machine address map has RAM starting at 0 and
it loads OpenSBI there, so it is M-mode and not accessible by S-mode,
tripping the early check and hang.
Add a helper to set up a simple payload that gets OpenSBI messages to
console, until OpenSBI can be fixed.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/riscv/tt_atlantis.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index 43f47fbd75..789a66870a 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -384,6 +384,30 @@ static void create_fdt(TTAtlantisState *s)
create_fdt_pmu(s);
}
+/*
+ * This works around a problem with OpenSBI hanging with no console output if
+ * no payload is provided. By chance, machines with memory at 0x80000000 do get
+ * output, but Atlantis memory begins at 0x0 which takes a different OpenSBI
+ * error path.
+ *
+ * This can be removed when OpenSBI is fixed in QEMU.
+ */
+static void tt_atlantis_setup_halting_payload_opensbi_fixup(
+ RISCVBootInfo *info, hwaddr addr)
+{
+ /* Store the payload vector in little_endian byte order */
+ static const uint32_t payload_vec[] = {
+ const_le32(0x10500073), /* 1: wfi */
+ const_le32(0xffdff06f), /* j 1b */
+ };
+ rom_add_blob_fixed_as("mrom.payload", payload_vec, sizeof(payload_vec),
+ addr, &address_space_memory);
+
+ info->kernel_size = sizeof(payload_vec);
+ info->image_low_addr = addr;
+ info->image_high_addr = info->image_low_addr + info->kernel_size;
+}
+
static void tt_atlantis_machine_done(Notifier *notifier, void *data)
{
TTAtlantisState *s = container_of(notifier, TTAtlantisState, machine_done);
@@ -421,6 +445,9 @@ static void tt_atlantis_machine_done(Notifier *notifier, void *data)
if (machine->kernel_filename) {
riscv_load_kernel(machine, &boot_info, kernel_start_addr,
true, NULL);
+ } else {
+ tt_atlantis_setup_halting_payload_opensbi_fixup(&boot_info,
+ kernel_start_addr);
}
kernel_entry = boot_info.image_low_addr;
--
2.53.0
next prev parent reply other threads:[~2026-05-16 0:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-16 0:41 [PATCH v6 00/10] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
2026-05-16 0:41 ` [PATCH v6 01/10] hw/riscv/boot: Describe discontiguous memory in boot_info Nicholas Piggin
2026-05-16 0:41 ` [PATCH v6 02/10] hw/riscv/boot: Account for discontiguous memory when loading firmware Nicholas Piggin
2026-05-16 0:41 ` [PATCH v6 03/10] hw/riscv/virt: Move AIA initialisation to helper file Nicholas Piggin
2026-05-16 0:41 ` [PATCH v6 04/10] hw/riscv/aia: Provide number of irq sources Nicholas Piggin
2026-05-16 0:42 ` [PATCH v6 05/10] hw/riscv: Add Tenstorrent Atlantis machine Nicholas Piggin
2026-05-16 0:42 ` Nicholas Piggin [this message]
2026-05-16 0:42 ` [PATCH v6 07/10] tests/functional/riscv64: Add tt-atlantis tests Nicholas Piggin
2026-05-16 0:42 ` [PATCH v6 08/10] hw/i2c: Add DesignWare I2C Controller Nicholas Piggin
2026-05-16 0:42 ` [PATCH v6 09/10] hw/riscv/atlantis: Integrate i2c controllers Nicholas Piggin
2026-05-16 0:42 ` [PATCH v6 10/10] hw/riscv/atlantis: Add some i2c peripherals Nicholas Piggin
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