[PATCH v5 0/3] Add eager FP and RISC-V vector context switching support

[PATCH v5 0/3] Add eager FP and RISC-V vector context switching support

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

1) fcsr to unsigned long.
2) removed redundant line
3) merging path 3 and 4 into patch 3.

Dave Patel (3):
  lib: sbi: Add RISC-V vector context save/restore support
  lib: sbi: Add floating-point context save/restore support.
  lib: sbi: domain FP/Vector context support for context switch

 include/sbi/sbi_fp.h         |  26 +++++
 include/sbi/sbi_hart.h       |   6 ++
 include/sbi/sbi_vector.h     |  28 +++++
 lib/sbi/objects.mk           |   2 +
 lib/sbi/sbi_domain_context.c |  40 ++++++++
 lib/sbi/sbi_fp.c             | 192 +++++++++++++++++++++++++++++++++++
 lib/sbi/sbi_hart.c           |   3 +
 lib/sbi/sbi_vector.c         | 109 ++++++++++++++++++++
 8 files changed, 406 insertions(+)
 create mode 100644 include/sbi/sbi_fp.h
 create mode 100644 include/sbi/sbi_vector.h
 create mode 100644 lib/sbi/sbi_fp.c
 create mode 100644 lib/sbi/sbi_vector.c

--
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[PATCH v5 1/3] lib: sbi: Add RISC-V vector context save/restore support

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

Eager context switch: Add support for saving and restoring RISC-V vector
extension state in OpenSBI. This introduces a per-hart vector context
structure and helper routines to perform full context save and restore.

The vector context includes vcsr CSRs along with storage for all 32 vector
registers. The register state is saved and restored using byte-wise vector
load/store instructions (vs8r/vl8r).

The implementation follows an eager context switching model where the entire
vector state is saved and restored on every context switch. This provides a
simple and deterministic mechanism without requiring lazy trap-based
management.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
---
 include/sbi/sbi_vector.h |  28 ++++++++++
 lib/sbi/objects.mk       |   1 +
 lib/sbi/sbi_vector.c     | 109 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 138 insertions(+)
 create mode 100644 include/sbi/sbi_vector.h
 create mode 100644 lib/sbi/sbi_vector.c

diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h
new file mode 100644
index 00000000..bbd857c3
--- /dev/null
+++ b/include/sbi/sbi_vector.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+
+#ifndef __SBI_VECTOR_H__
+#define __SBI_VECTOR_H__
+
+#include <sbi/sbi_types.h>
+
+struct sbi_vector_context {
+	unsigned long vcsr;
+	unsigned long vstart;
+
+	/* size depends on VLEN */
+	uint8_t vregs[];
+};
+
+void sbi_vector_save(struct sbi_vector_context *dst);
+void sbi_vector_restore(const struct sbi_vector_context *src);
+unsigned long vector_vlenb(void);
+
+#endif //__SBI_VECTOR_H__
+
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index 97cc4521..ddb2e7ac 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -109,3 +109,4 @@ libsbi-objs-y += sbi_trap_v_ldst.o
 libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
+libsbi-objs-y += sbi_vector.o
diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
new file mode 100644
index 00000000..1d2ac944
--- /dev/null
+++ b/lib/sbi/sbi_vector.c
@@ -0,0 +1,109 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *	 Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/sbi_domain.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_vector.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_console.h>
+
+#ifdef OPENSBI_CC_SUPPORT_VECTOR
+
+unsigned long vector_vlenb(void)
+{
+	unsigned long vlenb = 0;
+
+	asm volatile (
+		".option push\n\t"
+		".option arch, +v\n\t"
+		"csrr %0, vlenb\n\t"
+		".option pop\n\t"
+		: "=r"(vlenb)
+		:
+		: "memory");
+
+	return vlenb;
+}
+
+void sbi_vector_save(struct sbi_vector_context *dst)
+{
+	if (!dst)
+		return;
+
+	/* Step 1: Save CSRs */
+	dst->vcsr = csr_read(vcsr);
+	dst->vstart = csr_read(vstart);
+
+	ulong vlenb = vector_vlenb();
+	uint8_t *base = dst->vregs;
+
+	/* Step 3: Save vector registers */
+#define SAVE_VREG(i)						\
+	({							\
+	asm volatile(						\
+		"	.option push\n\t"			\
+		"	.option arch, +v\n\t"			\
+		"	vs8r.v v" #i ", (%0)\n\t"		\
+		"	.option pop\n\t"			\
+		::	"r"(base + (i) * vlenb)	: "memory");	\
+	})							\
+
+	SAVE_VREG(0);
+	SAVE_VREG(8);
+	SAVE_VREG(16);
+	SAVE_VREG(24);
+
+#undef SAVE_VREG
+}
+
+void sbi_vector_restore(const struct sbi_vector_context *src)
+{
+	if (!src)
+		return;
+
+	const uint8_t *base = src->vregs;
+	ulong vlenb = vector_vlenb();
+
+	/* Step 2: Restore vector registers */
+#define RESTORE_VREG(i)					\
+	({							\
+	asm volatile(						\
+		"	.option push\n\t"			\
+		"	.option arch, +v\n\t"			\
+		"	vl8r.v v" #i ", (%0)\n\t"		\
+		"	.option pop\n\t"			\
+		::	"r"(base + (i) * vlenb) : "memory");	\
+	 })							\
+
+	RESTORE_VREG(0);
+	RESTORE_VREG(8);
+	RESTORE_VREG(16);
+	RESTORE_VREG(24);
+#undef RESTORE_VREG
+
+	/* Step 3: Restore CSR's last */
+	/* Restore CSRs first */
+	csr_write(vcsr,   src->vcsr);
+	csr_write(vstart, src->vstart);
+}
+
+#else
+
+void sbi_vector_save(struct sbi_vector_context *dst)
+{
+}
+
+void sbi_vector_restore(const struct sbi_vector_context *src)
+{
+}
+
+#endif /* OPENSBI_CC_SUPPORT_VECTOR */
-- 
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[PATCH v5 2/3] lib: sbi: Add floating-point context save/restore support.

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

Add support for saving and restoring RISC-V floating-point (F/D) extension
state in OpenSBI. This introduces a floating-point context structure and
helper routines to perform full context save and restore.

The floating-point context includes storage for all 32 FPi registers (f0–f31)
along with the fcsr control and status register. The register state is saved
and restored using double-precision load/store instructions (fsd/fld), and
single-precision load/store instructions (fsw/flw) on an RV64 system with
F and D-extension support.

The implementation follows an eager context switching model where the entire
FP state is saved and restored on every context switch. This avoids the need
for trap-based lazy management and keeps the design simple and deterministic.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>"
---
 include/sbi/sbi_fp.h |  26 ++++++
 lib/sbi/objects.mk   |   1 +
 lib/sbi/sbi_fp.c     | 192 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 219 insertions(+)
 create mode 100644 include/sbi/sbi_fp.h
 create mode 100644 lib/sbi/sbi_fp.c

diff --git a/include/sbi/sbi_fp.h b/include/sbi/sbi_fp.h
new file mode 100644
index 00000000..a00756fc
--- /dev/null
+++ b/include/sbi/sbi_fp.h
@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+#ifndef __SBI_FP_H__
+#define __SBI_FP_H__
+
+#include <sbi/sbi_types.h>
+
+struct sbi_fp_context {
+#if __riscv_d
+	uint64_t f[32];
+#else
+	uint32_t f[32];
+#endif
+	unsigned long fcsr;
+};
+
+void sbi_fp_save(struct sbi_fp_context *dst);
+void sbi_fp_restore(const struct sbi_fp_context *src);
+
+#endif //__SBI_VECTOR_H__
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index ddb2e7ac..d8182383 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -110,3 +110,4 @@ libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
 libsbi-objs-y += sbi_vector.o
+libsbi-objs-y += sbi_fp.o
diff --git a/lib/sbi/sbi_fp.c b/lib/sbi/sbi_fp.c
new file mode 100644
index 00000000..887bca4d
--- /dev/null
+++ b/lib/sbi/sbi_fp.c
@@ -0,0 +1,192 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_fp.h>
+
+#if defined(__riscv_f) || defined(__riscv_d)
+
+void sbi_fp_save(struct sbi_fp_context *dst)
+{
+	if (!dst)
+		return;
+
+#if defined(__riscv_d)
+	asm volatile(
+		"fsd f0,  0(%0)\n"
+		"fsd f1,  8(%0)\n"
+		"fsd f2,  16(%0)\n"
+		"fsd f3,  24(%0)\n"
+		"fsd f4,  32(%0)\n"
+		"fsd f5,  40(%0)\n"
+		"fsd f6,  48(%0)\n"
+		"fsd f7,  56(%0)\n"
+		"fsd f8,  64(%0)\n"
+		"fsd f9,  72(%0)\n"
+		"fsd f10, 80(%0)\n"
+		"fsd f11, 88(%0)\n"
+		"fsd f12, 96(%0)\n"
+		"fsd f13, 104(%0)\n"
+		"fsd f14, 112(%0)\n"
+		"fsd f15, 120(%0)\n"
+		"fsd f16, 128(%0)\n"
+		"fsd f17, 136(%0)\n"
+		"fsd f18, 144(%0)\n"
+		"fsd f19, 152(%0)\n"
+		"fsd f20, 160(%0)\n"
+		"fsd f21, 168(%0)\n"
+		"fsd f22, 176(%0)\n"
+		"fsd f23, 184(%0)\n"
+		"fsd f24, 192(%0)\n"
+		"fsd f25, 200(%0)\n"
+		"fsd f26, 208(%0)\n"
+		"fsd f27, 216(%0)\n"
+		"fsd f28, 224(%0)\n"
+		"fsd f29, 232(%0)\n"
+		"fsd f30, 240(%0)\n"
+		"fsd f31, 248(%0)\n"
+		:
+		: "r"(dst->f)
+		: "memory"
+	);
+#else
+	asm volatile(
+		"fsw f0,  0(%0)\n"
+		"fsw f1,  4(%0)\n"
+		"fsw f2,  8(%0)\n"
+		"fsw f3,  12(%0)\n"
+		"fsw f4,  16(%0)\n"
+		"fsw f5,  20(%0)\n"
+		"fsw f6,  24(%0)\n"
+		"fsw f7,  28(%0)\n"
+		"fsw f8,  32(%0)\n"
+		"fsw f9,  36(%0)\n"
+		"fsw f10, 40(%0)\n"
+		"fsw f11, 44(%0)\n"
+		"fsw f12, 48(%0)\n"
+		"fsw f13, 52(%0)\n"
+		"fsw f14, 56(%0)\n"
+		"fsw f15, 60(%0)\n"
+		"fsw f16, 64(%0)\n"
+		"fsw f17, 68(%0)\n"
+		"fsw f18, 72(%0)\n"
+		"fsw f19, 76(%0)\n"
+		"fsw f20, 80(%0)\n"
+		"fsw f21, 84(%0)\n"
+		"fsw f22, 88(%0)\n"
+		"fsw f23, 92(%0)\n"
+		"fsw f24, 96(%0)\n"
+		"fsw f25, 100(%0)\n"
+		"fsw f26, 104(%0)\n"
+		"fsw f27, 108(%0)\n"
+		"fsw f28, 112(%0)\n"
+		"fsw f29, 116(%0)\n"
+		"fsw f30, 120(%0)\n"
+		"fsw f31, 124(%0)\n"
+		:
+		: "r"(dst->f)
+		: "memory"
+	);
+#endif //__riscv_d
+
+	dst->fcsr = csr_read(CSR_FCSR);
+}
+
+void sbi_fp_restore(const struct sbi_fp_context *src)
+{
+	if (!src)
+		return;
+
+#if defined(__riscv_d)
+	asm volatile(
+		"fld f0,  0(%0)\n"
+		"fld f1,  8(%0)\n"
+		"fld f2,  16(%0)\n"
+		"fld f3,  24(%0)\n"
+		"fld f4,  32(%0)\n"
+		"fld f5,  40(%0)\n"
+		"fld f6,  48(%0)\n"
+		"fld f7,  56(%0)\n"
+		"fld f8,  64(%0)\n"
+		"fld f9,  72(%0)\n"
+		"fld f10, 80(%0)\n"
+		"fld f11, 88(%0)\n"
+		"fld f12, 96(%0)\n"
+		"fld f13, 104(%0)\n"
+		"fld f14, 112(%0)\n"
+		"fld f15, 120(%0)\n"
+		"fld f16, 128(%0)\n"
+		"fld f17, 136(%0)\n"
+		"fld f18, 144(%0)\n"
+		"fld f19, 152(%0)\n"
+		"fld f20, 160(%0)\n"
+		"fld f21, 168(%0)\n"
+		"fld f22, 176(%0)\n"
+		"fld f23, 184(%0)\n"
+		"fld f24, 192(%0)\n"
+		"fld f25, 200(%0)\n"
+		"fld f26, 208(%0)\n"
+		"fld f27, 216(%0)\n"
+		"fld f28, 224(%0)\n"
+		"fld f29, 232(%0)\n"
+		"fld f30, 240(%0)\n"
+		"fld f31, 248(%0)\n"
+		:
+		: "r"(src->f)
+		: "memory"
+	);
+#else
+
+	asm volatile(
+		"flw f0,   0(%0)\n"
+		"flw f1,   4(%0)\n"
+		"flw f2,   8(%0)\n"
+		"flw f3,  12(%0)\n"
+		"flw f4,  16(%0)\n"
+		"flw f5,  20(%0)\n"
+		"flw f6,  24(%0)\n"
+		"flw f7,  28(%0)\n"
+		"flw f8,  32(%0)\n"
+		"flw f9,  36(%0)\n"
+		"flw f10, 40(%0)\n"
+		"flw f11, 44(%0)\n"
+		"flw f12, 48(%0)\n"
+		"flw f13, 52(%0)\n"
+		"flw f14, 56(%0)\n"
+		"flw f15, 60(%0)\n"
+		"flw f16, 64(%0)\n"
+		"flw f17, 68(%0)\n"
+		"flw f18, 72(%0)\n"
+		"flw f19, 76(%0)\n"
+		"flw f20, 80(%0)\n"
+		"flw f21, 84(%0)\n"
+		"flw f22, 88(%0)\n"
+		"flw f23, 92(%0)\n"
+		"flw f24, 96(%0)\n"
+		"flw f25, 100(%0)\n"
+		"flw f26, 104(%0)\n"
+		"flw f27, 108(%0)\n"
+		"flw f28, 112(%0)\n"
+		"flw f29, 116(%0)\n"
+		"flw f30, 120(%0)\n"
+		"flw f31, 124(%0)\n"
+		:
+		: "r"(src->f)
+		: "memory"
+	);
+
+#endif
+
+	csr_write(CSR_FCSR, src->fcsr);
+}
+#else
+void sbi_fp_save(struct sbi_fp_context *dst) {}
+void sbi_fp_restore(const struct sbi_fp_context *src) {}
+#endif // FP present
-- 
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[PATCH v5 3/3] lib: sbi: domain FP/Vector context support for context switch

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

This patch adds proper support for per-domain floating-point (FP) and
vector (V) contexts in the domain context switch logic. Each domain
now maintains its own FP and vector state, which is saved and restored
during domain switches.

Conditionalize FP and Vector save/restore based on extensions, unconditional
save and restore of floating-point (FP) and Vector registers fails on
generic platform firmware. This firmware must run on multiple platforms
that may lack these extensions.

Address this by conditionally executing FP save/restore only if the underlying
hart supports the F or D extensions. Similarly, perform Vector save/restore
only if the hart supports the Vector extension.

Changes include:

- Added `fp_ctx` and `vec_ctx` members to `struct hart_context`.
- Introduced dynamic vector struct allocation for vlenb in 'struct hart_context'
  to allocate and free per-domain FP and vector context.
- Modified `sbi_domain_register()` to initialize FP/Vector context per domain.
- Updated `switch_to_next_domain_context()` to save/restore FP and vector
  contexts safely:
    - Ensures FS/VS fields in `mstatus` are enabled (set to Initial) only if Off.
- Added runtime checks for FP and vector extensions where needed.
- Added SBI_HART_EXT_F, SBI_HART_EXT_D, SBI_HART_EXT_V to enum
  sbi_hart_extensions and the sbi_hart_ext[] array. Use sbi_hart_has_extension()
  to check for these capabilities before performing the context switches

This improves support for multi-domain systems with FP and Vector
extensions, and prevents corruption of FP/Vector state during domain
switches.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
---
 include/sbi/sbi_hart.h       |  6 ++++++
 lib/sbi/sbi_domain_context.c | 40 ++++++++++++++++++++++++++++++++++++
 lib/sbi/sbi_hart.c           |  3 +++
 3 files changed, 49 insertions(+)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index a788b34c..68a01b97 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -87,6 +87,12 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_XSIFIVE_CFLUSH_D_L1,
 	/** Hart has Xsfcease extension */
 	SBI_HART_EXT_XSIFIVE_CEASE,
+	/** Hart has V extension */
+	SBI_HART_EXT_V,
+	/** Hart has F extension */
+	SBI_HART_EXT_F,
+	/** Hart has D extension */
+	SBI_HART_EXT_D,
 
 	/** Maximum index of Hart extension */
 	SBI_HART_EXT_MAX,
diff --git a/lib/sbi/sbi_domain_context.c b/lib/sbi/sbi_domain_context.c
index 158f4990..46485728 100644
--- a/lib/sbi/sbi_domain_context.c
+++ b/lib/sbi/sbi_domain_context.c
@@ -18,6 +18,8 @@
 #include <sbi/sbi_domain_context.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_trap.h>
+#include <sbi/sbi_vector.h>
+#include <sbi/sbi_fp.h>
 
 /** Context representation for a hart within a domain */
 struct hart_context {
@@ -55,6 +57,11 @@ struct hart_context {
 	struct hart_context *prev_ctx;
 	/** Is context initialized and runnable */
 	bool initialized;
+
+	/** float context state */
+	struct sbi_fp_context fp_ctx;
+	/** vector context state */
+	struct sbi_vector_context *vec_ctx;
 };
 
 static struct sbi_domain_data dcpriv;
@@ -143,6 +150,25 @@ static int switch_to_next_domain_context(struct hart_context *ctx,
 	if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSQOSID))
 		ctx->srmcfg	= csr_swap(CSR_SRMCFG, dom_ctx->srmcfg);
 
+	/* Make sure FS and VS is on before context switch */
+	csr_set(CSR_MSTATUS, MSTATUS_FS | MSTATUS_VS);
+
+	/* Eager context switch F and V */
+
+	if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
+				   SBI_HART_EXT_F) ||
+	    sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
+				   SBI_HART_EXT_D)) {
+		sbi_fp_save(&ctx->fp_ctx);
+		sbi_fp_restore(&dom_ctx->fp_ctx);
+	}
+
+	if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
+				   SBI_HART_EXT_V)) {
+		sbi_vector_save(ctx->vec_ctx);
+		sbi_vector_restore(dom_ctx->vec_ctx);
+	}
+
 	/* Save current trap state and restore target domain's trap state */
 	trap_ctx = sbi_trap_get_context(scratch);
 	sbi_memcpy(&ctx->trap_ctx, trap_ctx, sizeof(*trap_ctx));
@@ -180,6 +206,20 @@ static int hart_context_init(u32 hartindex)
 		if (!ctx)
 			return SBI_ENOMEM;
 
+		if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
+					   SBI_HART_EXT_V)) {
+			unsigned long vlenb = vector_vlenb();
+			/* Calculate size: base struct + 32 registers of vlenb size */
+			size_t vec_size = sizeof(struct sbi_vector_context) + (32 * vlenb);
+
+			/* Allocate the vector context pointer */
+			ctx->vec_ctx = sbi_zalloc(vec_size);
+			if (!ctx->vec_ctx) {
+				sbi_free(ctx);
+				return SBI_ENOMEM;
+			}
+		}
+
 		/* Bind context and domain */
 		ctx->dom = dom;
 		hart_context_set(dom, hartindex, ctx);
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 60e95bca..b5e0ee10 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -396,6 +396,9 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = {
 	__SBI_HART_EXT_DATA(ssstateen, SBI_HART_EXT_SSSTATEEN),
 	__SBI_HART_EXT_DATA(xsfcflushdlone, SBI_HART_EXT_XSIFIVE_CFLUSH_D_L1),
 	__SBI_HART_EXT_DATA(xsfcease, SBI_HART_EXT_XSIFIVE_CEASE),
+	__SBI_HART_EXT_DATA(v, SBI_HART_EXT_V),
+	__SBI_HART_EXT_DATA(f, SBI_HART_EXT_F),
+	__SBI_HART_EXT_DATA(d, SBI_HART_EXT_D),
 };
 
 _Static_assert(SBI_HART_EXT_MAX == array_size(sbi_hart_ext),
-- 
2.43.0


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