Re: [PATCH v9 0/7] Add RISC-V big-endian target support

["Michael S. Tsirkin" <mst@redhat.com>]

On Mon, May 11, 2026 at 08:38:26AM +0000, Djordje Todorovic wrote:
> Rebase on top of master.

is Linux going to support this, ever? given this history:

https://lore.kernel.org/lkml/CAHk-%3DwgYcOiFvsJzFb%2BHfB4n6Wj6zM5H5EghUMfpXSCzyQVSfA@mail.gmail.com/t/#mce138059dc56014643bbda330810183031ef5c06

pls include a cover letter explaining why we should bother with this.


> Djordje Todorovic (7):
>   target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks
>   target/riscv: Add big-endian CPU configuration field and reset logic
>   target/riscv: Implement runtime data endianness via MSTATUS bits
>   hw/riscv: Make boot code endianness-aware at runtime
>   target/riscv: Fix page table walk endianness for big-endian harts
>   target/riscv: Expose big-endian CPU property and add documentation
>   target/riscv: Add endianness test for RISC-V BE
> 
>  docs/system/target-riscv.rst                  | 24 ++++++
>  hw/riscv/boot.c                               | 81 ++++++++++++++++---
>  include/hw/riscv/boot.h                       |  1 +
>  target/riscv/cpu.c                            | 11 +--
>  target/riscv/cpu.h                            | 23 ++++++
>  target/riscv/cpu_bits.h                       |  2 +
>  target/riscv/cpu_cfg_fields.h.inc             |  1 +
>  target/riscv/cpu_helper.c                     | 28 +++++--
>  target/riscv/insn_trans/trans_rva.c.inc       |  4 +-
>  target/riscv/insn_trans/trans_rvd.c.inc       |  4 +-
>  target/riscv/insn_trans/trans_rvf.c.inc       |  4 +-
>  target/riscv/insn_trans/trans_rvi.c.inc       |  8 +-
>  target/riscv/insn_trans/trans_rvzacas.c.inc   |  4 +-
>  target/riscv/insn_trans/trans_rvzalasr.c.inc  |  4 +-
>  target/riscv/insn_trans/trans_rvzce.c.inc     |  4 +-
>  target/riscv/insn_trans/trans_rvzfh.c.inc     |  4 +-
>  target/riscv/insn_trans/trans_rvzicfiss.c.inc |  4 +-
>  target/riscv/insn_trans/trans_xmips.c.inc     |  8 +-
>  target/riscv/insn_trans/trans_xthead.c.inc    | 16 ++--
>  target/riscv/insn_trans/trans_zilsd.c.inc     |  4 +-
>  target/riscv/internals.h                      |  9 +--
>  target/riscv/tcg/tcg-cpu.c                    |  3 +
>  target/riscv/translate.c                      | 22 ++---
>  tests/functional/riscv64/meson.build          |  1 +
>  tests/functional/riscv64/test_endianness.py   | 57 +++++++++++++
>  25 files changed, 251 insertions(+), 80 deletions(-)
>  create mode 100644 tests/functional/riscv64/test_endianness.py
> 
> -- 
> 2.34.1