* [PATCH v6 0/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions
@ 2026-05-20 9:56 Akihiko Odaki
2026-05-20 9:56 ` [PATCH v6 1/4] test/acpi: aarch64/virt: Test version 11.0 Akihiko Odaki
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Akihiko Odaki @ 2026-05-20 9:56 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Akihiko Odaki, Mohamed Mediouni
Remove the lower bound of the Highmem IO Regions' addresses for the
latest machine version to increase the chance to fit the regions in the
PA space.
The lower bound was especially problematic when using virt-install on
Apple M2. virt-install 5.0.0 adds multiple pcie-root-port devices that
require sufficient space in the ECAM region. However, the Highmem ECAM
region did not fit in the limited PA space on the hardware, and the ECAM
region size was limited to 16 MiB. If virt-install had added more than
16 devices to the root bridge, the region overflowed, which prevented
edk2-stable202505 from scanning PCI devices, including the boot disk,
causing boot failures.
Ideally, a virtual machine with more than 16 devices added to the root
bridge should just work so that users and management layers do not have
to care whether they use constrained hardware.
The base address of the Highmem IO Regions was fixed when commit
f90747c4e8fb ("hw/arm/virt: GICv3 DT node with one or two redistributor
regions") added the first Highmem IO Region. Later, commit 957e32cffa57
("hw/arm/virt: Dynamic memory map depending on RAM requirements")
allowed moving the Highmem IO Regions to higher addresses to accommodate
RAM more than 255 GiB, but the lower bound remained to keep the legacy
memory map.
Remove the lower bound for the latest machine version to accommodate
more devices with the root bridge. Keeping the lower bound for the old
machine versions ensures the compatibility is still maintained.
The hardcoded memory map in tests/qtest/libqos/generic-pcihost.c is also
updated.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
---
Changes in v6:
- Rebased.
- Link to v5: https://lore.kernel.org/qemu-devel/20260129-virt-v5-0-421c0abaaf26@rsg.ci.i.u-tokyo.ac.jp
Changes in v5:
- Changed to preserve memory layout for 10.2.
- Added patch "test/acpi: aarch64/virt: Test version 10.2".
- Link to v4: https://lore.kernel.org/qemu-devel/20260125-virt-v4-0-00d726b27224@rsg.ci.i.u-tokyo.ac.jp
Changes in v4:
- Rebased.
- Edited the patch message to avoid confusing git am.
- Link to v3: https://lore.kernel.org/qemu-devel/20251027-virt-v3-0-fa2a2f37e32d@rsg.ci.i.u-tokyo.ac.jp
Changes in v3:
- Fixed test failures reported by Peter Maydell.
- Link to v2: https://lore.kernel.org/qemu-devel/20250901-virt-v2-1-ac2379402c80@rsg.ci.i.u-tokyo.ac.jp
Changes in v2:
- Rebased.
- Link to v1: https://lore.kernel.org/qemu-devel/20250728-virt-v1-1-0ab9682262c8@rsg.ci.i.u-tokyo.ac.jp
---
Akihiko Odaki (4):
test/acpi: aarch64/virt: Test version 11.0
test/acpi: aarch64/virt: Allow DSDT and MCFG changes
hw/arm/virt: Remove the lower bound of HighMem IO Regions
test/acpi: aarch64/virt: Update golden masters for DSDT and MCFG
include/hw/arm/virt.h | 1 +
hw/arm/virt.c | 17 ++++++++++------
tests/qtest/bios-tables-test.c | 24 +++++++++++++++++++++++
tests/qtest/libqos/generic-pcihost.c | 2 +-
tests/data/acpi/aarch64/virt/DSDT | Bin 5337 -> 5333 bytes
tests/data/acpi/aarch64/virt/DSDT.11.0 | Bin 0 -> 5337 bytes
tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5423 -> 5419 bytes
tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 6246 -> 6242 bytes
tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 5391 -> 5387 bytes
tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6698 -> 6698 bytes
tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7812 -> 7808 bytes
tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev | Bin 10274 -> 10270 bytes
tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy | Bin 10274 -> 10270 bytes
tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5539 -> 5535 bytes
tests/data/acpi/aarch64/virt/DSDT.viot | Bin 5354 -> 5350 bytes
tests/data/acpi/aarch64/virt/MCFG | Bin 60 -> 60 bytes
tests/data/acpi/aarch64/virt/MCFG.11.0 | Bin 0 -> 60 bytes
tests/data/acpi/aarch64/virt/MCFG.memhp | Bin 0 -> 60 bytes
18 files changed, 37 insertions(+), 7 deletions(-)
---
base-commit: e89049b3ba5f1f0468bc0d294173345597514a1b
change-id: 20250728-virt-833dafa6c11b
Best regards,
--
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v6 1/4] test/acpi: aarch64/virt: Test version 11.0
2026-05-20 9:56 [PATCH v6 0/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
@ 2026-05-20 9:56 ` Akihiko Odaki
2026-05-20 13:07 ` Igor Mammedov
2026-05-20 9:56 ` [PATCH v6 2/4] test/acpi: aarch64/virt: Allow DSDT and MCFG changes Akihiko Odaki
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Akihiko Odaki @ 2026-05-20 9:56 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Akihiko Odaki, Mohamed Mediouni
A future commit changes the memory map for the latest version of the
machine. Test that the memory map of the previous version is preserved.
Suggested-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
---
tests/qtest/bios-tables-test.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 510751799e48..00e62699197a 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2214,6 +2214,28 @@ static void test_acpi_aarch64_virt_tcg(void)
free_test_data(&data);
}
+static void test_acpi_aarch64_virt_tcg_11_0(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .machine_param = "-11.0",
+ .arch = "aarch64",
+ .variant = ".11.0",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 128ULL * MiB,
+ };
+
+ data.smbios_cpu_max_speed = 2900;
+ data.smbios_cpu_curr_speed = 2700;
+ test_acpi_one("-cpu cortex-a57 -machine ras=on "
+ "-smbios type=4,max-speed=2900,current-speed=2700", &data);
+ free_test_data(&data);
+}
+
static void test_acpi_aarch64_virt_tcg_topology(void)
{
test_data data = {
@@ -2851,6 +2873,8 @@ int main(int argc, char *argv[])
} else if (strcmp(arch, "aarch64") == 0) {
if (has_tcg && qtest_has_device("virtio-blk-pci")) {
qtest_add_func("acpi/virt", test_acpi_aarch64_virt_tcg);
+ qtest_add_func("acpi/virt/11.0",
+ test_acpi_aarch64_virt_tcg_11_0);
qtest_add_func("acpi/virt/acpihmatvirt",
test_acpi_aarch64_virt_tcg_acpi_hmat);
qtest_add_func("acpi/virt/topology",
--
2.54.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 2/4] test/acpi: aarch64/virt: Allow DSDT and MCFG changes
2026-05-20 9:56 [PATCH v6 0/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
2026-05-20 9:56 ` [PATCH v6 1/4] test/acpi: aarch64/virt: Test version 11.0 Akihiko Odaki
@ 2026-05-20 9:56 ` Akihiko Odaki
2026-05-20 13:07 ` Igor Mammedov
2026-05-20 9:56 ` [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
2026-05-20 9:56 ` [PATCH v6 4/4] test/acpi: aarch64/virt: Update golden masters for DSDT and MCFG Akihiko Odaki
3 siblings, 1 reply; 10+ messages in thread
From: Akihiko Odaki @ 2026-05-20 9:56 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Akihiko Odaki
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..efb00724d09f 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,12 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/aarch64/virt/DSDT",
+"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/aarch64/virt/DSDT.acpipcihp",
+"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex",
+"tests/data/acpi/aarch64/virt/DSDT.memhp",
+"tests/data/acpi/aarch64/virt/DSDT.pxb",
+"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev",
+"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy",
+"tests/data/acpi/aarch64/virt/DSDT.topology",
+"tests/data/acpi/aarch64/virt/DSDT.viot",
+"tests/data/acpi/aarch64/virt/MCFG",
--
2.54.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions
2026-05-20 9:56 [PATCH v6 0/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
2026-05-20 9:56 ` [PATCH v6 1/4] test/acpi: aarch64/virt: Test version 11.0 Akihiko Odaki
2026-05-20 9:56 ` [PATCH v6 2/4] test/acpi: aarch64/virt: Allow DSDT and MCFG changes Akihiko Odaki
@ 2026-05-20 9:56 ` Akihiko Odaki
2026-05-20 13:51 ` Igor Mammedov
2026-05-20 9:56 ` [PATCH v6 4/4] test/acpi: aarch64/virt: Update golden masters for DSDT and MCFG Akihiko Odaki
3 siblings, 1 reply; 10+ messages in thread
From: Akihiko Odaki @ 2026-05-20 9:56 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Akihiko Odaki
Remove the lower bound of the Highmem IO Regions' addresses for the
latest machine version to increase the chance to fit the regions in the
PA space.
The lower bound was especially problematic when using virt-install on
Apple M2. virt-install 5.0.0 adds multiple pcie-root-port devices that
require sufficient space in the ECAM region. However, the Highmem ECAM
region did not fit in the limited PA space on the hardware, and the ECAM
region size was limited to 16 MiB. If virt-install had added more than
16 devices to the root bridge, the region overflowed, which prevented
edk2-stable202505 from scanning PCI devices, including the boot disk,
causing boot failures.
Ideally, a virtual machine with more than 16 devices added to the root
bridge should just work so that users and management layers do not have
to care whether they use constrained hardware.
The base address of the Highmem IO Regions was fixed when commit
f90747c4e8fb ("hw/arm/virt: GICv3 DT node with one or two redistributor
regions") added the first Highmem IO Region. Later, commit 957e32cffa57
("hw/arm/virt: Dynamic memory map depending on RAM requirements")
allowed moving the Highmem IO Regions to higher addresses to accommodate
RAM more than 255 GiB, but the lower bound remained to keep the legacy
memory map.
Remove the lower bound for the latest machine version to accommodate
more devices with the root bridge. Keeping the lower bound for the old
machine versions ensures the compatibility is still maintained.
The hardcoded memory map in tests/qtest/libqos/generic-pcihost.c is also
updated.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
---
include/hw/arm/virt.h | 1 +
hw/arm/virt.c | 17 +++++++++++------
tests/qtest/libqos/generic-pcihost.c | 2 +-
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 3ba33b4bd274..6c8ba8f3185b 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -142,6 +142,7 @@ typedef enum VirtGICType {
struct VirtMachineClass {
MachineClass parent;
+ hwaddr min_highmem_base;
bool no_tcg_its;
bool no_highmem_compact;
bool no_kvm_steal_time;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b090233893c5..78a85a966ad7 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -229,8 +229,7 @@ static const MemMapEntry base_memmap[] = {
* Highmem IO Regions: This memory map is floating, located after the RAM.
* Each MemMapEntry base (GPA) will be dynamically computed, depending on the
* top of the RAM, so that its base get the same alignment as the size,
- * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
- * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
+ * ie. a 512GiB entry will be aligned on a 512GiB boundary.
* Note the extended_memmap is sized so that it eventually also includes the
* base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
* index of base_memmap).
@@ -2479,6 +2478,7 @@ static void virt_set_high_memmap(VirtMachineState *vms,
static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
{
MachineState *ms = MACHINE(vms);
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
hwaddr base, device_memory_base, device_memory_size, memtop;
int i;
@@ -2505,8 +2505,7 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
/*
* We compute the base of the high IO region depending on the
* amount of initial and device memory. The device memory start/size
- * is aligned on 1GiB. We never put the high IO region below 256GiB
- * so that if maxram_size is < 255GiB we keep the legacy memory map.
+ * is aligned on 1GiB.
* The device region size assumes 1GiB page max alignment per slot.
*/
device_memory_base =
@@ -2524,8 +2523,8 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
error_report("maxmem/slots too huge");
exit(EXIT_FAILURE);
}
- if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
- base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
+ if (base < vmc->min_highmem_base) {
+ base = vmc->min_highmem_base;
}
/* We know for sure that at least the memory fits in the PA space */
@@ -4367,6 +4366,12 @@ static void virt_machine_11_0_options(MachineClass *mc)
virt_machine_11_1_options(mc);
compat_props_add(mc->compat_props, hw_compat_11_0, hw_compat_11_0_len);
vmc->hvf_no_kernel_irqchip_default = true;
+
+ /*
+ * Do not put the high IO region below 256GiB so that if maxram_size is
+ * < 255GiB we keep the legacy memory map.
+ */
+ vmc->min_highmem_base = base_memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
}
DEFINE_VIRT_MACHINE(11, 0)
diff --git a/tests/qtest/libqos/generic-pcihost.c b/tests/qtest/libqos/generic-pcihost.c
index b77617524cac..287e8445ec5b 100644
--- a/tests/qtest/libqos/generic-pcihost.c
+++ b/tests/qtest/libqos/generic-pcihost.c
@@ -210,7 +210,7 @@ void qpci_init_generic(QGenericPCIBus *qpci, QTestState *qts,
qpci->bus.pio_limit = 0x10000;
qpci->bus.mmio_alloc_ptr = 0x10000000;
qpci->bus.mmio_limit = 0x2eff0000;
- qpci->ecam_alloc_ptr = 0x4010000000;
+ qpci->ecam_alloc_ptr = 0x90000000;
qpci->obj.get_driver = qpci_generic_get_driver;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 4/4] test/acpi: aarch64/virt: Update golden masters for DSDT and MCFG
2026-05-20 9:56 [PATCH v6 0/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
` (2 preceding siblings ...)
2026-05-20 9:56 ` [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
@ 2026-05-20 9:56 ` Akihiko Odaki
3 siblings, 0 replies; 10+ messages in thread
From: Akihiko Odaki @ 2026-05-20 9:56 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Akihiko Odaki
@@ -1,36 +1,36 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
- * Disassembly of tests/data/acpi/aarch64/virt/MCFG
+ * Disassembly of /tmp/aml-EFVEJ3
*
* ACPI Data Table [MCFG]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex)
*/
[000h 0000 004h] Signature : "MCFG" [Memory Mapped Configuration Table]
[004h 0004 004h] Table Length : 0000003C
[008h 0008 001h] Revision : 01
-[009h 0009 001h] Checksum : EC
+[009h 0009 001h] Checksum : AC
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
[024h 0036 008h] Reserved : 0000000000000000
-[02Ch 0044 008h] Base Address : 0000004010000000
+[02Ch 0044 008h] Base Address : 0000000090000000
[034h 0052 002h] Segment Group Number : 0000
[036h 0054 001h] Start Bus Number : 00
[037h 0055 001h] End Bus Number : FF
[038h 0056 004h] Reserved : 00000000
Raw Table Data: Length 60 (0x3C)
- 0000: 4D 43 46 47 3C 00 00 00 01 EC 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0000: 4D 43 46 47 3C 00 00 00 01 AC 42 4F 43 48 53 20 // MCFG<.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................
- 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @...........
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT
+ * Disassembly of /tmp/aml-5GVEJ3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x000014D9 (5337)
+ * Length 0x000014D5 (5333)
* Revision 0x02
- * Checksum 0xA5
+ * Checksum 0xF7
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1751,33 +1751,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1840,34 +1840,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt
+ * Disassembly of /tmp/aml-HQ03I3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000152F (5423)
+ * Length 0x0000152B (5419)
* Revision 0x02
- * Checksum 0x70
+ * Checksum 0xB3
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1769,33 +1769,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1858,34 +1858,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.topology
+ * Disassembly of /tmp/aml-UC05I3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x000015A3 (5539)
+ * Length 0x0000159F (5535)
* Revision 0x02
- * Checksum 0x99
+ * Checksum 0xEB
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1793,33 +1793,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1882,34 +1882,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT
+ * Disassembly of /tmp/aml-TZRGJ3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x000014D9 (5337)
+ * Length 0x000014D5 (5333)
* Revision 0x02
- * Checksum 0xA5
+ * Checksum 0xF7
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1751,33 +1751,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1840,34 +1840,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT
+ * Disassembly of /tmp/aml-9EZ4I3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x000014D9 (5337)
+ * Length 0x000014D5 (5333)
* Revision 0x02
- * Checksum 0xA5
+ * Checksum 0xF7
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1751,33 +1751,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1840,34 +1840,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.memhp
+ * Disassembly of /tmp/aml-32Q9I3
*
* Original Table Header:
* Signature "DSDT"
* Length 0x00001A2A (6698)
* Revision 0x02
- * Checksum 0xD4
+ * Checksum 0x11
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
External (_SB_.NVDR, UnknownObj)
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
@@ -1753,33 +1753,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x0000000190000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1842,34 +1842,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000190000000, // Range Minimum
+ 0x000000019FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.acpipcihp
+ * Disassembly of /tmp/aml-DCVWI3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001866 (6246)
+ * Length 0x00001862 (6242)
* Revision 0x02
- * Checksum 0x71
+ * Checksum 0xC3
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1751,33 +1751,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1840,34 +1840,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
+ * Disassembly of /tmp/aml-KHOBJ3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000150F (5391)
+ * Length 0x0000150B (5387)
* Revision 0x02
- * Checksum 0x4C
+ * Checksum 0x9E
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1751,33 +1751,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1840,34 +1840,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.pxb
+ * Disassembly of /tmp/aml-FHLGJ3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001E84 (7812)
+ * Length 0x00001E80 (7808)
* Revision 0x02
- * Checksum 0x15
+ * Checksum 0x67
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -2936,33 +2936,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x007F, // Range Maximum
0x0000, // Translation Offset
0x0080, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -3025,34 +3025,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT
+ * Disassembly of /tmp/aml-BP7DJ3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x000014D9 (5337)
+ * Length 0x000014D5 (5333)
* Revision 0x02
- * Checksum 0xA5
+ * Checksum 0xF7
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1751,33 +1751,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1840,34 +1840,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.viot
+ * Disassembly of /tmp/aml-ARLYI3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x000014EA (5354)
+ * Length 0x000014E6 (5350)
* Revision 0x02
- * Checksum 0x47
+ * Checksum 0x99
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -1751,33 +1751,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -1840,34 +1840,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy
+ * Disassembly of /tmp/aml-XDBZI3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00002822 (10274)
+ * Length 0x0000281E (10270)
* Revision 0x02
- * Checksum 0xAB
+ * Checksum 0xFD
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -4121,33 +4121,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x000F, // Range Maximum
0x0000, // Translation Offset
0x0010, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -4210,34 +4210,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20240322 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev
+ * Disassembly of /tmp/aml-OB0ZI3
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00002822 (10274)
+ * Length 0x0000281E (10270)
* Revision 0x02
- * Checksum 0xAB
+ * Checksum 0xFD
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\_SB)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
@@ -4121,33 +4121,33 @@
0x001FFFFF,
0x02,
L001,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x03,
L002,
Zero
}
})
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
- Return (0x0000004010000000)
+ Return (0x90000000)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x000F, // Range Maximum
0x0000, // Translation Offset
0x0010, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFEFFFF, // Range Maximum
0x00000000, // Translation Offset
@@ -4210,34 +4210,34 @@
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- 0x0000004010000000, // Range Minimum
- 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000090000000, // Range Minimum
+ 0x000000009FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
}
Device (\_SB.GED)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, "GED") // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
{
0x00000029,
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
---
tests/qtest/bios-tables-test-allowed-diff.h | 11 -----------
tests/data/acpi/aarch64/virt/DSDT | Bin 5337 -> 5333 bytes
tests/data/acpi/aarch64/virt/DSDT.11.0 | Bin 0 -> 5337 bytes
tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5423 -> 5419 bytes
tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 6246 -> 6242 bytes
tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 5391 -> 5387 bytes
tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6698 -> 6698 bytes
tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7812 -> 7808 bytes
tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev | Bin 10274 -> 10270 bytes
tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy | Bin 10274 -> 10270 bytes
tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5539 -> 5535 bytes
tests/data/acpi/aarch64/virt/DSDT.viot | Bin 5354 -> 5350 bytes
tests/data/acpi/aarch64/virt/MCFG | Bin 60 -> 60 bytes
tests/data/acpi/aarch64/virt/MCFG.11.0 | Bin 0 -> 60 bytes
tests/data/acpi/aarch64/virt/MCFG.memhp | Bin 0 -> 60 bytes
15 files changed, 11 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index efb00724d09f..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,12 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/aarch64/virt/DSDT",
-"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
-"tests/data/acpi/aarch64/virt/DSDT.acpipcihp",
-"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex",
-"tests/data/acpi/aarch64/virt/DSDT.memhp",
-"tests/data/acpi/aarch64/virt/DSDT.pxb",
-"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev",
-"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy",
-"tests/data/acpi/aarch64/virt/DSDT.topology",
-"tests/data/acpi/aarch64/virt/DSDT.viot",
-"tests/data/acpi/aarch64/virt/MCFG",
diff --git a/tests/data/acpi/aarch64/virt/DSDT b/tests/data/acpi/aarch64/virt/DSDT
index 35a862e44714d26ded01d40dc147e76cc73a1c84..649b1e78d57748d3d941c9b79d7d30cfb43ec7ca 100644
GIT binary patch
delta 65
zcmV-H0KWg(Db*<oL{mgm)f4~#0{4*$8v%*2CPxYZMzd}Tp$7~MUqeDc0Hh26005A)
X9}-ys3XlK*00960|DOP}f)iH(cgzzn
delta 69
zcmcbrc~g_iCD<k8rU(NA)6$7t(u}<u)!exly*B4@Eo2uEh<A2!WLUz-z`!8jz`($;
WSz0KPkqgZH|Np<d!{$2Sa7F-)LJ}(g
diff --git a/tests/data/acpi/aarch64/virt/DSDT.11.0 b/tests/data/acpi/aarch64/virt/DSDT.11.0
new file mode 100644
index 0000000000000000000000000000000000000000..35a862e44714d26ded01d40dc147e76cc73a1c84
GIT binary patch
literal 5337
zcmZvgOK%%h6oAjzV|zS)Wc)}RJ5KCEsdz?XyLq&<1$)Lx+}erpqz#fQjVn|{8y1$R
zkV=J=8mTRjSkMU8MhgD}i4{9`2(f0vA7F>koja49qn=qfzK`?W``w(8j<4<5`+w#E
zLO-|mtR1J?`nYdZtJSIk0OGs&Ykb#I?z&FP9ZpJ?X_}h5)3H-ctKTtAa|1N@cE^U{
z<f^sT3&sY$9n-AU{4ve722Q4=7oNpI0OMc)d>aKtxc~r<VK~{`I<U4R_oH_2wrQGm
z&|GJ~sV6kovYLuSWc0K|gyM^SWK+E}2)5MS9qgH=xpuznS>*ZRI)wbiO^m3?)hR+O
z`wAk25H%ms61%8#2tC9xRK%!bMuTO9IYtyQ8kljJWvCoOLyXIqvBokY979KpHOyFN
z8BvarM2vOJ*kBnkj*&);4b0eN85+kh5MvWFuCR<a$H*ea6~w6dF9%IAUFR5i#JGwX
zY?{)SBuMoI#CRVw_&iN=`&dMbYnZ|3X^LZ%5aT*#@Ohf%7-ht`ff;<B&T)(t#P|R+
z_&hZ@MintW#0)-9GaTbJ#Asp$pQl-laS<_En8D|1j$>Rx3=1*pe4gex#+!&?V+Nn6
z^Bm)C#Ass%pQj5P<6Xqq!VEr73mjt=F}5*-&(lSYVIsy3X7G7h<QR3t=wJq)rzMVY
z88L2R2A`)(9Ah0ZZea$Wr)7?@i5OkX;PZ5uV_Zdy9%3~3JYC@!*AQbDGx$8MaEu#>
zvF9^7YWJ)l>hJbV%iKCEKKcVElhzYno%6akUluX6FCTTCfujs1%HIw_DH=gtWKgp2
z40TiN%71$ZN)#h_TW>Hd*+*IaTSQr5%DTj`WZyaKW#8)f|24sCnw#QGI=0_xh?=jx
z4Vv3(?Vg>Zvp>jG^l~38=)irbf(ccy;XZr`58xBH4<I03nbsfd=el3$N7;m$n9V@^
zZ$N%mx~5r!Y*O^=A#prGBiuF324queayC;y#MI7OBB~DAv>fx|8s|+BY5H?RUS$2O
zB_e~VAsK1<ks<IRgH^&_WUzy<7a2?q%gCA^8J3a3DykP5>_GJ*gQ=>F3^uRI$Y7NS
z@r)492=$D}$Y7Ny@r)ABDD{j|&lvHH5ziR)j8RXGcxuE`qn;Y|j1$i|@r+Z?IQ7(t
zr%pU|>Zw!D1o2D|&jj^MP|qasOcKu|^-NOF6!A<E&lL4cQO`8-OcT#E^-NRGIpR4-
zJm;wA9Q8Dar$Iao>S<8V4Drkm&kXg<P|qy!%o5Km^~_Sw9P!K%&m8s4QO`W_%oEQ%
z^~_VxdEz-wJm;zBJoQ{4o(sftfqE`b&jRr*5YGbjEKtuy;<-pX7pdnW^(+$4BJnIz
z&m#3K5zi9wEK$!A^;{yJOT=@DdM;7VGVv@E&ocEaQ_p4MxlBBlspm5FTp^w-#B+su
zu29bk@vIQf3iYf6o_WKyT1_}ji(4P@`$kqQJ2Cyyixh;CAfB1{P@We6lHxK)JjQJH
zpZHlOMpvH~KuLyW3t;9=pWOgZ;P@RB<2^^-jG3H-9?}08^4*xb=UD3TAz1c7ZMqvd
z`7D#ujbZPv#=n*Fhd&-XYW{Nlk57*eb=9&D>c@w=X4wagvG^E08R?bL)OdOFK>1pP
zdt<d}?&XO$Ec*;GG9HPZpOUgmplYXw`S)Dg>8aBTa?Rg2e*4>5`>OYS;h$ddSF1OT
zpFD)qOjwa0!%0sav>jC3Sl$(uxcF-5<}2pj>CR@eia2HT7~;FQ5wo<rtK!aWyKTGj
z?m=F-)kKkWyJM%e+cqgE!^&GS^r$^(Z$lD5i|gv}X+kuuw$tub^Q&(A&VGC>8l$Ok
z@?@lo+T>aPV9?T!WJeYB>a*>(ZR<zFNl}c*)n)Bx`Bm9)QWSI0P{ZFB7+e0%MXi^=
z6=~Z}FEw31c?e^1TBB*{C4Zu)qiO7i2YTpqG}fQK7y+D)rsb1|dTgAHgdhc@@i#9%
f2e>!BCkKa<gkzen<~HpC3@3ArxhWe-k!$}0AN?LZ
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt b/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt
index 7ce35f0d8606d17f3ddb9aa090c97c7ac9a38982..aa813cbcc4e8ac8ba7c68c3aac590eaa0eb90a28 100644
GIT binary patch
delta 66
zcmV-I0KNaODyu3AL{mgmD-{3$0<)0{8v>6<u_v4g0Y<aL3ZVxK3|~V+K>(x-0001x
Yvvm?#0Sb@+00030|Nox=v)B_?0cSN6mH+?%
delta 70
zcmZ3jwO)(MCD<iIUzCA?sbC_PG*h$3M)f&dj9#0Ma4lpP5Qukna%5P-$H2fK;K0DZ
Xu(?nul93C{{Qv*Iyu;=z!r_bndzTWD
diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpipcihp b/tests/data/acpi/aarch64/virt/DSDT.acpipcihp
index 6d1765c31017dede80d1d87f8fa7c6dd055d1839..5bd4a06dd193f065e2b9d2686bb371ebb3bfc620 100644
GIT binary patch
delta 65
zcmV-H0KWg`Fyb%@L{mgmVi*7b0>hCC8v%#0CPxYZMzd}Tp$7~MUqeDc0Hh26005A)
X9}-ys3XlK*00960|DOP}f)nHfU)K{t
delta 69
zcmaE4@XUbACD<h-O@e`esc<5fG-LNhHFqvXug!T}3)uw(;+>rw8J6%dFfa%>FfcG|
WmKKU+<N`DQ|Nk%Vu(?k72@3#oSrR?~
diff --git a/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex b/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
index 61cce30c7471faa4a9b7e3562dcb4ab9b3519a21..ec8ebbfdafabdd790297ec8728e9922c24c1b132 100644
GIT binary patch
delta 65
zcmeCz>ek|N33dtL7G+>ynm3V4nz3`EnmZSx+vYs3h3q^$@y<?;3`=+z7#JpOmKTa-
V<eI?1z`*eT|Nr?6o127t837go5wQRO
delta 69
zcmeCy>eu3O33dtL7iC~z@|nmb&Dgt9&7F(UYjYmgLUsXxcxNX^h9!Iq3=9Ge3=9mL
WrG+9Hxxmc-|NqN7Y_1dTWdr~us1U6H
diff --git a/tests/data/acpi/aarch64/virt/DSDT.memhp b/tests/data/acpi/aarch64/virt/DSDT.memhp
index ffc5f1c0d1090582672c60ade3eb1bc41acc5ef7..8a6cafac00d406077d6a369747c6e383d94a0786 100644
GIT binary patch
delta 43
zcmZ2wvdV<ZCD<iIONxPkNpK^VfDqFJ#?3N9F^pUj7#SEC{{R0!pK)`O@Cr5n?UM{C
delta 43
zcmZ2wvdV<ZCD<iIONxPk>B>ef0U;&<hs`oVF^pUS4h#$o|NsA&ci7w{yn+n?_kav3
diff --git a/tests/data/acpi/aarch64/virt/DSDT.pxb b/tests/data/acpi/aarch64/virt/DSDT.pxb
index f98dcbfc6b823bce6d5710e8056a4e260fb92a02..356e610fdffb6fea0a763517b62df0ed0c64ab97 100644
GIT binary patch
delta 65
zcmV-H0KWf(J%Bw5L{mgmfF1w<0%ws58v%x~Ce#xFMzi}9p$7~MUqeDc0Hh26005A)
XtQ%PY3XlK*00960|DOP}4;^&@V;K`h
delta 69
zcmZp$ZL#HY33dr-kz-(B5}n8;&Dgb3?TRp?*XG~C3)uw(;+>rw8J6%dFfa%>FfcG|
WULhUH$OUHp|Nmd!VKcXEDI)-PzY;<K
diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev
index 6c12a7aaf8a6315bac968a685f5b6673e7248817..f1419cbda7167ed5a36410f71c52e3d2a22218fe 100644
GIT binary patch
delta 73
zcmV-P0Ji_4P@Yf<L{mgm9w-0+0{xK+8v%o{CSe@~Mv_oNNt6E*AG50+eg_N;UqeDc
f0Hh26005A)IVD*E3XlK*00960|DOP}oF;|=B@-5f
delta 77
zcmbOiuqc4bCD<iINrQobY4t=dX~y=AYKgL}UXucxJtzMcmfyTuwvJsuAl})@kzolR
f0|SGA0|NuYW>eKjMlLY(|NsB;4x4AFwJ`z!LyZ-I
diff --git a/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy b/tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy
index 6c12a7aaf8a6315bac968a685f5b6673e7248817..f1419cbda7167ed5a36410f71c52e3d2a22218fe 100644
GIT binary patch
delta 73
zcmV-P0Ji_4P@Yf<L{mgm9w-0+0{xK+8v%o{CSe@~Mv_oNNt6E*AG50+eg_N;UqeDc
f0Hh26005A)IVD*E3XlK*00960|DOP}oF;|=B@-5f
delta 77
zcmbOiuqc4bCD<iINrQobY4t=dX~y=AYKgL}UXucxJtzMcmfyTuwvJsuAl})@kzolR
f0|SGA0|NuYW>eKjMlLY(|NsB;4x4AFwJ`z!LyZ-I
diff --git a/tests/data/acpi/aarch64/virt/DSDT.topology b/tests/data/acpi/aarch64/virt/DSDT.topology
index 208a3163a6bf2a59cf421418dcb16ad1156285c6..33a9c4c397ca498f5b3fbcc7e7e446fe8ac0b125 100644
GIT binary patch
delta 65
zcmV-H0KWgDE1xS0L{mgmpA`TA0_%|q8v%o{CJ_q(Mzc5zp$7~MUqeDc0Hh26005A)
X=@MB13XlK*00960|DOP}OcYlEOyd%(
delta 69
zcmbQQy;z&eCD<iou_yxr)69un(v0mJ)daa2y*68LFJu=Gh<A2!WLUz-z`!8jz`($;
W`KeGOBNv$Y|Nnn^hs_=$;fw%X^%184
diff --git a/tests/data/acpi/aarch64/virt/DSDT.viot b/tests/data/acpi/aarch64/virt/DSDT.viot
index f81e3e6cc794d77ea66b7e27b1afe56e248132b6..625ce32b13706b83d4400548dcf8b81485dba965 100644
GIT binary patch
delta 65
zcmV-H0KWg~Dds5(L{mgm<`e(`0-2Et8v%*2CPxYZMzd}Tp$7~MUqeDc0Hh26005A)
X9}-ys3XlK*00960|DOP}f)i)~acmP6
delta 69
zcmaE+`AU<^CD<k8l?Vd^llw$2X~y1-YVKT&UYql{7P1Qn#5+4VGA!X^U|<k%U|?X_
WEG-nt$OUHp|Nmd!VRM~u1|tB5HWCp4
diff --git a/tests/data/acpi/aarch64/virt/MCFG b/tests/data/acpi/aarch64/virt/MCFG
index f4ae3203a4e9258a397c9912332178640209637b..99e75f326c3c7fc3be5154c4667f34995e33dbc2 100644
GIT binary patch
delta 30
ecmcDq;qrBMbGKn&U|?J`kxP|#0s{p62T=f4aRlW6
delta 30
fcmcDq;qrBMbGKn&U|@VRkxP|Vz<~h_{)0#WS8)X8
diff --git a/tests/data/acpi/aarch64/virt/MCFG.11.0 b/tests/data/acpi/aarch64/virt/MCFG.11.0
new file mode 100644
index 0000000000000000000000000000000000000000..f4ae3203a4e9258a397c9912332178640209637b
GIT binary patch
literal 60
ucmeZuc5}C3U|?W;<K*w`5v<@85#X$#prF9Wz`y`vgJ>im-~i$L2T=ezMF;@^
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/aarch64/virt/MCFG.memhp b/tests/data/acpi/aarch64/virt/MCFG.memhp
new file mode 100644
index 0000000000000000000000000000000000000000..360f1dbbea17e4857f1c26a172ff533eef446823
GIT binary patch
literal 60
ucmeZuc5}C3U|?We?d0$55v<@85#X$#prF9Wz`y`vgJ>i$0m}am5(5A*-UtBz
literal 0
HcmV?d00001
--
2.54.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v6 1/4] test/acpi: aarch64/virt: Test version 11.0
2026-05-20 9:56 ` [PATCH v6 1/4] test/acpi: aarch64/virt: Test version 11.0 Akihiko Odaki
@ 2026-05-20 13:07 ` Igor Mammedov
0 siblings, 0 replies; 10+ messages in thread
From: Igor Mammedov @ 2026-05-20 13:07 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Ani Sinha, Fabiano Rosas, Laurent Vivier,
Paolo Bonzini, Mohamed Mediouni
On Wed, 20 May 2026 18:56:30 +0900
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
> A future commit changes the memory map for the latest version of the
> machine. Test that the memory map of the previous version is preserved.
>
> Suggested-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> tests/qtest/bios-tables-test.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 510751799e48..00e62699197a 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -2214,6 +2214,28 @@ static void test_acpi_aarch64_virt_tcg(void)
> free_test_data(&data);
> }
>
> +static void test_acpi_aarch64_virt_tcg_11_0(void)
> +{
> + test_data data = {
> + .machine = "virt",
> + .machine_param = "-11.0",
> + .arch = "aarch64",
> + .variant = ".11.0",
> + .tcg_only = true,
> + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
> + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
> + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
> + .ram_start = 0x40000000ULL,
> + .scan_len = 128ULL * MiB,
> + };
> +
> + data.smbios_cpu_max_speed = 2900;
> + data.smbios_cpu_curr_speed = 2700;
> + test_acpi_one("-cpu cortex-a57 -machine ras=on "
> + "-smbios type=4,max-speed=2900,current-speed=2700", &data);
> + free_test_data(&data);
> +}
> +
> static void test_acpi_aarch64_virt_tcg_topology(void)
> {
> test_data data = {
> @@ -2851,6 +2873,8 @@ int main(int argc, char *argv[])
> } else if (strcmp(arch, "aarch64") == 0) {
> if (has_tcg && qtest_has_device("virtio-blk-pci")) {
> qtest_add_func("acpi/virt", test_acpi_aarch64_virt_tcg);
> + qtest_add_func("acpi/virt/11.0",
> + test_acpi_aarch64_virt_tcg_11_0);
> qtest_add_func("acpi/virt/acpihmatvirt",
> test_acpi_aarch64_virt_tcg_acpi_hmat);
> qtest_add_func("acpi/virt/topology",
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 2/4] test/acpi: aarch64/virt: Allow DSDT and MCFG changes
2026-05-20 9:56 ` [PATCH v6 2/4] test/acpi: aarch64/virt: Allow DSDT and MCFG changes Akihiko Odaki
@ 2026-05-20 13:07 ` Igor Mammedov
0 siblings, 0 replies; 10+ messages in thread
From: Igor Mammedov @ 2026-05-20 13:07 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Ani Sinha, Fabiano Rosas, Laurent Vivier,
Paolo Bonzini
On Wed, 20 May 2026 18:56:31 +0900
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
> Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Acked-by: Igor Mammedov <imammedo@redhat.com>
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
> index dfb8523c8bf4..efb00724d09f 100644
> --- a/tests/qtest/bios-tables-test-allowed-diff.h
> +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> @@ -1 +1,12 @@
> /* List of comma-separated changed AML files to ignore */
> +"tests/data/acpi/aarch64/virt/DSDT",
> +"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt",
> +"tests/data/acpi/aarch64/virt/DSDT.acpipcihp",
> +"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex",
> +"tests/data/acpi/aarch64/virt/DSDT.memhp",
> +"tests/data/acpi/aarch64/virt/DSDT.pxb",
> +"tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev",
> +"tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy",
> +"tests/data/acpi/aarch64/virt/DSDT.topology",
> +"tests/data/acpi/aarch64/virt/DSDT.viot",
> +"tests/data/acpi/aarch64/virt/MCFG",
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions
2026-05-20 9:56 ` [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
@ 2026-05-20 13:51 ` Igor Mammedov
2026-05-21 4:43 ` Akihiko Odaki
0 siblings, 1 reply; 10+ messages in thread
From: Igor Mammedov @ 2026-05-20 13:51 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Ani Sinha, Fabiano Rosas, Laurent Vivier,
Paolo Bonzini
On Wed, 20 May 2026 18:56:32 +0900
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
> Remove the lower bound of the Highmem IO Regions' addresses for the
> latest machine version to increase the chance to fit the regions in the
> PA space.
>
> The lower bound was especially problematic when using virt-install on
> Apple M2. virt-install 5.0.0 adds multiple pcie-root-port devices that
it looks like with this patch everything would move down,
with 'small' but, VIRT_HIGH_PCIE_MMIO that still won't fit into M2 PA and
will get disabled.
Is it intended (perhaps it should be mentioned in patch)
> require sufficient space in the ECAM region. However, the Highmem ECAM
> region did not fit in the limited PA space on the hardware, and the ECAM
> region size was limited to 16 MiB. If virt-install had added more than
> 16 devices to the root bridge, the region overflowed, which prevented
> edk2-stable202505 from scanning PCI devices, including the boot disk,
> causing boot failures.
>
> Ideally, a virtual machine with more than 16 devices added to the root
> bridge should just work so that users and management layers do not have
> to care whether they use constrained hardware.
>
> The base address of the Highmem IO Regions was fixed when commit
> f90747c4e8fb ("hw/arm/virt: GICv3 DT node with one or two redistributor
> regions") added the first Highmem IO Region. Later, commit 957e32cffa57
> ("hw/arm/virt: Dynamic memory map depending on RAM requirements")
> allowed moving the Highmem IO Regions to higher addresses to accommodate
> RAM more than 255 GiB, but the lower bound remained to keep the legacy
> memory map.
>
> Remove the lower bound for the latest machine version to accommodate
> more devices with the root bridge. Keeping the lower bound for the old
> machine versions ensures the compatibility is still maintained.
>
> The hardcoded memory map in tests/qtest/libqos/generic-pcihost.c is also
> updated.
>
> Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> ---
> include/hw/arm/virt.h | 1 +
> hw/arm/virt.c | 17 +++++++++++------
> tests/qtest/libqos/generic-pcihost.c | 2 +-
> 3 files changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> index 3ba33b4bd274..6c8ba8f3185b 100644
> --- a/include/hw/arm/virt.h
> +++ b/include/hw/arm/virt.h
> @@ -142,6 +142,7 @@ typedef enum VirtGICType {
>
> struct VirtMachineClass {
> MachineClass parent;
> + hwaddr min_highmem_base;
> bool no_tcg_its;
> bool no_highmem_compact;
> bool no_kvm_steal_time;
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index b090233893c5..78a85a966ad7 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -229,8 +229,7 @@ static const MemMapEntry base_memmap[] = {
> * Highmem IO Regions: This memory map is floating, located after the RAM.
> * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
> * top of the RAM, so that its base get the same alignment as the size,
> - * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
> - * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
> + * ie. a 512GiB entry will be aligned on a 512GiB boundary.
> * Note the extended_memmap is sized so that it eventually also includes the
> * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
> * index of base_memmap).
> @@ -2479,6 +2478,7 @@ static void virt_set_high_memmap(VirtMachineState *vms,
> static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
> {
> MachineState *ms = MACHINE(vms);
> + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
> hwaddr base, device_memory_base, device_memory_size, memtop;
> int i;
>
> @@ -2505,8 +2505,7 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
> /*
> * We compute the base of the high IO region depending on the
> * amount of initial and device memory. The device memory start/size
> - * is aligned on 1GiB. We never put the high IO region below 256GiB
> - * so that if maxram_size is < 255GiB we keep the legacy memory map.
> + * is aligned on 1GiB.
> * The device region size assumes 1GiB page max alignment per slot.
> */
> device_memory_base =
> @@ -2524,8 +2523,8 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
> error_report("maxmem/slots too huge");
> exit(EXIT_FAILURE);
> }
> - if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
> - base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
> + if (base < vmc->min_highmem_base) {
> + base = vmc->min_highmem_base;
> }
>
> /* We know for sure that at least the memory fits in the PA space */
> @@ -4367,6 +4366,12 @@ static void virt_machine_11_0_options(MachineClass *mc)
> virt_machine_11_1_options(mc);
> compat_props_add(mc->compat_props, hw_compat_11_0, hw_compat_11_0_len);
> vmc->hvf_no_kernel_irqchip_default = true;
> +
> + /*
> + * Do not put the high IO region below 256GiB so that if maxram_size is
> + * < 255GiB we keep the legacy memory map.
> + */
> + vmc->min_highmem_base = base_memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
> }
> DEFINE_VIRT_MACHINE(11, 0)
>
> diff --git a/tests/qtest/libqos/generic-pcihost.c b/tests/qtest/libqos/generic-pcihost.c
> index b77617524cac..287e8445ec5b 100644
> --- a/tests/qtest/libqos/generic-pcihost.c
> +++ b/tests/qtest/libqos/generic-pcihost.c
> @@ -210,7 +210,7 @@ void qpci_init_generic(QGenericPCIBus *qpci, QTestState *qts,
> qpci->bus.pio_limit = 0x10000;
> qpci->bus.mmio_alloc_ptr = 0x10000000;
> qpci->bus.mmio_limit = 0x2eff0000;
> - qpci->ecam_alloc_ptr = 0x4010000000;
> + qpci->ecam_alloc_ptr = 0x90000000;
>
> qpci->obj.get_driver = qpci_generic_get_driver;
> }
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions
2026-05-20 13:51 ` Igor Mammedov
@ 2026-05-21 4:43 ` Akihiko Odaki
2026-05-21 12:14 ` Igor Mammedov
0 siblings, 1 reply; 10+ messages in thread
From: Akihiko Odaki @ 2026-05-21 4:43 UTC (permalink / raw)
To: Igor Mammedov
Cc: qemu-devel, Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Ani Sinha, Fabiano Rosas, Laurent Vivier,
Paolo Bonzini
On 2026/05/20 22:51, Igor Mammedov wrote:
> On Wed, 20 May 2026 18:56:32 +0900
> Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
>
>> Remove the lower bound of the Highmem IO Regions' addresses for the
>> latest machine version to increase the chance to fit the regions in the
>> PA space.
>>
>> The lower bound was especially problematic when using virt-install on
>> Apple M2. virt-install 5.0.0 adds multiple pcie-root-port devices that
>
> it looks like with this patch everything would move down,
> with 'small' but, VIRT_HIGH_PCIE_MMIO that still won't fit into M2 PA and
> will get disabled.
> Is it intended (perhaps it should be mentioned in patch)
Yes. It is another opportunity for improvement, but out of scopoe of
this patch.
>
>
>> require sufficient space in the ECAM region. However, the Highmem ECAM
>> region did not fit in the limited PA space on the hardware, and the ECAM
>> region size was limited to 16 MiB. If virt-install had added more than
>> 16 devices to the root bridge, the region overflowed, which prevented
>> edk2-stable202505 from scanning PCI devices, including the boot disk,
>> causing boot failures.
>>
>> Ideally, a virtual machine with more than 16 devices added to the root
>> bridge should just work so that users and management layers do not have
>> to care whether they use constrained hardware.
>>
>> The base address of the Highmem IO Regions was fixed when commit
>> f90747c4e8fb ("hw/arm/virt: GICv3 DT node with one or two redistributor
>> regions") added the first Highmem IO Region. Later, commit 957e32cffa57
>> ("hw/arm/virt: Dynamic memory map depending on RAM requirements")
>> allowed moving the Highmem IO Regions to higher addresses to accommodate
>> RAM more than 255 GiB, but the lower bound remained to keep the legacy
>> memory map.
>>
>> Remove the lower bound for the latest machine version to accommodate
>> more devices with the root bridge. Keeping the lower bound for the old
>> machine versions ensures the compatibility is still maintained.
>>
>> The hardcoded memory map in tests/qtest/libqos/generic-pcihost.c is also
>> updated.
>>
>> Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
>> Reviewed-by: Eric Auger <eric.auger@redhat.com>
>> ---
>> include/hw/arm/virt.h | 1 +
>> hw/arm/virt.c | 17 +++++++++++------
>> tests/qtest/libqos/generic-pcihost.c | 2 +-
>> 3 files changed, 13 insertions(+), 7 deletions(-)
>>
>> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
>> index 3ba33b4bd274..6c8ba8f3185b 100644
>> --- a/include/hw/arm/virt.h
>> +++ b/include/hw/arm/virt.h
>> @@ -142,6 +142,7 @@ typedef enum VirtGICType {
>>
>> struct VirtMachineClass {
>> MachineClass parent;
>> + hwaddr min_highmem_base;
>> bool no_tcg_its;
>> bool no_highmem_compact;
>> bool no_kvm_steal_time;
>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> index b090233893c5..78a85a966ad7 100644
>> --- a/hw/arm/virt.c
>> +++ b/hw/arm/virt.c
>> @@ -229,8 +229,7 @@ static const MemMapEntry base_memmap[] = {
>> * Highmem IO Regions: This memory map is floating, located after the RAM.
>> * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
>> * top of the RAM, so that its base get the same alignment as the size,
>> - * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
>> - * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
>> + * ie. a 512GiB entry will be aligned on a 512GiB boundary.
>> * Note the extended_memmap is sized so that it eventually also includes the
>> * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
>> * index of base_memmap).
>> @@ -2479,6 +2478,7 @@ static void virt_set_high_memmap(VirtMachineState *vms,
>> static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
>> {
>> MachineState *ms = MACHINE(vms);
>> + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
>> hwaddr base, device_memory_base, device_memory_size, memtop;
>> int i;
>>
>> @@ -2505,8 +2505,7 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
>> /*
>> * We compute the base of the high IO region depending on the
>> * amount of initial and device memory. The device memory start/size
>> - * is aligned on 1GiB. We never put the high IO region below 256GiB
>> - * so that if maxram_size is < 255GiB we keep the legacy memory map.
>> + * is aligned on 1GiB.
>> * The device region size assumes 1GiB page max alignment per slot.
>> */
>> device_memory_base =
>> @@ -2524,8 +2523,8 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
>> error_report("maxmem/slots too huge");
>> exit(EXIT_FAILURE);
>> }
>> - if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
>> - base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
>> + if (base < vmc->min_highmem_base) {
>> + base = vmc->min_highmem_base;
>> }
>>
>> /* We know for sure that at least the memory fits in the PA space */
>> @@ -4367,6 +4366,12 @@ static void virt_machine_11_0_options(MachineClass *mc)
>> virt_machine_11_1_options(mc);
>> compat_props_add(mc->compat_props, hw_compat_11_0, hw_compat_11_0_len);
>> vmc->hvf_no_kernel_irqchip_default = true;
>> +
>> + /*
>> + * Do not put the high IO region below 256GiB so that if maxram_size is
>> + * < 255GiB we keep the legacy memory map.
>> + */
>> + vmc->min_highmem_base = base_memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
>> }
>> DEFINE_VIRT_MACHINE(11, 0)
>>
>> diff --git a/tests/qtest/libqos/generic-pcihost.c b/tests/qtest/libqos/generic-pcihost.c
>> index b77617524cac..287e8445ec5b 100644
>> --- a/tests/qtest/libqos/generic-pcihost.c
>> +++ b/tests/qtest/libqos/generic-pcihost.c
>> @@ -210,7 +210,7 @@ void qpci_init_generic(QGenericPCIBus *qpci, QTestState *qts,
>> qpci->bus.pio_limit = 0x10000;
>> qpci->bus.mmio_alloc_ptr = 0x10000000;
>> qpci->bus.mmio_limit = 0x2eff0000;
>> - qpci->ecam_alloc_ptr = 0x4010000000;
>> + qpci->ecam_alloc_ptr = 0x90000000;
>>
>> qpci->obj.get_driver = qpci_generic_get_driver;
>> }
>>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions
2026-05-21 4:43 ` Akihiko Odaki
@ 2026-05-21 12:14 ` Igor Mammedov
0 siblings, 0 replies; 10+ messages in thread
From: Igor Mammedov @ 2026-05-21 12:14 UTC (permalink / raw)
To: Akihiko Odaki
Cc: qemu-devel, Peter Maydell, qemu-arm, Eric Auger, Andrew Jones,
Michael S. Tsirkin, Ani Sinha, Fabiano Rosas, Laurent Vivier,
Paolo Bonzini
On Thu, 21 May 2026 13:43:18 +0900
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
> On 2026/05/20 22:51, Igor Mammedov wrote:
> > On Wed, 20 May 2026 18:56:32 +0900
> > Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
> >
> >> Remove the lower bound of the Highmem IO Regions' addresses for the
> >> latest machine version to increase the chance to fit the regions in the
> >> PA space.
> >>
> >> The lower bound was especially problematic when using virt-install on
> >> Apple M2. virt-install 5.0.0 adds multiple pcie-root-port devices that
> >
> > it looks like with this patch everything would move down,
> > with 'small' but, VIRT_HIGH_PCIE_MMIO that still won't fit into M2 PA and
> > will get disabled.
> > Is it intended (perhaps it should be mentioned in patch)
>
> Yes. It is another opportunity for improvement, but out of scopoe of
> this patch.
in this case, I'd just mentionin commit message that this region is not not available,
for particular configuration with implications that stem from this,
as it's not obvious from the patch itself.
other than that LGTM
>
> >
> >
> >> require sufficient space in the ECAM region. However, the Highmem ECAM
> >> region did not fit in the limited PA space on the hardware, and the ECAM
> >> region size was limited to 16 MiB. If virt-install had added more than
> >> 16 devices to the root bridge, the region overflowed, which prevented
> >> edk2-stable202505 from scanning PCI devices, including the boot disk,
> >> causing boot failures.
> >>
> >> Ideally, a virtual machine with more than 16 devices added to the root
> >> bridge should just work so that users and management layers do not have
> >> to care whether they use constrained hardware.
> >>
> >> The base address of the Highmem IO Regions was fixed when commit
> >> f90747c4e8fb ("hw/arm/virt: GICv3 DT node with one or two redistributor
> >> regions") added the first Highmem IO Region. Later, commit 957e32cffa57
> >> ("hw/arm/virt: Dynamic memory map depending on RAM requirements")
> >> allowed moving the Highmem IO Regions to higher addresses to accommodate
> >> RAM more than 255 GiB, but the lower bound remained to keep the legacy
> >> memory map.
> >>
> >> Remove the lower bound for the latest machine version to accommodate
> >> more devices with the root bridge. Keeping the lower bound for the old
> >> machine versions ensures the compatibility is still maintained.
> >>
> >> The hardcoded memory map in tests/qtest/libqos/generic-pcihost.c is also
> >> updated.
> >>
> >> Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
> >> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> >> ---
> >> include/hw/arm/virt.h | 1 +
> >> hw/arm/virt.c | 17 +++++++++++------
> >> tests/qtest/libqos/generic-pcihost.c | 2 +-
> >> 3 files changed, 13 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> >> index 3ba33b4bd274..6c8ba8f3185b 100644
> >> --- a/include/hw/arm/virt.h
> >> +++ b/include/hw/arm/virt.h
> >> @@ -142,6 +142,7 @@ typedef enum VirtGICType {
> >>
> >> struct VirtMachineClass {
> >> MachineClass parent;
> >> + hwaddr min_highmem_base;
> >> bool no_tcg_its;
> >> bool no_highmem_compact;
> >> bool no_kvm_steal_time;
> >> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> >> index b090233893c5..78a85a966ad7 100644
> >> --- a/hw/arm/virt.c
> >> +++ b/hw/arm/virt.c
> >> @@ -229,8 +229,7 @@ static const MemMapEntry base_memmap[] = {
> >> * Highmem IO Regions: This memory map is floating, located after the RAM.
> >> * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
> >> * top of the RAM, so that its base get the same alignment as the size,
> >> - * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
> >> - * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
> >> + * ie. a 512GiB entry will be aligned on a 512GiB boundary.
> >> * Note the extended_memmap is sized so that it eventually also includes the
> >> * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
> >> * index of base_memmap).
> >> @@ -2479,6 +2478,7 @@ static void virt_set_high_memmap(VirtMachineState *vms,
> >> static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
> >> {
> >> MachineState *ms = MACHINE(vms);
> >> + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
> >> hwaddr base, device_memory_base, device_memory_size, memtop;
> >> int i;
> >>
> >> @@ -2505,8 +2505,7 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
> >> /*
> >> * We compute the base of the high IO region depending on the
> >> * amount of initial and device memory. The device memory start/size
> >> - * is aligned on 1GiB. We never put the high IO region below 256GiB
> >> - * so that if maxram_size is < 255GiB we keep the legacy memory map.
> >> + * is aligned on 1GiB.
> >> * The device region size assumes 1GiB page max alignment per slot.
> >> */
> >> device_memory_base =
> >> @@ -2524,8 +2523,8 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
> >> error_report("maxmem/slots too huge");
> >> exit(EXIT_FAILURE);
> >> }
> >> - if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
> >> - base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
> >> + if (base < vmc->min_highmem_base) {
> >> + base = vmc->min_highmem_base;
> >> }
> >>
> >> /* We know for sure that at least the memory fits in the PA space */
> >> @@ -4367,6 +4366,12 @@ static void virt_machine_11_0_options(MachineClass *mc)
> >> virt_machine_11_1_options(mc);
> >> compat_props_add(mc->compat_props, hw_compat_11_0, hw_compat_11_0_len);
> >> vmc->hvf_no_kernel_irqchip_default = true;
> >> +
> >> + /*
> >> + * Do not put the high IO region below 256GiB so that if maxram_size is
> >> + * < 255GiB we keep the legacy memory map.
> >> + */
> >> + vmc->min_highmem_base = base_memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
> >> }
> >> DEFINE_VIRT_MACHINE(11, 0)
> >>
> >> diff --git a/tests/qtest/libqos/generic-pcihost.c b/tests/qtest/libqos/generic-pcihost.c
> >> index b77617524cac..287e8445ec5b 100644
> >> --- a/tests/qtest/libqos/generic-pcihost.c
> >> +++ b/tests/qtest/libqos/generic-pcihost.c
> >> @@ -210,7 +210,7 @@ void qpci_init_generic(QGenericPCIBus *qpci, QTestState *qts,
> >> qpci->bus.pio_limit = 0x10000;
> >> qpci->bus.mmio_alloc_ptr = 0x10000000;
> >> qpci->bus.mmio_limit = 0x2eff0000;
> >> - qpci->ecam_alloc_ptr = 0x4010000000;
> >> + qpci->ecam_alloc_ptr = 0x90000000;
> >>
> >> qpci->obj.get_driver = qpci_generic_get_driver;
> >> }
> >>
> >
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2026-05-21 12:14 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-20 9:56 [PATCH v6 0/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
2026-05-20 9:56 ` [PATCH v6 1/4] test/acpi: aarch64/virt: Test version 11.0 Akihiko Odaki
2026-05-20 13:07 ` Igor Mammedov
2026-05-20 9:56 ` [PATCH v6 2/4] test/acpi: aarch64/virt: Allow DSDT and MCFG changes Akihiko Odaki
2026-05-20 13:07 ` Igor Mammedov
2026-05-20 9:56 ` [PATCH v6 3/4] hw/arm/virt: Remove the lower bound of HighMem IO Regions Akihiko Odaki
2026-05-20 13:51 ` Igor Mammedov
2026-05-21 4:43 ` Akihiko Odaki
2026-05-21 12:14 ` Igor Mammedov
2026-05-20 9:56 ` [PATCH v6 4/4] test/acpi: aarch64/virt: Update golden masters for DSDT and MCFG Akihiko Odaki
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