From: sashiko-bot@kernel.org
To: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>
Cc: Frank.Li@kernel.org, dmaengine@vger.kernel.org, vkoul@kernel.org
Subject: Re: [PATCH v18 12/14] crypto: qce - Map crypto memory for DMA
Date: Fri, 22 May 2026 17:56:43 +0000 [thread overview]
Message-ID: <20260522175643.6022E1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260522-qcom-qce-cmd-descr-v18-12-99103926bafc@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but in the error path of `devm_qce_register_algs()`, the driver fails to properly unregister already registered algorithms and repeatedly unregisters the failed one.
--
commit 56e64a8a181facb8444e80e7d550153e25a41208
Author: Bartosz Golaszewski <brgl@kernel.org>
crypto: qce - Map crypto memory for DMA
As the first step in converting the driver to using DMA for register
I/O, let's map the crypto memory range.
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index a0e2eadc3afd5..d7b7a3dda4649 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
[ ... ]
> @@ -255,6 +264,18 @@ static int qce_crypto_probe(struct platform_device *pdev)
> qce->async_req_enqueue = qce_async_request_enqueue;
> qce->async_req_done = qce_async_request_done;
>
> + qce->dma_size = resource_size(res);
> + qce->base_dma = dma_map_resource(dev, res->start, qce->dma_size,
> + DMA_BIDIRECTIONAL, 0);
> + qce->base_phys = res->start;
> + ret = dma_mapping_error(dev, qce->base_dma);
> + if (ret)
> + return ret;
> +
> + ret = devm_add_action_or_reset(qce->dev, qce_crypto_unmap_dma, qce);
> + if (ret)
> + return ret;
> +
> return devm_qce_register_algs(qce);
> }
[Severity: High]
This isn't a bug introduced by this patch, but in the error path of
devm_qce_register_algs(), the driver fails to properly unregister already
registered algorithms and repeatedly unregisters the failed one.
Looking at devm_qce_register_algs() in drivers/crypto/qce/core.c:
for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
ops = qce_ops[i];
ret = ops->register_algs(qce);
if (ret) {
for (j = i - 1; j >= 0; j--)
ops->unregister_algs(qce);
return ret;
}
}
The rollback loop iterates backwards with j, but calls ops->unregister_algs()
where ops still points to the currently failed algorithm qce_ops[i].
Should it be calling qce_ops[j]->unregister_algs(qce) instead?
As a result, previously successfully registered algorithms are leaked, and the
driver repeatedly unregisters an algorithm that either failed to register or
was never successfully registered.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260522-qcom-qce-cmd-descr-v18-0-99103926bafc@oss.qualcomm.com?part=12
next prev parent reply other threads:[~2026-05-22 17:56 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-22 13:39 [PATCH v18 00/14] crypto/dmaengine: qce: introduce BAM locking and use DMA for register I/O Bartosz Golaszewski
2026-05-22 13:39 ` [PATCH v18 01/14] dmaengine: constify struct dma_descriptor_metadata_ops Bartosz Golaszewski
2026-05-22 13:39 ` [PATCH v18 02/14] dmaengine: qcom: bam_dma: free interrupt before the clock in error path Bartosz Golaszewski
2026-05-22 14:17 ` sashiko-bot
2026-05-22 13:39 ` [PATCH v18 03/14] dmaengine: qcom: bam_dma: convert tasklet to a BH workqueue Bartosz Golaszewski
2026-05-22 14:37 ` sashiko-bot
2026-05-22 13:39 ` [PATCH v18 04/14] dmaengine: qcom: bam_dma: Extend the driver's device match data Bartosz Golaszewski
2026-05-22 13:39 ` [PATCH v18 05/14] dmaengine: qcom: bam_dma: Add pipe_lock_supported flag support Bartosz Golaszewski
2026-05-22 13:39 ` [PATCH v18 06/14] dmaengine: qcom: bam_dma: add support for BAM locking Bartosz Golaszewski
2026-05-22 15:25 ` sashiko-bot
2026-05-22 13:40 ` [PATCH v18 07/14] crypto: qce - Cancel work on device detach Bartosz Golaszewski
2026-05-22 15:57 ` sashiko-bot
2026-05-22 13:40 ` [PATCH v18 08/14] crypto: qce - Include algapi.h in the core.h header Bartosz Golaszewski
2026-05-22 13:40 ` [PATCH v18 09/14] crypto: qce - Remove unused ignore_buf Bartosz Golaszewski
2026-05-22 16:44 ` sashiko-bot
2026-05-22 13:40 ` [PATCH v18 10/14] crypto: qce - Simplify arguments of devm_qce_dma_request() Bartosz Golaszewski
2026-05-22 13:40 ` [PATCH v18 11/14] crypto: qce - Use existing devres APIs in devm_qce_dma_request() Bartosz Golaszewski
2026-05-22 17:15 ` sashiko-bot
2026-05-22 13:40 ` [PATCH v18 12/14] crypto: qce - Map crypto memory for DMA Bartosz Golaszewski
2026-05-22 17:56 ` sashiko-bot [this message]
2026-05-22 13:40 ` [PATCH v18 13/14] crypto: qce - Add BAM DMA support for crypto register I/O Bartosz Golaszewski
2026-05-22 13:40 ` [PATCH v18 14/14] crypto: qce - Communicate the base physical address to the dmaengine Bartosz Golaszewski
2026-05-24 20:49 ` [PATCH v18 00/14] crypto/dmaengine: qce: introduce BAM locking and use DMA for register I/O Eric Biggers
2026-05-25 5:44 ` Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260522175643.6022E1F000E9@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=Frank.Li@kernel.org \
--cc=bartosz.golaszewski@oss.qualcomm.com \
--cc=dmaengine@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.