[linux-next:master 6035/8157] drivers/gpu/drm/amd/amdgpu/../display/dc/pg/dcn42/dcn42_pg_cntl.c:64 pg_cntl42_dsc_pg_control() warn: inconsistent indenting

[linux-next:master 6035/8157] drivers/gpu/drm/amd/amdgpu/../display/dc/pg/dcn42/dcn42_pg_cntl.c:64 pg_cntl42_dsc_pg_control() warn: inconsistent indenting

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   c1ecb239fa3456529a32255359fc78b69eb9d847
commit: 55e69772bd70fff0cb44d7686211137bb57ab7f3 [6035/8157] drm/amd/display: Allow power up when PG disallowed in driver
config: x86_64-randconfig-161-20260522 (https://download.01.org/0day-ci/archive/20260523/202605232000.Gf60VFNI-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
smatch: v0.5.0-9185-gbcc58b9c

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202605232000.Gf60VFNI-lkp@intel.com/

smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/pg/dcn42/dcn42_pg_cntl.c:64 pg_cntl42_dsc_pg_control() warn: inconsistent indenting

vim +64 drivers/gpu/drm/amd/amdgpu/../display/dc/pg/dcn42/dcn42_pg_cntl.c

    50	
    51	void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on)
    52	{
    53		struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
    54		uint32_t power_gate = power_on ? 0 : 1;
    55		uint32_t pwr_status = power_on ? 0 : 2;
    56		uint32_t org_ip_request_cntl = 0;
    57		bool block_enabled;
    58	
    59		/*need to enable dscclk regardless DSC_PG*/
    60		if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on)
    61			pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc(
    62					pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);
    63	
  > 64	    bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||
    65				pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||
    66				pg_cntl->ctx->dc->idle_optimizations_allowed;
    67	
    68		if (skip_pg && !power_on)
    69			return;
    70	
    71		block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, dsc_inst);
    72		if (power_on) {
    73			if (block_enabled)
    74				return;
    75		} else {
    76			if (!block_enabled)
    77				return;
    78		}
    79	
    80		REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
    81		if (org_ip_request_cntl == 0)
    82			REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
    83	
    84		if (power_on) {
    85			if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)
    86				pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);
    87		}
    88		switch (dsc_inst) {
    89		case 0: /* DSC0 */
    90			REG_UPDATE(DOMAIN16_PG_CONFIG,
    91					DOMAIN_POWER_GATE, power_gate);
    92	
    93			REG_WAIT(DOMAIN16_PG_STATUS,
    94					DOMAIN_PGFSM_PWR_STATUS, pwr_status,
    95					1, 1000);
    96			break;
    97		case 1: /* DSC1 */
    98			REG_UPDATE(DOMAIN17_PG_CONFIG,
    99					DOMAIN_POWER_GATE, power_gate);
   100	
   101			REG_WAIT(DOMAIN17_PG_STATUS,
   102					DOMAIN_PGFSM_PWR_STATUS, pwr_status,
   103					1, 1000);
   104			break;
   105		case 2: /* DSC2 */
   106			REG_UPDATE(DOMAIN18_PG_CONFIG,
   107					DOMAIN_POWER_GATE, power_gate);
   108	
   109			REG_WAIT(DOMAIN18_PG_STATUS,
   110					DOMAIN_PGFSM_PWR_STATUS, pwr_status,
   111					1, 1000);
   112			break;
   113		case 3: /* DSC3 */
   114			REG_UPDATE(DOMAIN19_PG_CONFIG,
   115					DOMAIN_POWER_GATE, power_gate);
   116	
   117			REG_WAIT(DOMAIN19_PG_STATUS,
   118					DOMAIN_PGFSM_PWR_STATUS, pwr_status,
   119					1, 1000);
   120			break;
   121		default:
   122			BREAK_TO_DEBUGGER();
   123			break;
   124		}
   125	
   126		if (power_on) {
   127			if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)
   128				pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);
   129		}
   130	
   131		if (dsc_inst < MAX_PIPES)
   132			pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on;
   133	
   134		if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) {
   135			/*this is to disable dscclk*/
   136			pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc(
   137				pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);
   138		}
   139	}
   140	

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https://github.com/intel/lkp-tests/wiki