From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Kane Chen" <kane_chen@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>
Subject: [PATCH v2 3/9] hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support
Date: Mon, 25 May 2026 05:30:42 +0000 [thread overview]
Message-ID: <20260525053036.3305181-4-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260525053036.3305181-1-jamin_lin@aspeedtech.com>
Some Aspeed SoCs contain multiple SRAM regions with different
MMIO mappings, such as internal SRAM and secure SRAM.
Prepare for future multi-SRAM support by renaming the SRAM
memmap entry from ASPEED_DEV_SRAM to ASPEED_DEV_SRAM0.
This makes the numbering explicit and aligns with the
array-based SRAM representation introduced previously.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_ast10x0.c | 4 ++--
hw/arm/aspeed_ast2400.c | 6 +++---
hw/arm/aspeed_ast2600.c | 4 ++--
hw/arm/aspeed_ast27x0-ssp.c | 4 ++--
hw/arm/aspeed_ast27x0-tsp.c | 4 ++--
hw/arm/aspeed_ast27x0.c | 4 ++--
7 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3a7db959a9..dda602e9f2 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -228,7 +228,7 @@ enum {
ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
- ASPEED_DEV_SRAM,
+ ASPEED_DEV_SRAM0,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 9e597a75ec..b55f788342 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -20,7 +20,7 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
static const hwaddr aspeed_soc_ast1030_memmap[] = {
- [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM0] = 0x00000000,
[ASPEED_DEV_SECSRAM] = 0x79000000,
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
@@ -247,7 +247,7 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
return false;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM],
+ sc->memmap[ASPEED_DEV_SRAM0],
&s->sram[0]);
memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
sc->secsram_size, &err);
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index c4e5388999..79a653f65f 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -38,7 +38,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SRAM0] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
@@ -75,7 +75,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SRAM0] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
@@ -286,7 +286,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 2f8f49a376..d1f18e471a 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -23,7 +23,7 @@
static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_SPI_BOOT] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_SRAM0] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x18000000,
/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
[ASPEED_DEV_IOMEM] = 0x1E600000,
@@ -442,7 +442,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* DPMCU */
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 8b84300e0f..b3c4eb1915 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -20,7 +20,7 @@
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x70000000,
+ [ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
@@ -182,7 +182,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index e7c7b74491..6098d1aae3 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -20,7 +20,7 @@
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x70000000,
+ [ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
@@ -182,7 +182,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 30883ea7ce..d7ce14e8c5 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -30,7 +30,7 @@
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_VBOOTROM] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x00020000,
- [ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_SRAM0] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x11000000,
[ASPEED_DEV_IOMEM0] = 0x12000000,
[ASPEED_DEV_EHCI1] = 0x12061000,
@@ -783,7 +783,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* VBOOTROM */
if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
--
2.43.0
next prev parent reply other threads:[~2026-05-25 5:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
2026-05-25 5:30 ` [PATCH v2 1/9] hw/arm/aspeed: Convert SRAM MemoryRegion to array type Jamin Lin
2026-05-25 5:30 ` [PATCH v2 2/9] hw/arm/aspeed: Convert SRAM size definition " Jamin Lin
2026-05-25 5:30 ` Jamin Lin [this message]
2026-05-25 5:30 ` [PATCH v2 4/9] hw/arm/aspeed: Consolidate secure SRAM into SRAM array Jamin Lin
2026-05-25 5:30 ` [PATCH v2 5/9] hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID Jamin Lin
2026-05-25 5:30 ` [PATCH v2 6/9] hw/arm/aspeed: Introduce AST1040 A0 SoC model Jamin Lin
2026-05-25 5:30 ` [PATCH v2 7/9] hw/arm/aspeed: Add AST1040 EVB machine model Jamin Lin
2026-05-25 5:30 ` [PATCH v2 8/9] tests/function/aspeed: Add AST1040 functional test Jamin Lin
2026-05-25 5:30 ` [PATCH v2 9/9] docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board Jamin Lin
2026-05-26 4:58 ` [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Cédric Le Goater
2026-05-26 5:02 ` Cédric Le Goater
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