From: Ewan Hai <ewandevelop@gmail.com>
To: seanjc@google.com, pbonzini@redhat.com, tglx@kernel.org,
mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
x86@kernel.org, hpa@zytor.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: binbin.wu@linux.intel.com, ewanhai@zhaoxin.com,
cobechen@zhaoxin.com, tonywwang@zhaoxin.com
Subject: [PATCH v2 4/5] KVM: x86: Expose Zhaoxin PHE2 CPUID feature
Date: Thu, 28 May 2026 11:22:33 +0800 [thread overview]
Message-ID: <20260528032234.1322565-5-ewandevelop@gmail.com> (raw)
In-Reply-To: <20260528032234.1322565-1-ewandevelop@gmail.com>
Advertise the Zhaoxin PadLock Hash Engine v2 to guests via CPUID
0xC0000001 EDX bits 25 (PHE2) and 26 (PHE2_EN). PHE2 extends the
PadLock hash family with SHA-384 and SHA-512 support per FIPS 180-3,
complementing the existing PHE feature (SHA-1 and SHA-256).
Two user-mode instructions are exposed, documented in the Zhaoxin
PadLock Instruction Reference, chapter 3 ("Hash Engine"):
- REP XSHA384 (encoding F3 0F A6 D8, subsection 3.3)
- REP XSHA512 (encoding F3 0F A6 E0, subsection 3.4)
Both consume software-padded 128-byte blocks (RCX = block count, RSI =
input, RDI = state) and produce hash output in the state buffer.
Both instructions are unprivileged (no CPL restriction) and available
in all CPU modes, with no associated MSR control. The PHE2 and PHE2_EN
bits are redundant by hardware design (set or cleared together) and
both serve purely as CPUID-level feature-presence reporting flags
requiring no KVM emulation. Both bits are advertised because different
software may probe either one when checking for PHE2 availability.
Signed-off-by: Ewan Hai <ewandevelop@gmail.com>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kvm/cpuid.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index e264758d58e2..3702d7a30ae6 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -152,6 +152,8 @@
#define X86_FEATURE_PMM_EN ( 5*32+13) /* "pmm_en" PMM enabled */
#define X86_FEATURE_RNG2 ( 5*32+22) /* "rng2" RNG v2 */
#define X86_FEATURE_RNG2_EN ( 5*32+23) /* "rng2_en" RNG2 enabled */
+#define X86_FEATURE_PHE2 ( 5*32+25) /* "phe2" PadLock Hash Engine v2 */
+#define X86_FEATURE_PHE2_EN ( 5*32+26) /* "phe2_en" PHE2 enabled */
/* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* "lahf_lm" LAHF/SAHF in long mode */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 087c41341240..3fb81f7a6107 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1288,6 +1288,8 @@ void kvm_initialize_cpu_caps(void)
F(PMM_EN),
F(RNG2),
F(RNG2_EN),
+ F(PHE2),
+ F(PHE2_EN),
);
/*
--
2.34.1
next prev parent reply other threads:[~2026-05-28 3:22 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 3:22 [PATCH v2 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai
2026-05-28 3:22 ` [PATCH v2 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature Ewan Hai
2026-05-28 3:42 ` sashiko-bot
2026-05-28 7:09 ` Ewan Hai
2026-05-28 12:49 ` Sean Christopherson
2026-05-28 13:35 ` Ewan Hai
2026-05-28 3:22 ` [PATCH v2 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) " Ewan Hai
2026-06-02 7:30 ` Binbin Wu
2026-06-02 7:49 ` Ewan Hai
2026-05-28 3:22 ` [PATCH v2 3/5] KVM: x86: Expose Zhaoxin RNG2 " Ewan Hai
2026-05-28 3:22 ` Ewan Hai [this message]
2026-06-02 7:29 ` [PATCH v2 4/5] KVM: x86: Expose Zhaoxin PHE2 " Binbin Wu
2026-05-28 3:22 ` [PATCH v2 5/5] KVM: x86: Expose Zhaoxin RSA " Ewan Hai
2026-05-28 5:03 ` sashiko-bot
2026-05-28 7:14 ` Ewan Hai
2026-06-02 7:32 ` [PATCH v2 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Binbin Wu
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