From: Jakub Kicinski <kuba@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: ivecera@redhat.com, vadim.fedorenko@linux.dev, jiri@resnulli.us,
edumazet@google.com, netdev@vger.kernel.org,
richardcochran@gmail.com, donald.hunter@gmail.com,
linux-kernel@vger.kernel.org, arkadiusz.kubalewski@intel.com,
Prathosh.Satish@microchip.com, andrew+netdev@lunn.ch,
intel-wired-lan@lists.osuosl.org, horms@kernel.org,
przemyslaw.kitszel@intel.com, anthony.l.nguyen@intel.com,
pabeni@redhat.com, davem@davemloft.net
Subject: Re: [Intel-wired-lan] [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825
Date: Wed, 3 Jun 2026 18:30:36 -0700 [thread overview]
Message-ID: <20260603183036.7c4762d2@kernel.org> (raw)
In-Reply-To: <20260529142628.1678955-1-grzegorz.nitka@intel.com>
On Fri, 29 May 2026 16:26:20 +0200 Grzegorz Nitka wrote:
> NOTE: This series is intentionally submitted on net-next (not
> intel-wired-lan) as early feedback of DPLL subsystem changes is
> welcomed. In the past possible approaches were discussed in [1].
I dug into 3 of the issues reported by Claude here and I think all
are really preexisting. But I don't see why we wouldn't fix those
first, and have a clean AI scan. Please send the fixes ASAP if you
have them, if they are trivial they may make it for tomorrow's PR.
--
pw-bot: cr
WARNING: multiple messages have this Message-ID (diff)
From: Jakub Kicinski <kuba@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
intel-wired-lan@lists.osuosl.org, poros@redhat.com,
richardcochran@gmail.com, andrew+netdev@lunn.ch,
przemyslaw.kitszel@intel.com, anthony.l.nguyen@intel.com,
Prathosh.Satish@microchip.com, ivecera@redhat.com,
jiri@resnulli.us, arkadiusz.kubalewski@intel.com,
vadim.fedorenko@linux.dev, donald.hunter@gmail.com,
horms@kernel.org, pabeni@redhat.com, davem@davemloft.net,
edumazet@google.com
Subject: Re: [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825
Date: Wed, 3 Jun 2026 18:30:36 -0700 [thread overview]
Message-ID: <20260603183036.7c4762d2@kernel.org> (raw)
In-Reply-To: <20260529142628.1678955-1-grzegorz.nitka@intel.com>
On Fri, 29 May 2026 16:26:20 +0200 Grzegorz Nitka wrote:
> NOTE: This series is intentionally submitted on net-next (not
> intel-wired-lan) as early feedback of DPLL subsystem changes is
> welcomed. In the past possible approaches were discussed in [1].
I dug into 3 of the issues reported by Claude here and I think all
are really preexisting. But I don't see why we wouldn't fix those
first, and have a clean AI scan. Please send the fixes ASAP if you
have them, if they are trivial they may make it for tomorrow's PR.
--
pw-bot: cr
next prev parent reply other threads:[~2026-06-04 1:30 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 14:26 [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 1/8] dpll: add generic DPLL type Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 3/8] dpll: extend pin notifier with notification source ID Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 4/8] dpll: allow fwnode pins to attempt state change without capability bit Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-05-29 14:26 ` [PATCH v12 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
2026-05-29 14:26 ` [Intel-wired-lan] " Grzegorz Nitka
2026-06-04 1:30 ` Jakub Kicinski [this message]
2026-06-04 1:30 ` [PATCH v12 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Jakub Kicinski
2026-06-04 20:05 ` [Intel-wired-lan] " Nitka, Grzegorz
2026-06-04 20:05 ` Nitka, Grzegorz
2026-06-04 22:54 ` Jakub Kicinski
2026-06-04 22:54 ` [Intel-wired-lan] " Jakub Kicinski
2026-06-05 16:10 ` Nitka, Grzegorz
2026-06-05 16:10 ` [Intel-wired-lan] " Nitka, Grzegorz
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