* [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support
@ 2026-06-10 8:08 Yu-Chun Lin
2026-06-10 8:08 ` [PATCH v8 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin
` (9 more replies)
0 siblings, 10 replies; 15+ messages in thread
From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12,
afaerber, jyanchou
Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel,
linux-realtek-soc, james.tai, cy.huang, stanley_chang,
eleanor.lin
Hello,
This patch series adds clock support for Realtek's RTD1625 platform.
The series includes:
1. Device Tree: Add clock controller nodes.
2. Infrastructure: reset controller, basic clocks, PLLs, gate clocks, mux
clocks, and MMC-tuned PLLs.
3. Platform drivers: two clock controller drivers for RTD1625-CRT and
RTD1625-ISO.
Best regards,
Yu-Chun Lin
---
Changes in v8:
Patch 3:
- Add depends on RESET_CONTROLLER and select MFD_SYSCON for config
RTK_CLK_COMMON
- Fix error handling for devm_auxiliary_device_create()
Patch 4:
- Reduce the timeout value in regmap_read_poll_timeout_atomic() from 2000ms to
500ms to avoid prolonged busy-waiting and prevent triggering the NMI Watchdog
- Remove 'freq_ready_valid' and add comments to clarify that register offset 0
is never a valid address on Realtek SoCs, meaning it is not configured
- Add the missing spin_unlock_irqrestore() when regmap_read() fails
Patch 6:
- In clk_regmap_mux_get_parent(), return 0xff instead of 0 to properly indicate
an error
- In clk_regmap_mux_set_parent(), cast index to u32 to avoid signed integer
- overflow
Patch 7:
- Fix the mask shift in set_phrt0()
- For better safety and readability, modify pointer comparison for phase_id
- In clk_pll_mmc_recalc_rate(), return 0 instead of an error code upon failure
Patch 8 & 9:
- Remove the trailing NULL element ([RTD1625_XX_CLK_MAX] = NULL) from the
clk_hw_onecell_data arrays
- Add MODULE_DEVICE_TABLE(of, ...) for the tristate config
- Add '.suppress_bind_attrs = true', to avoid handling pointer problem, cause
clock should not allow to manually disable by users
- Fix a typo
Patch 10:
- Sort device nodes by unit address
v7: https://lore.kernel.org/lkml/20260508111641.3192177-1-eleanor.lin@realtek.com/
Cheng-Yu Lee (8):
reset: Add Realtek basic reset support
clk: realtek: Introduce a common probe()
clk: realtek: Add support for phase locked loops (PLLs)
clk: realtek: Add support for gate clock
clk: realtek: Add support for mux clock
clk: realtek: Add support for MMC-tuned PLL clocks
clk: realtek: Add RTD1625-CRT clock controller driver
clk: realtek: Add RTD1625-ISO clock controller driver
Yu-Chun Lin (2):
dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller
arm64: dts: realtek: Add clock support for RTD1625
.../bindings/clock/realtek,rtd1625-clk.yaml | 58 ++
MAINTAINERS | 20 +
arch/arm64/boot/dts/realtek/kent.dtsi | 33 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/realtek/Kconfig | 48 ++
drivers/clk/realtek/Makefile | 13 +
drivers/clk/realtek/clk-pll-mmc.c | 459 ++++++++++
drivers/clk/realtek/clk-pll.c | 209 +++++
drivers/clk/realtek/clk-pll.h | 60 ++
drivers/clk/realtek/clk-regmap-gate.c | 70 ++
drivers/clk/realtek/clk-regmap-gate.h | 65 ++
drivers/clk/realtek/clk-regmap-mux.c | 41 +
drivers/clk/realtek/clk-regmap-mux.h | 43 +
drivers/clk/realtek/clk-rtd1625-crt.c | 792 ++++++++++++++++++
drivers/clk/realtek/clk-rtd1625-iso.c | 151 ++++
drivers/clk/realtek/common.c | 66 ++
drivers/clk/realtek/common.h | 37 +
drivers/clk/realtek/freq_table.c | 38 +
drivers/clk/realtek/freq_table.h | 16 +
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/realtek/Kconfig | 19 +
drivers/reset/realtek/Makefile | 3 +
drivers/reset/realtek/common.c | 90 ++
drivers/reset/realtek/common.h | 29 +
drivers/reset/realtek/reset-rtd1625-crt.c | 187 +++++
drivers/reset/realtek/reset-rtd1625-iso.c | 99 +++
.../dt-bindings/clock/realtek,rtd1625-clk.h | 164 ++++
include/dt-bindings/reset/realtek,rtd1625.h | 171 ++++
30 files changed, 2985 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml
create mode 100644 drivers/clk/realtek/Kconfig
create mode 100644 drivers/clk/realtek/Makefile
create mode 100644 drivers/clk/realtek/clk-pll-mmc.c
create mode 100644 drivers/clk/realtek/clk-pll.c
create mode 100644 drivers/clk/realtek/clk-pll.h
create mode 100644 drivers/clk/realtek/clk-regmap-gate.c
create mode 100644 drivers/clk/realtek/clk-regmap-gate.h
create mode 100644 drivers/clk/realtek/clk-regmap-mux.c
create mode 100644 drivers/clk/realtek/clk-regmap-mux.h
create mode 100644 drivers/clk/realtek/clk-rtd1625-crt.c
create mode 100644 drivers/clk/realtek/clk-rtd1625-iso.c
create mode 100644 drivers/clk/realtek/common.c
create mode 100644 drivers/clk/realtek/common.h
create mode 100644 drivers/clk/realtek/freq_table.c
create mode 100644 drivers/clk/realtek/freq_table.h
create mode 100644 drivers/reset/realtek/Kconfig
create mode 100644 drivers/reset/realtek/Makefile
create mode 100644 drivers/reset/realtek/common.c
create mode 100644 drivers/reset/realtek/common.h
create mode 100644 drivers/reset/realtek/reset-rtd1625-crt.c
create mode 100644 drivers/reset/realtek/reset-rtd1625-iso.c
create mode 100644 include/dt-bindings/clock/realtek,rtd1625-clk.h
create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h
--
2.43.0
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v8 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 02/10] reset: Add Realtek basic reset support Yu-Chun Lin ` (8 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin, Krzysztof Kozlowski Add DT binding schema for Realtek RTD1625 clock and reset controller Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Co-developed-by: Cheng-Yu Lee <cylee12@realtek.com> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - None --- .../bindings/clock/realtek,rtd1625-clk.yaml | 58 ++++++ MAINTAINERS | 10 + .../dt-bindings/clock/realtek,rtd1625-clk.h | 164 +++++++++++++++++ include/dt-bindings/reset/realtek,rtd1625.h | 171 ++++++++++++++++++ 4 files changed, 403 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml create mode 100644 include/dt-bindings/clock/realtek,rtd1625-clk.h create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h diff --git a/Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml b/Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml new file mode 100644 index 000000000000..1aceef31e148 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/realtek,rtd1625-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTD1625 Clock & Reset Controller + +maintainers: + - Cheng-Yu Lee <cylee12@realtek.com> + - Yu-Chun Lin <eleanor.lin@realtek.com> + +description: | + The Realtek RTD1625 Clock Controller manages and distributes clock + signals to various controllers and implements a Reset Controller for the + SoC peripherals. + + Clocks and resets are referenced by unique identifiers, which are defined as + preprocessor macros in include/dt-bindings/clock/realtek,rtd1625-clk.h and + include/dt-bindings/reset/realtek,rtd1625.h. + +properties: + compatible: + enum: + - realtek,rtd1625-crt-clk + - realtek,rtd1625-iso-clk + - realtek,rtd1625-iso-s-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@98000000 { + compatible = "realtek,rtd1625-crt-clk"; + reg = <0x98000000 0x1000>; + clocks = <&osc27m>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 355e4ab2f9e5..613ca7e95e47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22477,6 +22477,16 @@ S: Maintained F: Documentation/devicetree/bindings/net/dsa/realtek.yaml F: drivers/net/dsa/realtek/* +REALTEK SOC CLOCK AND RESET DRIVERS +M: Cheng-Yu Lee <cylee12@realtek.com> +M: Yu-Chun Lin <eleanor.lin@realtek.com> +L: devicetree@vger.kernel.org +L: linux-clk@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/clock/realtek* +F: include/dt-bindings/clock/realtek* +F: include/dt-bindings/reset/realtek* + REALTEK SPI-NAND M: Chris Packham <chris.packham@alliedtelesis.co.nz> S: Maintained diff --git a/include/dt-bindings/clock/realtek,rtd1625-clk.h b/include/dt-bindings/clock/realtek,rtd1625-clk.h new file mode 100644 index 000000000000..61ca652d6880 --- /dev/null +++ b/include/dt-bindings/clock/realtek,rtd1625-clk.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Realtek Semiconductor Corp. + */ +#ifndef __DT_BINDINGS_RTK_CLOCK_RTD1625_H +#define __DT_BINDINGS_RTK_CLOCK_RTD1625_H + +#define RTD1625_CRT_CLK_EN_MISC 0 +#define RTD1625_CRT_CLK_EN_PCIE0 1 +#define RTD1625_CRT_CLK_EN_DIP 2 +#define RTD1625_CRT_CLK_EN_GSPI 3 +#define RTD1625_CRT_CLK_EN_ISO_MISC 5 +#define RTD1625_CRT_CLK_EN_SDS 6 +#define RTD1625_CRT_CLK_EN_HDMI 7 +#define RTD1625_CRT_CLK_EN_GPU 9 +#define RTD1625_CRT_CLK_EN_VE1 10 +#define RTD1625_CRT_CLK_EN_VE2 11 +#define RTD1625_CRT_CLK_EN_MD 18 +#define RTD1625_CRT_CLK_EN_TP 19 +#define RTD1625_CRT_CLK_EN_RCIC 20 +#define RTD1625_CRT_CLK_EN_NF 21 +#define RTD1625_CRT_CLK_EN_EMMC 22 +#define RTD1625_CRT_CLK_EN_SD 23 +#define RTD1625_CRT_CLK_EN_SDIO_IP 24 +#define RTD1625_CRT_CLK_EN_MIPI_CSI 25 +#define RTD1625_CRT_CLK_EN_EMMC_IP 26 +#define RTD1625_CRT_CLK_EN_SDIO 27 +#define RTD1625_CRT_CLK_EN_SD_IP 28 +#define RTD1625_CRT_CLK_EN_TPB 30 +#define RTD1625_CRT_CLK_EN_MISC_SC1 31 +#define RTD1625_CRT_CLK_EN_MISC_I2C_3 32 +#define RTD1625_CRT_CLK_EN_ACPU 33 +#define RTD1625_CRT_CLK_EN_JPEG 34 +#define RTD1625_CRT_CLK_EN_MISC_SC0 37 +#define RTD1625_CRT_CLK_EN_HDMIRX 45 +#define RTD1625_CRT_CLK_EN_HSE 46 +#define RTD1625_CRT_CLK_EN_FAN 49 +#define RTD1625_CRT_CLK_EN_SATA_WRAP_SYS 52 +#define RTD1625_CRT_CLK_EN_SATA_WRAP_SYSH 53 +#define RTD1625_CRT_CLK_EN_SATA_MAC_SYSH 54 +#define RTD1625_CRT_CLK_EN_R2RDSC 55 +#define RTD1625_CRT_CLK_EN_TPC 56 +#define RTD1625_CRT_CLK_EN_PCIE1 57 +#define RTD1625_CRT_CLK_EN_MISC_I2C_4 58 +#define RTD1625_CRT_CLK_EN_MISC_I2C_5 59 +#define RTD1625_CRT_CLK_EN_TSIO 60 +#define RTD1625_CRT_CLK_EN_VE4 61 +#define RTD1625_CRT_CLK_EN_EDP 62 +#define RTD1625_CRT_CLK_EN_TSIO_TRX 63 +#define RTD1625_CRT_CLK_EN_PCIE2 64 +#define RTD1625_CRT_CLK_EN_EARC 66 +#define RTD1625_CRT_CLK_EN_LITE 67 +#define RTD1625_CRT_CLK_EN_MIPI_DSI 68 +#define RTD1625_CRT_CLK_EN_NPUPP 69 +#define RTD1625_CRT_CLK_EN_NPU 70 +#define RTD1625_CRT_CLK_EN_AUCPU0 71 +#define RTD1625_CRT_CLK_EN_AUCPU1 72 +#define RTD1625_CRT_CLK_EN_NSRAM 73 +#define RTD1625_CRT_CLK_EN_HDMITOP 74 +#define RTD1625_CRT_CLK_EN_AUCPU_ISO_NPU 76 +#define RTD1625_CRT_CLK_EN_KEYLADDER 77 +#define RTD1625_CRT_CLK_EN_IFCP_KLM 78 +#define RTD1625_CRT_CLK_EN_IFCP 79 +#define RTD1625_CRT_CLK_EN_MDL_GENPW 80 +#define RTD1625_CRT_CLK_EN_MDL_CHIP 81 +#define RTD1625_CRT_CLK_EN_MDL_IP 82 +#define RTD1625_CRT_CLK_EN_MDLM2M 83 +#define RTD1625_CRT_CLK_EN_MDL_XTAL 84 +#define RTD1625_CRT_CLK_EN_TEST_MUX 85 +#define RTD1625_CRT_CLK_EN_DLA 86 +#define RTD1625_CRT_CLK_EN_TPCW 88 +#define RTD1625_CRT_CLK_EN_GPU_TS_SRC 89 +#define RTD1625_CRT_CLK_EN_VI 91 +#define RTD1625_CRT_CLK_EN_LVDS1 92 +#define RTD1625_CRT_CLK_EN_LVDS2 93 +#define RTD1625_CRT_CLK_EN_AUCPU 94 +#define RTD1625_CRT_CLK_EN_UR1 96 +#define RTD1625_CRT_CLK_EN_UR2 97 +#define RTD1625_CRT_CLK_EN_UR3 98 +#define RTD1625_CRT_CLK_EN_UR4 99 +#define RTD1625_CRT_CLK_EN_UR5 100 +#define RTD1625_CRT_CLK_EN_UR6 101 +#define RTD1625_CRT_CLK_EN_UR7 102 +#define RTD1625_CRT_CLK_EN_UR8 103 +#define RTD1625_CRT_CLK_EN_UR9 104 +#define RTD1625_CRT_CLK_EN_UR_TOP 105 +#define RTD1625_CRT_CLK_EN_MISC_I2C_7 110 +#define RTD1625_CRT_CLK_EN_MISC_I2C_6 111 +#define RTD1625_CRT_CLK_EN_SPI0 112 +#define RTD1625_CRT_CLK_EN_SPI1 113 +#define RTD1625_CRT_CLK_EN_SPI2 114 +#define RTD1625_CRT_CLK_EN_LSADC0 120 +#define RTD1625_CRT_CLK_EN_LSADC1 121 +#define RTD1625_CRT_CLK_EN_ISOMIS_DMA 122 +#define RTD1625_CRT_CLK_EN_DPTX 124 +#define RTD1625_CRT_CLK_EN_NPU_MIPI_CSI 125 +#define RTD1625_CRT_CLK_EN_EDPTX 126 +#define RTD1625_CRT_CLK_HIFI 128 +#define RTD1625_CRT_CLK_NPU_MIPI_CSI 129 +#define RTD1625_CRT_CLK_NPU 130 +#define RTD1625_CRT_CLK_NPU_SYSH 132 +#define RTD1625_CRT_CLK_HIFI_SCPU 133 +#define RTD1625_CRT_CLK_GPU 134 +#define RTD1625_CRT_CLK_GPU2D 135 +#define RTD1625_CRT_CLK_MIPI_DSI_PCLK 136 +#define RTD1625_CRT_CLK_VE1 137 +#define RTD1625_CRT_CLK_VE2 138 +#define RTD1625_CRT_CLK_VE4 139 +#define RTD1625_CRT_CLK_SYS 141 +#define RTD1625_CRT_CLK_SYSH 142 +#define RTD1625_CRT_PLL_SDIO_REF 145 +#define RTD1625_CRT_PLL_CR_REF 146 +#define RTD1625_CRT_PLL_EMMC_REF 147 +#define RTD1625_CRT_CLK_MIS_SC0 148 +#define RTD1625_CRT_CLK_MIS_SC1 149 +#define RTD1625_CRT_PLL_SCPU 150 +#define RTD1625_CRT_PLL_VE1 151 +#define RTD1625_CRT_PLL_DDSA 152 +#define RTD1625_CRT_PLL_PSAUDA1 153 +#define RTD1625_CRT_PLL_PSAUDA2 154 +#define RTD1625_CRT_PLL_BUS 155 +#define RTD1625_CRT_PLL_SDIO 156 +#define RTD1625_CRT_PLL_SDIO_VP0 157 +#define RTD1625_CRT_PLL_SDIO_VP1 158 +#define RTD1625_CRT_PLL_DCSB 159 +#define RTD1625_CRT_PLL_GPU 160 +#define RTD1625_CRT_PLL_NPU 161 +#define RTD1625_CRT_PLL_VE2 162 +#define RTD1625_CRT_PLL_HIFI 163 +#define RTD1625_CRT_PLL_SD 164 +#define RTD1625_CRT_PLL_SD_VP0 165 +#define RTD1625_CRT_PLL_SD_VP1 166 +#define RTD1625_CRT_PLL_EMMC 167 +#define RTD1625_CRT_PLL_EMMC_VP0 168 +#define RTD1625_CRT_PLL_EMMC_VP1 169 +#define RTD1625_CRT_PLL_ACPU 170 +#define RTD1625_CRT_CLK_DET 171 + +#define RTD1625_ISO_CLK_EN_USB_P4 0 +#define RTD1625_ISO_CLK_EN_USB_P3 1 +#define RTD1625_ISO_CLK_EN_MISC_CEC0 2 +#define RTD1625_ISO_CLK_EN_CBUSRX_SYS 3 +#define RTD1625_ISO_CLK_EN_CBUSTX_SYS 4 +#define RTD1625_ISO_CLK_EN_CBUS_SYS 5 +#define RTD1625_ISO_CLK_EN_CBUS_OSC 6 +#define RTD1625_ISO_CLK_EN_MISC_UR0 8 +#define RTD1625_ISO_CLK_EN_I2C0 9 +#define RTD1625_ISO_CLK_EN_I2C1 10 +#define RTD1625_ISO_CLK_EN_ETN_250M 11 +#define RTD1625_ISO_CLK_EN_ETN_SYS 12 +#define RTD1625_ISO_CLK_EN_USB_DRD 13 +#define RTD1625_ISO_CLK_EN_USB_HOST 14 +#define RTD1625_ISO_CLK_EN_USB_U3_HOST 15 +#define RTD1625_ISO_CLK_EN_USB 16 +#define RTD1625_ISO_CLK_EN_VTC 17 +#define RTD1625_ISO_CLK_EN_MISC_VFD 18 + +#define RTD1625_ISO_S_CLK_EN_ISOM_MIS 0 +#define RTD1625_ISO_S_CLK_EN_ISOM_GPIOM 1 +#define RTD1625_ISO_S_CLK_EN_TIMER7 2 +#define RTD1625_ISO_S_CLK_EN_IRDA 3 +#define RTD1625_ISO_S_CLK_EN_UR10 4 + +#endif /* __DT_BINDINGS_RTK_CLOCK_RTD1625_H */ diff --git a/include/dt-bindings/reset/realtek,rtd1625.h b/include/dt-bindings/reset/realtek,rtd1625.h new file mode 100644 index 000000000000..31e7fa66ef31 --- /dev/null +++ b/include/dt-bindings/reset/realtek,rtd1625.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Realtek Semiconductor Corp. + */ + +#ifndef __DT_BINDINGS_RTK_RESET_RTD1625_H +#define __DT_BINDINGS_RTK_RESET_RTD1625_H + +#define RTD1625_CRT_RSTN_MISC 0 +#define RTD1625_CRT_RSTN_DIP 1 +#define RTD1625_CRT_RSTN_GSPI 2 +#define RTD1625_CRT_RSTN_SDS 3 +#define RTD1625_CRT_RSTN_SDS_REG 4 +#define RTD1625_CRT_RSTN_SDS_PHY 5 +#define RTD1625_CRT_RSTN_GPU2D 6 +#define RTD1625_CRT_RSTN_DC_PHY 7 +#define RTD1625_CRT_RSTN_DCPHY_CRT 8 +#define RTD1625_CRT_RSTN_LSADC 9 +#define RTD1625_CRT_RSTN_SE 10 +#define RTD1625_CRT_RSTN_DLA 11 +#define RTD1625_CRT_RSTN_JPEG 12 +#define RTD1625_CRT_RSTN_SD 13 +#define RTD1625_CRT_RSTN_SDIO 14 +#define RTD1625_CRT_RSTN_PCR_CNT 15 +#define RTD1625_CRT_RSTN_PCIE0_STITCH 16 +#define RTD1625_CRT_RSTN_PCIE0_PHY 17 +#define RTD1625_CRT_RSTN_PCIE0 18 +#define RTD1625_CRT_RSTN_PCIE0_CORE 19 +#define RTD1625_CRT_RSTN_PCIE0_POWER 20 +#define RTD1625_CRT_RSTN_PCIE0_NONSTICH 21 +#define RTD1625_CRT_RSTN_PCIE0_PHY_MDIO 22 +#define RTD1625_CRT_RSTN_PCIE0_SGMII_MDIO 23 +#define RTD1625_CRT_RSTN_VO2 24 +#define RTD1625_CRT_RSTN_MISC_SC0 25 +#define RTD1625_CRT_RSTN_MD 26 +#define RTD1625_CRT_RSTN_LVDS1 27 +#define RTD1625_CRT_RSTN_LVDS2 28 +#define RTD1625_CRT_RSTN_MISC_SC1 29 +#define RTD1625_CRT_RSTN_I2C_3 30 +#define RTD1625_CRT_RSTN_FAN 31 +#define RTD1625_CRT_RSTN_TVE 32 +#define RTD1625_CRT_RSTN_AIO 33 +#define RTD1625_CRT_RSTN_VO 34 +#define RTD1625_CRT_RSTN_MIPI_CSI 35 +#define RTD1625_CRT_RSTN_HDMIRX 36 +#define RTD1625_CRT_RSTN_HDMIRX_WRAP 37 +#define RTD1625_CRT_RSTN_HDMI 38 +#define RTD1625_CRT_RSTN_DISP 39 +#define RTD1625_CRT_RSTN_SATA_PHY_POW1 40 +#define RTD1625_CRT_RSTN_SATA_PHY_POW0 41 +#define RTD1625_CRT_RSTN_SATA_MDIO1 42 +#define RTD1625_CRT_RSTN_SATA_MDIO0 43 +#define RTD1625_CRT_RSTN_SATA_WRAP 44 +#define RTD1625_CRT_RSTN_SATA_MAC_P1 45 +#define RTD1625_CRT_RSTN_SATA_MAC_P0 46 +#define RTD1625_CRT_RSTN_SATA_MAC_COM 47 +#define RTD1625_CRT_RSTN_PCIE1_STITCH 48 +#define RTD1625_CRT_RSTN_PCIE1_PHY 49 +#define RTD1625_CRT_RSTN_PCIE1 50 +#define RTD1625_CRT_RSTN_PCIE1_CORE 51 +#define RTD1625_CRT_RSTN_PCIE1_POWER 52 +#define RTD1625_CRT_RSTN_PCIE1_NONSTICH 53 +#define RTD1625_CRT_RSTN_PCIE1_PHY_MDIO 54 +#define RTD1625_CRT_RSTN_HDMITOP 55 +#define RTD1625_CRT_RSTN_I2C_4 56 +#define RTD1625_CRT_RSTN_I2C_5 57 +#define RTD1625_CRT_RSTN_TSIO 58 +#define RTD1625_CRT_RSTN_VI 59 +#define RTD1625_CRT_RSTN_EDP 60 +#define RTD1625_CRT_RSTN_VE1_MMU 61 +#define RTD1625_CRT_RSTN_VE1_MMU_FUNC 62 +#define RTD1625_CRT_RSTN_HSE_MMU 63 +#define RTD1625_CRT_RSTN_HSE_MMU_FUNC 64 +#define RTD1625_CRT_RSTN_MDLM2M 65 +#define RTD1625_CRT_RSTN_ISO_GSPI 66 +#define RTD1625_CRT_RSTN_SOFT_NPU 67 +#define RTD1625_CRT_RSTN_SPI2EMMC 68 +#define RTD1625_CRT_RSTN_EARC 69 +#define RTD1625_CRT_RSTN_VE1 70 +#define RTD1625_CRT_RSTN_PCIE2_STITCH 71 +#define RTD1625_CRT_RSTN_PCIE2_PHY 72 +#define RTD1625_CRT_RSTN_PCIE2 73 +#define RTD1625_CRT_RSTN_PCIE2_CORE 74 +#define RTD1625_CRT_RSTN_PCIE2_POWER 75 +#define RTD1625_CRT_RSTN_PCIE2_NONSTICH 76 +#define RTD1625_CRT_RSTN_PCIE2_PHY_MDIO 77 +#define RTD1625_CRT_RSTN_DCPHY_UMCTL2 78 +#define RTD1625_CRT_RSTN_MIPI_DSI 79 +#define RTD1625_CRT_RSTN_HIFM 80 +#define RTD1625_CRT_RSTN_NSRAM 81 +#define RTD1625_CRT_RSTN_AUCPU0_REG 82 +#define RTD1625_CRT_RSTN_MDL_GENPW 83 +#define RTD1625_CRT_RSTN_MDL_CHIP 84 +#define RTD1625_CRT_RSTN_MDL_IP 85 +#define RTD1625_CRT_RSTN_TEST_MUX 86 +#define RTD1625_CRT_RSTN_ISO_BIST 87 +#define RTD1625_CRT_RSTN_MAIN_BIST 88 +#define RTD1625_CRT_RSTN_MAIN2_BIST 89 +#define RTD1625_CRT_RSTN_VE1_BIST 90 +#define RTD1625_CRT_RSTN_VE2_BIST 91 +#define RTD1625_CRT_RSTN_DCPHY_BIST 92 +#define RTD1625_CRT_RSTN_GPU_BIST 93 +#define RTD1625_CRT_RSTN_DISP_BIST 94 +#define RTD1625_CRT_RSTN_NPU_BIST 95 +#define RTD1625_CRT_RSTN_CAS_BIST 96 +#define RTD1625_CRT_RSTN_VE4_BIST 97 +#define RTD1625_CRT_RSTN_EMMC 98 +#define RTD1625_CRT_RSTN_GPU 99 +#define RTD1625_CRT_RSTN_VE2 100 +#define RTD1625_CRT_RSTN_UR1 101 +#define RTD1625_CRT_RSTN_UR2 102 +#define RTD1625_CRT_RSTN_UR3 103 +#define RTD1625_CRT_RSTN_UR4 104 +#define RTD1625_CRT_RSTN_UR5 105 +#define RTD1625_CRT_RSTN_UR6 106 +#define RTD1625_CRT_RSTN_UR7 107 +#define RTD1625_CRT_RSTN_UR8 108 +#define RTD1625_CRT_RSTN_UR9 109 +#define RTD1625_CRT_RSTN_UR_TOP 110 +#define RTD1625_CRT_RSTN_I2C_7 111 +#define RTD1625_CRT_RSTN_I2C_6 112 +#define RTD1625_CRT_RSTN_SPI0 113 +#define RTD1625_CRT_RSTN_SPI1 114 +#define RTD1625_CRT_RSTN_SPI2 115 +#define RTD1625_CRT_RSTN_LSADC0 116 +#define RTD1625_CRT_RSTN_LSADC1 117 +#define RTD1625_CRT_RSTN_ISOMIS_DMA 118 +#define RTD1625_CRT_RSTN_AUDIO_ADC 119 +#define RTD1625_CRT_RSTN_DPTX 120 +#define RTD1625_CRT_RSTN_AUCPU1_REG 121 +#define RTD1625_CRT_RSTN_EDPTX 122 + +/* ISO reset */ +#define RTD1625_ISO_RSTN_VFD 0 +#define RTD1625_ISO_RSTN_CEC0 1 +#define RTD1625_ISO_RSTN_CEC1 2 +#define RTD1625_ISO_RSTN_CBUSTX 3 +#define RTD1625_ISO_RSTN_CBUSRX 4 +#define RTD1625_ISO_RSTN_USB3_PHY2_XTAL_POW 5 +#define RTD1625_ISO_RSTN_UR0 6 +#define RTD1625_ISO_RSTN_GMAC 7 +#define RTD1625_ISO_RSTN_GPHY 8 +#define RTD1625_ISO_RSTN_I2C_0 9 +#define RTD1625_ISO_RSTN_I2C_1 10 +#define RTD1625_ISO_RSTN_CBUS 11 +#define RTD1625_ISO_RSTN_USB_DRD 12 +#define RTD1625_ISO_RSTN_USB_HOST 13 +#define RTD1625_ISO_RSTN_USB_PHY_0 14 +#define RTD1625_ISO_RSTN_USB_PHY_1 15 +#define RTD1625_ISO_RSTN_USB_PHY_2 16 +#define RTD1625_ISO_RSTN_USB 17 +#define RTD1625_ISO_RSTN_TYPE_C 18 +#define RTD1625_ISO_RSTN_USB_U3_HOST 19 +#define RTD1625_ISO_RSTN_USB3_PHY0_POW 20 +#define RTD1625_ISO_RSTN_USB3_P0_MDIO 21 +#define RTD1625_ISO_RSTN_USB3_PHY1_POW 22 +#define RTD1625_ISO_RSTN_USB3_P1_MDIO 23 +#define RTD1625_ISO_RSTN_VTC 24 +#define RTD1625_ISO_RSTN_USB3_PHY2_POW 25 +#define RTD1625_ISO_RSTN_USB3_P2_MDIO 26 +#define RTD1625_ISO_RSTN_USB_PHY_3 27 +#define RTD1625_ISO_RSTN_USB_PHY_4 28 + +/* ISO_S reset */ +#define RTD1625_ISO_S_RSTN_ISOM_MIS 0 +#define RTD1625_ISO_S_RSTN_GPIOM 1 +#define RTD1625_ISO_S_RSTN_TIMER7 2 +#define RTD1625_ISO_S_RSTN_IRDA 3 +#define RTD1625_ISO_S_RSTN_UR10 4 + +#endif /* __DT_BINDINGS_RTK_RESET_RTD1625_H */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 02/10] reset: Add Realtek basic reset support 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:18 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 03/10] clk: realtek: Introduce a common probe() Yu-Chun Lin ` (7 subsequent siblings) 9 siblings, 1 reply; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Define the reset operations backed by a regmap-based register interface and prepare the reset controller to be registered through the reset framework. Since the reset controllers on Realtek SoCs often share the same register space with the clock controllers, this common framework is designed to extract the regmap and device tree node from the parent device (e.g., an auxiliary device parent). Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - None --- MAINTAINERS | 1 + drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/realtek/Kconfig | 8 +++ drivers/reset/realtek/Makefile | 2 + drivers/reset/realtek/common.c | 90 ++++++++++++++++++++++++++++++++++ drivers/reset/realtek/common.h | 29 +++++++++++ 7 files changed, 132 insertions(+) create mode 100644 drivers/reset/realtek/Kconfig create mode 100644 drivers/reset/realtek/Makefile create mode 100644 drivers/reset/realtek/common.c create mode 100644 drivers/reset/realtek/common.h diff --git a/MAINTAINERS b/MAINTAINERS index 613ca7e95e47..80e840a6691d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22484,6 +22484,7 @@ L: devicetree@vger.kernel.org L: linux-clk@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/clock/realtek* +F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* F: include/dt-bindings/reset/realtek* diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..45a4227b5f44 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -418,6 +418,7 @@ config RESET_ZYNQMP source "drivers/reset/amlogic/Kconfig" source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/realtek/Kconfig" source "drivers/reset/spacemit/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..7330fee91365 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,6 +2,7 @@ obj-y += core.o obj-y += amlogic/ obj-y += hisilicon/ +obj-y += realtek/ obj-y += spacemit/ obj-y += starfive/ obj-y += sti/ diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig new file mode 100644 index 000000000000..bb6dd856a64a --- /dev/null +++ b/drivers/reset/realtek/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +config RESET_RTK_COMMON + tristate "Realtek common reset driver" if COMPILE_TEST + help + This option enables the common reset controller library for + Realtek SoCs. It provides shared reset control operations + (assert, deassert, status) and a registration helper function + that other Realtek-specific reset drivers can use. diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile new file mode 100644 index 000000000000..b59a3f7f2453 --- /dev/null +++ b/drivers/reset/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RESET_RTK_COMMON) += common.o diff --git a/drivers/reset/realtek/common.c b/drivers/reset/realtek/common.c new file mode 100644 index 000000000000..2ce20c25377b --- /dev/null +++ b/drivers/reset/realtek/common.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019-2026 Realtek Semiconductor Corporation + */ + +#include <linux/device.h> +#include <linux/export.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regmap.h> +#include "common.h" + +static inline struct rtk_reset_data *to_rtk_reset_controller(struct reset_controller_dev *r) +{ + return container_of(r, struct rtk_reset_data, rcdev); +} + +static inline const struct rtk_reset_desc *rtk_reset_get_desc(struct rtk_reset_data *data, + unsigned long idx) +{ + return &data->descs[idx]; +} + +static int rtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 mask, val; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + val = desc->write_en ? (0x2U << desc->bit) : 0; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 mask, val; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + val = mask; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_status(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 val; + int ret; + + desc = rtk_reset_get_desc(data, idx); + ret = regmap_read(data->regmap, desc->ofs, &val); + if (ret) + return ret; + + return !((val >> desc->bit) & 1); +} + +static const struct reset_control_ops rtk_reset_ops = { + .assert = rtk_reset_assert, + .deassert = rtk_reset_deassert, + .status = rtk_reset_status, +}; + +/* The caller must initialize data->descs, data->rcdev.nr_resets and + * data->rcdev.owner before calling rtk_reset_controller_add(). + */ +int rtk_reset_controller_add(struct device *dev, + struct rtk_reset_data *data) +{ + data->regmap = dev_get_platdata(dev); + data->rcdev.ops = &rtk_reset_ops; + data->rcdev.dev = dev; + data->rcdev.of_node = dev->parent->of_node; + + return devm_reset_controller_register(dev, &data->rcdev); +} +EXPORT_SYMBOL_NS_GPL(rtk_reset_controller_add, "REALTEK_RESET"); + +MODULE_DESCRIPTION("realtek reset infrastructure"); +MODULE_LICENSE("GPL"); diff --git a/drivers/reset/realtek/common.h b/drivers/reset/realtek/common.h new file mode 100644 index 000000000000..42eb41eae2ec --- /dev/null +++ b/drivers/reset/realtek/common.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + * Author: Yu-Chun Lin <eleanor.lin@realtek.com> + */ + +#ifndef __RESET_REALTEK_COMMON_H +#define __RESET_REALTEK_COMMON_H + +#include <linux/reset-controller.h> + +struct regmap; + +struct rtk_reset_desc { + u32 ofs; + u32 bit; + bool write_en; +}; + +struct rtk_reset_data { + struct reset_controller_dev rcdev; + const struct rtk_reset_desc *descs; + struct regmap *regmap; +}; + +int rtk_reset_controller_add(struct device *dev, + struct rtk_reset_data *initdata); + +#endif /* __RESET_REALTEK_COMMON_H */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v8 02/10] reset: Add Realtek basic reset support 2026-06-10 8:08 ` [PATCH v8 02/10] reset: Add Realtek basic reset support Yu-Chun Lin @ 2026-06-10 8:18 ` sashiko-bot 0 siblings, 0 replies; 15+ messages in thread From: sashiko-bot @ 2026-06-10 8:18 UTC (permalink / raw) To: Yu-Chun Lin; +Cc: devicetree, conor+dt, robh Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Generic module name `common.ko` pollutes the global kernel module namespace. -- commit 67818ad9f005d500ae216802db2e67d2214119c7 Author: Cheng-Yu Lee <cylee12@realtek.com> reset: Add Realtek basic reset support This commit defines common reset operations backed by a regmap-based register interface for Realtek SoCs. It prepares a common reset framework to extract the regmap and device tree node from the parent device. > diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile > new file mode 100644 > index 0000000000000..b59a3f7f2453e > --- /dev/null > +++ b/drivers/reset/realtek/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_RESET_RTK_COMMON) += common.o [Severity: Low] Does this create a module with an overly generic name? Since CONFIG_RESET_RTK_COMMON is a tristate configuration, building it as a module will directly produce a kernel module named common.ko. Because kernel module names occupy a global, flat namespace, this name lacks any vendor or subsystem prefix. Could this risk future naming collisions with other subsystems or confuse users managing modules? Building this as a composite object with a more descriptive name, such as reset-rtk-common.ko, might prevent this. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260610080824.255063-1-eleanor.lin@realtek.com?part=2 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v8 03/10] clk: realtek: Introduce a common probe() 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 02/10] reset: Add Realtek basic reset support Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 04/10] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin ` (6 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Add rtk_clk_probe() to set up the shared regmap, register clock hardware, and add the clock provider. Additionally, if the "#reset-cells" property is present in the device tree, it creates and registers an auxiliary device using the provided aux_name. This allows the dedicated reset driver to bind to this device, enabling both clock and reset drivers to share the same regmap. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - Add depends on RESET_CONTROLLER and select MFD_SYSCON for config RTK_CLK_COMMON. - Fix error handling for devm_auxiliary_device_create(). --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/realtek/Kconfig | 30 ++++++++++++++++ drivers/clk/realtek/Makefile | 4 +++ drivers/clk/realtek/common.c | 66 ++++++++++++++++++++++++++++++++++++ drivers/clk/realtek/common.h | 37 ++++++++++++++++++++ 7 files changed, 140 insertions(+) create mode 100644 drivers/clk/realtek/Kconfig create mode 100644 drivers/clk/realtek/Makefile create mode 100644 drivers/clk/realtek/common.c create mode 100644 drivers/clk/realtek/common.h diff --git a/MAINTAINERS b/MAINTAINERS index 80e840a6691d..aec1ea6d35d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22484,6 +22484,7 @@ L: devicetree@vger.kernel.org L: linux-clk@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/clock/realtek* +F: drivers/clk/realtek/* F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* F: include/dt-bindings/reset/realtek* diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2efbe9f6acb..8bf262dd23a9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -519,6 +519,7 @@ source "drivers/clk/nuvoton/Kconfig" source "drivers/clk/pistachio/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/ralink/Kconfig" +source "drivers/clk/realtek/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a3e2862ebd7e..e226bee2d039 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -140,6 +140,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ obj-y += ralink/ +obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig new file mode 100644 index 000000000000..ed97531e321d --- /dev/null +++ b/drivers/clk/realtek/Kconfig @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only +config COMMON_CLK_REALTEK + tristate "Clock driver for Realtek SoCs" + depends on ARCH_REALTEK || COMPILE_TEST + default ARCH_REALTEK + help + Enable the common clock framework infrastructure for Realtek + system-on-chip platforms. + + This provides the base support required by individual Realtek + clock controller drivers to expose clocks to peripheral devices. + + If you have a Realtek-based platform, say Y. + +if COMMON_CLK_REALTEK + +config RTK_CLK_COMMON + tristate "Realtek Clock Common" + depends on RESET_CONTROLLER + select AUXILIARY_BUS + select MFD_SYSCON + select RESET_RTK_COMMON + help + Common helper code shared by Realtek clock controller drivers. + + This provides utility functions and data structures used by + multiple Realtek clock implementations, and include integration + with reset controllers where required. + +endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile new file mode 100644 index 000000000000..377ec776ee47 --- /dev/null +++ b/drivers/clk/realtek/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o + +clk-rtk-y += common.o diff --git a/drivers/clk/realtek/common.c b/drivers/clk/realtek/common.c new file mode 100644 index 000000000000..1b40fcc59a76 --- /dev/null +++ b/drivers/clk/realtek/common.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include <linux/auxiliary_bus.h> +#include <linux/device.h> +#include <linux/export.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include "common.h" + +static int rtk_reset_controller_register(struct device *dev, const char *aux_name, + struct regmap *map) +{ + struct auxiliary_device *adev; + + if (!of_property_present(dev->of_node, "#reset-cells")) + return 0; + + adev = devm_auxiliary_device_create(dev, aux_name, (void *)map); + + if (!adev) + return -ENOMEM; + + return 0; +} + +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc, + const char *aux_name) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + int i, ret; + + regmap = device_node_to_regmap(dev->of_node); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n"); + + for (i = 0; i < desc->num_clks; i++) + desc->clks[i]->regmap = regmap; + + for (i = 0; i < desc->clk_data->num; i++) { + struct clk_hw *hw = desc->clk_data->hws[i]; + + if (!hw) + continue; + + ret = devm_clk_hw_register(dev, hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register hw of clk%d\n", i); + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + desc->clk_data); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return rtk_reset_controller_register(dev, aux_name, regmap); +} +EXPORT_SYMBOL_NS_GPL(rtk_clk_probe, "REALTEK_CLK"); + +MODULE_DESCRIPTION("Realtek clock infrastructure"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/realtek/common.h b/drivers/clk/realtek/common.h new file mode 100644 index 000000000000..c52fcdbff5ee --- /dev/null +++ b/drivers/clk/realtek/common.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#ifndef __CLK_REALTEK_COMMON_H +#define __CLK_REALTEK_COMMON_H + +#include <linux/clk-provider.h> + +#define __clk_regmap_hw(_p) ((_p)->hw) + +struct device; +struct platform_device; +struct regmap; + +struct clk_regmap { + struct clk_hw hw; + struct regmap *regmap; +}; + +struct rtk_clk_desc { + struct clk_hw_onecell_data *clk_data; + struct clk_regmap * const *clks; + size_t num_clks; +}; + +static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) +{ + return container_of(hw, struct clk_regmap, hw); +} + +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc, + const char *aux_name); + +#endif /* __CLK_REALTEK_COMMON_H */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 04/10] clk: realtek: Add support for phase locked loops (PLLs) 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin ` (2 preceding siblings ...) 2026-06-10 8:08 ` [PATCH v8 03/10] clk: realtek: Introduce a common probe() Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:18 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 05/10] clk: realtek: Add support for gate clock Yu-Chun Lin ` (5 subsequent siblings) 9 siblings, 1 reply; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Provide a full set of PLL operations for programmable PLLs and a read-only variant for fixed or hardware-managed PLLs. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - Reduce the timeout value in regmap_read_poll_timeout_atomic() from 2000ms to 500ms to avoid prolonged busy-waiting and prevent triggering the NMI Watchdog. - Remove 'freq_ready_valid' and add comments to clarify that register offset 0 is never a valid address on Realtek SoCs, meaning it is not configured. - Add the missing spin_unlock_irqrestore() when regmap_read() fails. --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-pll.c | 209 +++++++++++++++++++++++++++++++ drivers/clk/realtek/clk-pll.h | 47 +++++++ drivers/clk/realtek/freq_table.c | 38 ++++++ drivers/clk/realtek/freq_table.h | 16 +++ 5 files changed, 312 insertions(+) create mode 100644 drivers/clk/realtek/clk-pll.c create mode 100644 drivers/clk/realtek/clk-pll.h create mode 100644 drivers/clk/realtek/freq_table.c create mode 100644 drivers/clk/realtek/freq_table.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 377ec776ee47..a89ad77993e9 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += common.o +clk-rtk-y += clk-pll.o +clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-pll.c b/drivers/clk/realtek/clk-pll.c new file mode 100644 index 000000000000..6c4343d71dbe --- /dev/null +++ b/drivers/clk/realtek/clk-pll.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include <linux/export.h> +#include <linux/regmap.h> +#include <linux/spinlock.h> +#include "clk-pll.h" + +#define TIMEOUT 500 + +static inline struct clk_pll *to_clk_pll(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + + return container_of(clkr, struct clk_pll, clkr); +} + +static int wait_freq_ready(struct clk_pll *clkp) +{ + u32 pollval; + + /* reg == 0 means not configured. + * Register offset 0 is never a valid address on Realtek SoCs. + */ + if (!clkp->freq_ready_reg) + return 0; + + return regmap_read_poll_timeout_atomic(clkp->clkr.regmap, clkp->freq_ready_reg, pollval, + (pollval & clkp->freq_ready_mask) == clkp->freq_ready_val, 1, TIMEOUT); +} + +static bool is_power_on(struct clk_pll *clkp) +{ + u32 val; + + /* reg == 0 means not configured (assume always on). + * Register offset 0 is never a valid address on Realtek SoCs. + */ + if (!clkp->power_reg) + return true; + + if (regmap_read(clkp->clkr.regmap, clkp->power_reg, &val)) + return true; + + return (val & clkp->power_mask) == clkp->power_val_on; +} + +static void clk_pll_disable(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + unsigned long flags; + + if (!clkp->seq_power_off) + return; + + spin_lock_irqsave(&clkp->lock, flags); + + regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_off, + clkp->num_seq_power_off); + + spin_unlock_irqrestore(&clkp->lock, flags); +} + +static int clk_pll_is_enabled(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + unsigned long flags; + int ret; + + spin_lock_irqsave(&clkp->lock, flags); + + ret = is_power_on(clkp); + + spin_unlock_irqrestore(&clkp->lock, flags); + + return ret; +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *ftblv = NULL; + + ftblv = ftbl_find_by_rate(clkp->freq_tbl, req->rate); + if (!ftblv) + return -EINVAL; + + req->rate = ftblv->rate; + + return 0; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *fv; + unsigned long flags; + u32 freq_val; + + spin_lock_irqsave(&clkp->lock, flags); + + if (regmap_read(clkp->clkr.regmap, clkp->freq_reg, &freq_val)) { + spin_unlock_irqrestore(&clkp->lock, flags); + return 0; + } + + freq_val &= clkp->freq_mask; + + fv = ftbl_find_by_val_with_mask(clkp->freq_tbl, clkp->freq_mask, + freq_val); + + spin_unlock_irqrestore(&clkp->lock, flags); + + return fv ? fv->rate : 0; +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pll *clkp = to_clk_pll(hw); + const struct freq_table *fv; + unsigned long flags; + int ret; + + fv = ftbl_find_by_rate(clkp->freq_tbl, rate); + if (!fv || fv->rate != rate) + return -EINVAL; + + spin_lock_irqsave(&clkp->lock, flags); + + if (clkp->seq_pre_set_freq) { + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq, + clkp->num_seq_pre_set_freq); + if (ret) + goto unlock; + } + + ret = regmap_update_bits(clkp->clkr.regmap, clkp->freq_reg, + clkp->freq_mask, fv->val); + if (ret) + goto unlock; + + if (clkp->seq_post_set_freq) { + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_freq, + clkp->num_seq_post_set_freq); + if (ret) + goto unlock; + } + + if (is_power_on(clkp)) { + ret = wait_freq_ready(clkp); + if (ret) + goto unlock; + } + +unlock: + spin_unlock_irqrestore(&clkp->lock, flags); + + return ret; +} + +static int clk_pll_enable(struct clk_hw *hw) +{ + struct clk_pll *clkp = to_clk_pll(hw); + unsigned long flags; + int ret = 0; + + if (!clkp->seq_power_on) + return ret; + + spin_lock_irqsave(&clkp->lock, flags); + + if (is_power_on(clkp)) + goto unlock; + + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_on, + clkp->num_seq_power_on); + if (ret) + goto unlock; + + ret = wait_freq_ready(clkp); + if (ret) + goto unlock; + +unlock: + spin_unlock_irqrestore(&clkp->lock, flags); + + return ret; +} + +const struct clk_ops rtk_clk_pll_ops = { + .enable = clk_pll_enable, + .disable = clk_pll_disable, + .is_enabled = clk_pll_is_enabled, + .recalc_rate = clk_pll_recalc_rate, + .determine_rate = clk_pll_determine_rate, + .set_rate = clk_pll_set_rate, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_ops, "REALTEK_CLK"); + +const struct clk_ops rtk_clk_pll_ro_ops = { + .recalc_rate = clk_pll_recalc_rate, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_ro_ops, "REALTEK_CLK"); diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h new file mode 100644 index 000000000000..59abfa9a6122 --- /dev/null +++ b/drivers/clk/realtek/clk-pll.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#ifndef __CLK_REALTEK_CLK_PLL_H +#define __CLK_REALTEK_CLK_PLL_H + +#include <linux/spinlock.h> +#include "common.h" +#include "freq_table.h" + +struct reg_sequence; + +struct clk_pll { + struct clk_regmap clkr; + const struct reg_sequence *seq_power_on; + u32 num_seq_power_on; + const struct reg_sequence *seq_power_off; + u32 num_seq_power_off; + const struct reg_sequence *seq_pre_set_freq; + u32 num_seq_pre_set_freq; + const struct reg_sequence *seq_post_set_freq; + u32 num_seq_post_set_freq; + const struct freq_table *freq_tbl; + u32 freq_reg; + u32 freq_mask; + u32 freq_ready_mask; + u32 freq_ready_reg; + u32 freq_ready_val; + u32 power_reg; + u32 power_mask; + u32 power_val_on; + + /* This lock prevents race conditions when multiple CPUs or contexts + * simultaneously access this PLL's registers during multi-step operations + */ + spinlock_t lock; +}; + +#define __clk_pll_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr) + +extern const struct clk_ops rtk_clk_pll_ops; +extern const struct clk_ops rtk_clk_pll_ro_ops; + +#endif /* __CLK_REALTEK_CLK_PLL_H */ diff --git a/drivers/clk/realtek/freq_table.c b/drivers/clk/realtek/freq_table.c new file mode 100644 index 000000000000..0ff1e5e79102 --- /dev/null +++ b/drivers/clk/realtek/freq_table.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/bitops.h> +#include "freq_table.h" + +#define IS_FREQ_TABLE_END(_f) ((_f)->rate == 0) + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate) +{ + const struct freq_table *best = NULL; + unsigned long best_rate = 0; + + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if (ftbl->rate == rate) + return ftbl; + + if (ftbl->rate > rate) + continue; + + if (ftbl->rate > best_rate) { + best_rate = ftbl->rate; + best = ftbl; + } + } + + return best; +} + +const struct freq_table * +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value) +{ + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if ((ftbl->val & mask) == (value & mask)) + return ftbl; + } + return NULL; +}; diff --git a/drivers/clk/realtek/freq_table.h b/drivers/clk/realtek/freq_table.h new file mode 100644 index 000000000000..16bf7e3fd489 --- /dev/null +++ b/drivers/clk/realtek/freq_table.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +struct freq_table { + u32 val; + unsigned long rate; +}; + +#define FREQ_TABLE_END \ + { \ + .rate = 0 \ + } + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate); +const struct freq_table * +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value); -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v8 04/10] clk: realtek: Add support for phase locked loops (PLLs) 2026-06-10 8:08 ` [PATCH v8 04/10] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin @ 2026-06-10 8:18 ` sashiko-bot 0 siblings, 0 replies; 15+ messages in thread From: sashiko-bot @ 2026-06-10 8:18 UTC (permalink / raw) To: Yu-Chun Lin; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] `clk_pll_determine_rate()` ignores consumer constraints (`req->min_rate` and `req->max_rate`), leading to invalid frequency selection and rejected clock rate changes. - [High] `is_power_on()` incorrectly returns `true` when register reads fail, masking hardware errors and causing silent enablement failures. - [Low] Unnecessary semicolon at the end of the `ftbl_find_by_val_with_mask` function definition. -- commit 4d3f4fa427421504b7a5b08f5c9946c2979abab1 Author: Cheng-Yu Lee <cylee12@realtek.com> clk: realtek: Add support for phase locked loops (PLLs) Provide a full set of PLL operations for programmable PLLs and a read-only variant for fixed or hardware-managed PLLs. > diff --git a/drivers/clk/realtek/clk-pll.c b/drivers/clk/realtek/clk-pll.c > new file mode 100644 > index 0000000000000..6c4343d71dbe4 > --- /dev/null > +++ b/drivers/clk/realtek/clk-pll.c [ ... ] > +static bool is_power_on(struct clk_pll *clkp) > +{ > + u32 val; > + > + /* reg == 0 means not configured (assume always on). > + * Register offset 0 is never a valid address on Realtek SoCs. > + */ > + if (!clkp->power_reg) > + return true; > + > + if (regmap_read(clkp->clkr.regmap, clkp->power_reg, &val)) > + return true; [Severity: High] Will this incorrectly mask hardware errors and cause silent enablement failures? If regmap_read() fails, the function returns true. This false positive causes clk_pll_enable() to assume the PLL is already powered on. This skips the seq_power_on sequence and immediately returns success, so the clock core framework considers the clock successfully enabled while the physical hardware remains disabled. > + > + return (val & clkp->power_mask) == clkp->power_val_on; > +} [ ... ] > +static int clk_pll_determine_rate(struct clk_hw *hw, > + struct clk_rate_request *req) > +{ > + struct clk_pll *clkp = to_clk_pll(hw); > + const struct freq_table *ftblv = NULL; > + > + ftblv = ftbl_find_by_rate(clkp->freq_tbl, req->rate); [Severity: High] Does this ignore the req->min_rate and req->max_rate constraints? The ftbl_find_by_rate() helper solely searches for the largest available frequency less than or equal to req->rate. If req->rate was clamped to min_rate by the core framework, the search may select an entry strictly less than min_rate. The framework will subsequently reject this out-of-bounds rate, even though a valid higher frequency within the bounds might exist in the table. > + if (!ftblv) > + return -EINVAL; > + > + req->rate = ftblv->rate; > + > + return 0; > +} [ ... ] > diff --git a/drivers/clk/realtek/freq_table.c b/drivers/clk/realtek/freq_table.c > new file mode 100644 > index 0000000000000..0ff1e5e79102b > --- /dev/null > +++ b/drivers/clk/realtek/freq_table.c [ ... ] > +const struct freq_table * > +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 value) > +{ > + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { > + if ((ftbl->val & mask) == (value & mask)) > + return ftbl; > + } > + return NULL; > +}; [Severity: Low] this isn't a bug, but there is an unnecessary semicolon at the end of the ftbl_find_by_val_with_mask() definition. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260610080824.255063-1-eleanor.lin@realtek.com?part=4 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v8 05/10] clk: realtek: Add support for gate clock 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin ` (3 preceding siblings ...) 2026-06-10 8:08 ` [PATCH v8 04/10] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 06/10] clk: realtek: Add support for mux clock Yu-Chun Lin ` (4 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and for standard regmap gate clocks. Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - None --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-regmap-gate.c | 70 +++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index a89ad77993e9..74375f8127ac 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -2,5 +2,7 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += common.o + clk-rtk-y += clk-pll.o +clk-rtk-y += clk-regmap-gate.o clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c new file mode 100644 index 000000000000..0db0057215e3 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include <linux/bits.h> +#include <linux/clk-provider.h> +#include <linux/export.h> +#include <linux/regmap.h> +#include "clk-regmap-gate.h" + +static int clk_regmap_gate_enable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = BIT(clkg->bit_idx); + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static void clk_regmap_gate_disable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = 0; + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw); + int ret; + u32 val; + + ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops rtk_clk_regmap_gate_ops = { + .enable = clk_regmap_gate_enable, + .disable = clk_regmap_gate_disable, + .is_enabled = clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "REALTEK_CLK"); + +const struct clk_ops rtk_clk_regmap_gate_ro_ops = { + .is_enabled = clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ro_ops, "REALTEK_CLK"); diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h new file mode 100644 index 000000000000..711e168071f6 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "common.h" + +struct clk_regmap_gate { + struct clk_regmap clkr; + int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __clk_regmap_gate_hw(_p) __clk_regmap_hw(&(_p)->clkr) + +#define __CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT(#_name, _parent, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +#define __CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write_en) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +static inline struct clk_regmap_gate *to_clk_regmap_gate(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + + return container_of(clkr, struct clk_regmap_gate, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_gate_ops; +extern const struct clk_ops rtk_clk_regmap_gate_ro_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 06/10] clk: realtek: Add support for mux clock 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin ` (4 preceding siblings ...) 2026-06-10 8:08 ` [PATCH v8 05/10] clk: realtek: Add support for gate clock Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:19 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 07/10] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin ` (3 subsequent siblings) 9 siblings, 1 reply; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Add a simple regmap-based clk_ops implementation for Realtek mux clocks. The implementation supports parent selection and rate determination through regmap-backed register access. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - In clk_regmap_mux_get_parent(), return 0xff instead of 0 to properly indicate an error. - In clk_regmap_mux_set_parent(), cast index to u32 to avoid signed integer - overflow. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-mux.c | 41 ++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-mux.h | 43 ++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-mux.c create mode 100644 drivers/clk/realtek/clk-regmap-mux.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 74375f8127ac..f90dc57fcfdb 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -5,4 +5,5 @@ clk-rtk-y += common.o clk-rtk-y += clk-pll.o clk-rtk-y += clk-regmap-gate.o +clk-rtk-y += clk-regmap-mux.o clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk-regmap-mux.c new file mode 100644 index 000000000000..8bb66a9e244a --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include <linux/clk-provider.h> +#include <linux/export.h> +#include <linux/regmap.h> +#include "clk-regmap-mux.h" + +static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) +{ + struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw); + int num_parents = clk_hw_get_num_parents(hw); + u32 val; + int ret; + + ret = regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val); + if (ret) + return 0; + + val = (val >> clkm->shift) & clkm->mask; + + return val >= num_parents ? 0xff : val; +} + +static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw); + + return regmap_update_bits(clkm->clkr.regmap, clkm->mux_ofs, + clkm->mask << clkm->shift, (u32)index << clkm->shift); +} + +const struct clk_ops rtk_clk_regmap_mux_ops = { + .set_parent = clk_regmap_mux_set_parent, + .get_parent = clk_regmap_mux_get_parent, + .determine_rate = __clk_mux_determine_rate, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_mux_ops, "REALTEK_CLK"); diff --git a/drivers/clk/realtek/clk-regmap-mux.h b/drivers/clk/realtek/clk-regmap-mux.h new file mode 100644 index 000000000000..fff413222d19 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_MUX_H +#define __CLK_REALTEK_CLK_REGMAP_MUX_H + +#include "common.h" + +struct clk_regmap_mux { + struct clk_regmap clkr; + int mux_ofs; + unsigned int mask; + unsigned int shift; +}; + +#define __clk_regmap_mux_hw(_p) __clk_regmap_hw(&(_p)->clkr) + +#define __CLK_REGMAP_MUX(_name, _parents, _ops, _flags, _ofs, _sft, _mask) \ + struct clk_regmap_mux _name = { \ + .clkr.hw.init = \ + CLK_HW_INIT_PARENTS(#_name, _parents, _ops, _flags), \ + .mux_ofs = _ofs, \ + .shift = _sft, \ + .mask = _mask, \ + } + +#define CLK_REGMAP_MUX(_name, _parents, _flags, _ofs, _sft, _mask) \ + __CLK_REGMAP_MUX(_name, _parents, &rtk_clk_regmap_mux_ops, _flags, _ofs, \ + _sft, _mask) + +static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + + return container_of(clkr, struct clk_regmap_mux, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_mux_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_MUX_H */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v8 06/10] clk: realtek: Add support for mux clock 2026-06-10 8:08 ` [PATCH v8 06/10] clk: realtek: Add support for mux clock Yu-Chun Lin @ 2026-06-10 8:19 ` sashiko-bot 0 siblings, 0 replies; 15+ messages in thread From: sashiko-bot @ 2026-06-10 8:19 UTC (permalink / raw) To: Yu-Chun Lin; +Cc: conor+dt, devicetree, robh Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] clk_regmap_mux_get_parent() returns 0 instead of an error indicator when regmap_read() fails, silently masking the I/O error and confusing the Common Clock Framework. -- commit 6f252a1d2352da3ab0338149dff431cfd1082f04 Author: Cheng-Yu Lee <cylee12@realtek.com> clk: realtek: Add support for mux clock Add a simple regmap-based clk_ops implementation for Realtek mux clocks. The implementation supports parent selection and rate determination through regmap-backed register access. > diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk-regmap-mux.c > new file mode 100644 > index 0000000000000..8bb66a9e244a1 > --- /dev/null > +++ b/drivers/clk/realtek/clk-regmap-mux.c [ ... ] > +static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) > +{ > + struct clk_regmap_mux *clkm = to_clk_regmap_mux(hw); > + int num_parents = clk_hw_get_num_parents(hw); > + u32 val; > + int ret; > + > + ret = regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val); > + if (ret) > + return 0; [Severity: High] When regmap_read() fails here, it returns 0. Since 0 is a valid parent index in the Common Clock Framework, will this mask the I/O error and falsely report that parent 0 is active? If the hardware was actually using a different parent, this could lead the CCF to incorrectly assume the actual parent has no active children and potentially gate it during clk_disable_unused(). Would it be safer to return an out-of-bounds value like 0xff (which is used later in this function) or an error code when the read fails, to prevent the CCF from making incorrect assumptions about the hardware state? [ ... ] -- Sashiko AI review · https://sashiko.dev/#/patchset/20260610080824.255063-1-eleanor.lin@realtek.com?part=6 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v8 07/10] clk: realtek: Add support for MMC-tuned PLL clocks 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin ` (5 preceding siblings ...) 2026-06-10 8:08 ` [PATCH v8 06/10] clk: realtek: Add support for mux clock Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:19 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 08/10] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin ` (2 subsequent siblings) 9 siblings, 1 reply; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Add clk_pll_mmc_ops for enable/disable, prepare, rate control, and status operations on MMC PLL clocks. Also add clk_pll_mmc_phase_ops to support phase get/set operations. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Jyan Chou <jyanchou@realtek.com> Signed-off-by: Jyan Chou <jyanchou@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - Fix the mask shift in set_phrt0(). - For better safety and readability, modify pointer comparison for phase_id. - In clk_pll_mmc_recalc_rate(), return 0 instead of an error code upon failure. --- MAINTAINERS | 8 + drivers/clk/realtek/Kconfig | 3 + drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-pll-mmc.c | 459 ++++++++++++++++++++++++++++++ drivers/clk/realtek/clk-pll.h | 13 + 5 files changed, 485 insertions(+) create mode 100644 drivers/clk/realtek/clk-pll-mmc.c diff --git a/MAINTAINERS b/MAINTAINERS index aec1ea6d35d6..52d8099d32a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22489,6 +22489,14 @@ F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* F: include/dt-bindings/reset/realtek* +REALTEK SOC PLL CLOCK FOR MMC SUPPORT +M: Cheng-Yu Lee <cylee12@realtek.com> +M: Jyan Chou <jyanchou@realtek.com> +M: Yu-Chun Lin <eleanor.lin@realtek.com> +L: linux-clk@vger.kernel.org +S: Supported +F: drivers/clk/realtek/clk-pll-mmc.c + REALTEK SPI-NAND M: Chris Packham <chris.packham@alliedtelesis.co.nz> S: Maintained diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig index ed97531e321d..5a832fc3228a 100644 --- a/drivers/clk/realtek/Kconfig +++ b/drivers/clk/realtek/Kconfig @@ -27,4 +27,7 @@ config RTK_CLK_COMMON multiple Realtek clock implementations, and include integration with reset controllers where required. +config RTK_CLK_PLL_MMC + tristate + endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index f90dc57fcfdb..fd7d777902c8 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -7,3 +7,5 @@ clk-rtk-y += clk-pll.o clk-rtk-y += clk-regmap-gate.o clk-rtk-y += clk-regmap-mux.o clk-rtk-y += freq_table.o + +clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) += clk-pll-mmc.o diff --git a/drivers/clk/realtek/clk-pll-mmc.c b/drivers/clk/realtek/clk-pll-mmc.c new file mode 100644 index 000000000000..c11cb2bd577e --- /dev/null +++ b/drivers/clk/realtek/clk-pll-mmc.c @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include <linux/bits.h> +#include <linux/export.h> +#include <linux/math64.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include "clk-pll.h" + +#define PLL_EMMC1_OFFSET 0x0 +#define PLL_EMMC2_OFFSET 0x4 +#define PLL_EMMC3_OFFSET 0x8 +#define PLL_EMMC4_OFFSET 0xc +#define PLL_SSC_DIG_EMMC1_OFFSET 0x0 +#define PLL_SSC_DIG_EMMC3_OFFSET 0xc +#define PLL_SSC_DIG_EMMC4_OFFSET 0x10 + +#define PLL_MMC_SSC_DIV_N_VAL 0x1b + +#define PLL_PHRT0_MASK BIT(0) +#define PLL_PHSEL_MASK GENMASK(4, 0) +#define PLL_SSCPLL_RS_MASK GENMASK(12, 10) +#define PLL_SSCPLL_ICP_MASK GENMASK(9, 5) +#define PLL_SSC_DIV_EXT_F_MASK GENMASK(25, 13) +#define PLL_PI_IBSELH_MASK GENMASK(28, 27) +#define PLL_SSC_DIV_N_MASK GENMASK(23, 16) +#define PLL_NCODE_SSC_EMMC_MASK GENMASK(20, 13) +#define PLL_FCODE_SSC_EMMC_MASK GENMASK(12, 0) +#define PLL_GRAN_EST_EM_MC_MASK GENMASK(20, 0) +#define PLL_EN_SSC_EMMC_MASK BIT(0) +#define PLL_FLAG_INITAL_EMMC_MASK BIT(8) + +#define PLL_PHRT0_SHIFT 1 +#define PLL_SSCPLL_RS_SHIFT 10 +#define PLL_SSCPLL_ICP_SHIFT 5 +#define PLL_SSC_DIV_EXT_F_SHIFT 13 +#define PLL_PI_IBSELH_SHIFT 27 +#define PLL_SSC_DIV_N_SHIFT 16 +#define PLL_NCODE_SSC_EMMC_SHIFT 13 +#define PLL_FLAG_INITAL_EMMC_SHIFT 8 + +#define CYCLE_DEGREES 360 +#define PHASE_STEPS 32 +#define PHASE_SCALE_FACTOR 1125 + +static inline struct clk_pll_mmc *to_clk_pll_mmc(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + + return container_of(clkr, struct clk_pll_mmc, clkr); +} + +static inline int get_phrt0(struct clk_pll_mmc *clkm, u32 *val) +{ + u32 reg; + int ret; + + ret = regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, ®); + if (ret) + return ret; + + *val = (reg >> PLL_PHRT0_SHIFT) & PLL_PHRT0_MASK; + + return 0; +} + +static inline int set_phrt0(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, + PLL_PHRT0_MASK << PLL_PHRT0_SHIFT, val << PLL_PHRT0_SHIFT); +} + +static inline int get_phsel(struct clk_pll_mmc *clkm, int id, u32 *val) +{ + u32 sft = id ? 8 : 3; + u32 raw_val; + int ret; + + ret = regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, &raw_val); + if (ret) + return ret; + + *val = (raw_val >> sft) & PLL_PHSEL_MASK; + + return 0; +} + +static inline int set_phsel(struct clk_pll_mmc *clkm, int id, u32 val) +{ + u32 sft = id ? 8 : 3; + + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, + PLL_PHSEL_MASK << sft, val << sft); +} + +static inline int set_sscpll_rs(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OFFSET, + PLL_SSCPLL_RS_MASK, val << PLL_SSCPLL_RS_SHIFT); +} + +static inline int set_sscpll_icp(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OFFSET, + PLL_SSCPLL_ICP_MASK, val << PLL_SSCPLL_ICP_SHIFT); +} + +static inline int get_ssc_div_ext_f(struct clk_pll_mmc *clkm, u32 *val) +{ + u32 raw_val; + int ret; + + ret = regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OFFSET, &raw_val); + if (ret) + return ret; + + *val = (raw_val & PLL_SSC_DIV_EXT_F_MASK) >> PLL_SSC_DIV_EXT_F_SHIFT; + + return 0; +} + +static inline int set_ssc_div_ext_f(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OFFSET, + PLL_SSC_DIV_EXT_F_MASK, + val << PLL_SSC_DIV_EXT_F_SHIFT); +} + +static inline int set_pi_ibselh(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OFFSET, + PLL_PI_IBSELH_MASK, val << PLL_PI_IBSELH_SHIFT); +} + +static inline int set_ssc_div_n(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC3_OFFSET, + PLL_SSC_DIV_N_MASK, val << PLL_SSC_DIV_N_SHIFT); +} + +static inline int get_ssc_div_n(struct clk_pll_mmc *clkm, u32 *val) +{ + int ret; + u32 raw_val; + + ret = regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC3_OFFSET, &raw_val); + if (ret) + return ret; + + *val = (raw_val & PLL_SSC_DIV_N_MASK) >> PLL_SSC_DIV_N_SHIFT; + + return 0; +} + +static inline int set_pow_ctl(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_write(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC4_OFFSET, val); +} + +static inline int get_pow_ctl(struct clk_pll_mmc *clkm, u32 *val) +{ + int ret; + u32 raw_val; + + ret = regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC4_OFFSET, &raw_val); + if (ret) + return ret; + + *val = raw_val; + + return 0; +} + +static int clk_pll_mmc_phase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_hw *hwp = clk_hw_get_parent(hw); + struct clk_pll_mmc *clkm; + int phase_id; + int ret; + u32 val; + + if (!hwp) + return -ENOENT; + + clkm = to_clk_pll_mmc(hwp); + phase_id = (hw == &clkm->phase0_hw) ? 0 : 1; + val = DIV_ROUND_CLOSEST(degrees * 100, PHASE_SCALE_FACTOR); + ret = set_phsel(clkm, phase_id, val); + if (ret) + return ret; + + usleep_range(10, 20); + + return 0; +} + +static int clk_pll_mmc_phase_get_phase(struct clk_hw *hw) +{ + struct clk_hw *hwp; + struct clk_pll_mmc *clkm; + int phase_id; + int ret; + u32 val; + + hwp = clk_hw_get_parent(hw); + if (!hwp) + return -ENOENT; + + clkm = to_clk_pll_mmc(hwp); + phase_id = (hw == &clkm->phase0_hw) ? 0 : 1; + ret = get_phsel(clkm, phase_id, &val); + if (ret) + return ret; + + val = DIV_ROUND_CLOSEST(val * CYCLE_DEGREES, PHASE_STEPS); + + return val; +} + +const struct clk_ops rtk_clk_pll_mmc_phase_ops = { + .set_phase = clk_pll_mmc_phase_set_phase, + .get_phase = clk_pll_mmc_phase_get_phase, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_mmc_phase_ops, "REALTEK_CLK"); + +static int clk_pll_mmc_prepare(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + + return set_pow_ctl(clkm, 7); +} + +static void clk_pll_mmc_unprepare(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + + set_pow_ctl(clkm, 0); +} + +static int clk_pll_mmc_is_prepared(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + u32 val; + int ret; + + ret = get_pow_ctl(clkm, &val); + if (ret) + return 1; + + return val != 0x0; +} + +static int clk_pll_mmc_enable(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + int ret; + + ret = set_phrt0(clkm, 1); + if (ret) + return ret; + + udelay(10); + + return 0; +} + +static void clk_pll_mmc_disable(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + + set_phrt0(clkm, 0); + udelay(10); +} + +static int clk_pll_mmc_is_enabled(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + u32 val; + int ret; + + ret = get_phrt0(clkm, &val); + if (ret) + return 1; + + return val == 0x1; +} + +static unsigned long clk_pll_mmc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + u32 val, ext_f; + u64 rate, base; + int ret; + + ret = get_ssc_div_n(clkm, &val); + if (ret) + return 0; + + ret = get_ssc_div_ext_f(clkm, &ext_f); + if (ret) + return 0; + + base = parent_rate / 4; + rate = base * (val + 2); + rate += div_u64(base * ext_f, 8192); + + return rate; +} + +static int clk_pll_mmc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) +{ + u32 val; + + if (!req->best_parent_rate) + return -EINVAL; + + val = DIV_ROUND_CLOSEST(req->rate * 4, req->best_parent_rate); + req->rate = req->best_parent_rate * val / 4; + + return 0; +} + +static int clk_pll_mmc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) +{ + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); + u32 val = PLL_MMC_SSC_DIV_N_VAL; + int ret; + + ret = regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_FLAG_INITAL_EMMC_MASK, 0x0 << PLL_FLAG_INITAL_EMMC_SHIFT); + if (ret) + return ret; + + ret = set_ssc_div_n(clkm, val); + if (ret) + return ret; + + ret = set_ssc_div_ext_f(clkm, 1517); + if (ret) + return ret; + + switch (val) { + case 31 ... 46: + ret = set_pi_ibselh(clkm, 3); + if (ret) + return ret; + + ret = set_sscpll_rs(clkm, 3); + if (ret) + return ret; + + ret = set_sscpll_icp(clkm, 2); + if (ret) + return ret; + break; + + case 20 ... 30: + ret = set_pi_ibselh(clkm, 2); + if (ret) + return ret; + + ret = set_sscpll_rs(clkm, 3); + if (ret) + return ret; + + ret = set_sscpll_icp(clkm, 1); + if (ret) + return ret; + break; + + case 10 ... 19: + ret = set_pi_ibselh(clkm, 1); + if (ret) + return ret; + + ret = set_sscpll_rs(clkm, 2); + if (ret) + return ret; + + ret = set_sscpll_icp(clkm, 1); + if (ret) + return ret; + break; + + case 5 ... 9: + ret = set_pi_ibselh(clkm, 0); + if (ret) + return ret; + + ret = set_sscpll_rs(clkm, 2); + if (ret) + return ret; + + ret = set_sscpll_icp(clkm, 0); + if (ret) + return ret; + break; + } + + ret = regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC3_OFFSET, + PLL_NCODE_SSC_EMMC_MASK, + 27 << PLL_NCODE_SSC_EMMC_SHIFT); + if (ret) + return ret; + + ret = regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC3_OFFSET, + PLL_FCODE_SSC_EMMC_MASK, 321); + if (ret) + return ret; + + ret = regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC4_OFFSET, + PLL_GRAN_EST_EM_MC_MASK, 5985); + if (ret) + return ret; + + ret = regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_EN_SSC_EMMC_MASK, 0x1); + if (ret) + return ret; + + ret = regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_EN_SSC_EMMC_MASK, 0x0); + if (ret) + return ret; + + ret = regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_FLAG_INITAL_EMMC_MASK, + 0x1 << PLL_FLAG_INITAL_EMMC_SHIFT); + if (ret) + return ret; + + usleep_range(10, 20); + + return 0; +} + +const struct clk_ops rtk_clk_pll_mmc_ops = { + .prepare = clk_pll_mmc_prepare, + .unprepare = clk_pll_mmc_unprepare, + .is_prepared = clk_pll_mmc_is_prepared, + .enable = clk_pll_mmc_enable, + .disable = clk_pll_mmc_disable, + .is_enabled = clk_pll_mmc_is_enabled, + .recalc_rate = clk_pll_mmc_recalc_rate, + .determine_rate = clk_pll_mmc_determine_rate, + .set_rate = clk_pll_mmc_set_rate, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_pll_mmc_ops, "REALTEK_CLK"); diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h index 59abfa9a6122..192858013384 100644 --- a/drivers/clk/realtek/clk-pll.h +++ b/drivers/clk/realtek/clk-pll.h @@ -44,4 +44,17 @@ struct clk_pll { extern const struct clk_ops rtk_clk_pll_ops; extern const struct clk_ops rtk_clk_pll_ro_ops; +struct clk_pll_mmc { + struct clk_regmap clkr; + unsigned int pll_ofs; + unsigned int ssc_dig_ofs; + struct clk_hw phase0_hw; + struct clk_hw phase1_hw; +}; + +#define __clk_pll_mmc_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr) + +extern const struct clk_ops rtk_clk_pll_mmc_ops; +extern const struct clk_ops rtk_clk_pll_mmc_phase_ops; + #endif /* __CLK_REALTEK_CLK_PLL_H */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v8 07/10] clk: realtek: Add support for MMC-tuned PLL clocks 2026-06-10 8:08 ` [PATCH v8 07/10] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin @ 2026-06-10 8:19 ` sashiko-bot 0 siblings, 0 replies; 15+ messages in thread From: sashiko-bot @ 2026-06-10 8:19 UTC (permalink / raw) To: Yu-Chun Lin; +Cc: conor+dt, devicetree, robh Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] `clk_pll_mmc_set_rate` entirely ignores dynamic rate parameters and hardcodes the PLL frequency. - [Medium] `clk_pll_mmc_determine_rate` lacks bounds clamping and allows out-of-bounds rates that map to unsupported hardware configurations. - [Low] The tristate `RTK_CLK_PLL_MMC` config causes `clk-pll-mmc.o` to be silently dropped from the build when `CONFIG_RTK_CLK_COMMON=y` and `CONFIG_RTK_CLK_PLL_MMC=m`. -- commit 021382a87679f7b201df250be3c9547b24d2131a Author: Cheng-Yu Lee <cylee12@realtek.com> clk: realtek: Add support for MMC-tuned PLL clocks This commit adds clk_pll_mmc_ops for enable/disable, prepare, rate control, and status operations on MMC PLL clocks. It also adds clk_pll_mmc_phase_ops to support phase get/set operations. > diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig > --- a/drivers/clk/realtek/Kconfig > +++ b/drivers/clk/realtek/Kconfig [ ... ] > @@ -27,4 +27,7 @@ config RTK_CLK_COMMON > multiple Realtek clock implementations, and include integration > with reset controllers where required. > > +config RTK_CLK_PLL_MMC > + tristate > + > endif [ ... ] > diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile > --- a/drivers/clk/realtek/Makefile > +++ b/drivers/clk/realtek/Makefile [ ... ] > @@ -7,3 +7,5 @@ clk-rtk-y += clk-pll.o > clk-rtk-y += clk-regmap-gate.o > clk-rtk-y += clk-regmap-mux.o > clk-rtk-y += freq_table.o > + > +clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) += clk-pll-mmc.o [Severity: Low] When CONFIG_RTK_CLK_COMMON is set to 'y' and CONFIG_RTK_CLK_PLL_MMC is set to 'm', does Kbuild drop clk-pll-mmc.o from the build entirely? Since clk-rtk is a built-in object (obj-y) when CONFIG_RTK_CLK_COMMON=y, conditionally appending to it via clk-rtk-m += clk-pll-mmc.o will cause Kbuild to ignore the module object. This can lead to undefined reference build errors when attempting to link against rtk_clk_pll_mmc_ops. [ ... ] > diff --git a/drivers/clk/realtek/clk-pll-mmc.c b/drivers/clk/realtek/clk-pll-mmc.c > new file mode 100644 > --- /dev/null > +++ b/drivers/clk/realtek/clk-pll-mmc.c [ ... ] > +static int clk_pll_mmc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) > +{ > + u32 val; > + > + if (!req->best_parent_rate) > + return -EINVAL; > + > + val = DIV_ROUND_CLOSEST(req->rate * 4, req->best_parent_rate); > + req->rate = req->best_parent_rate * val / 4; > + > + return 0; > +} [Severity: Medium] Is there a risk of integer overflow here on 32-bit platforms if req->rate exceeds ~1.07 GHz? The calculation req->rate * 4 operates on an unsigned long. Also, does val need to be bounds-checked against the hardware's supported tuning limits? If an extreme rate is requested, the framework might approve it but it could map to unsupported hardware configurations later on, since val is never clamped here. [ ... ] > +static int clk_pll_mmc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) > +{ > + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); > + u32 val = PLL_MMC_SSC_DIV_N_VAL; > + int ret; [Severity: High] Does this function intentionally ignore the rate and parent_rate parameters? Because val is initialized to a hardcoded constant (PLL_MMC_SSC_DIV_N_VAL, which is 27), the hardware is strictly locked to a single static configuration and the dynamic rate arguments are bypassed. Additionally, this hardcoded value causes the subsequent switch statement to unconditionally take the `case 20 ... 30:` branch, making the rest of the frequency ranges dead code. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260610080824.255063-1-eleanor.lin@realtek.com?part=7 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v8 08/10] clk: realtek: Add RTD1625-CRT clock controller driver 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin ` (6 preceding siblings ...) 2026-06-10 8:08 ` [PATCH v8 07/10] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 09/10] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 10/10] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin 9 siblings, 0 replies; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Add support for the CRT (Clock, Reset, and Test) domain clock controller on the Realtek RTD1625 SoC. This driver provides essential clock sources (including PLLs), gating, and multiplexing functionalities for the platform's peripherals. Since the reset controller shares the same register space with the CRT clock controller, it is instantiated as an auxiliary device by the core clock driver. This patch also includes the corresponding auxiliary reset driver to handle the CRT domain resets. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - Remove the trailing NULL element ([RTD1625_CRT_CLK_MAX] = NULL) from the clk_hw_onecell_data arrays. - Add MODULE_DEVICE_TABLE(of, ...) for the tristate config. - Add '.suppress_bind_attrs = true' to avoid handling pointer problem, cause clock should not allow to manually disable by users. - Fix a typo. --- drivers/clk/realtek/Kconfig | 15 + drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-rtd1625-crt.c | 792 ++++++++++++++++++++++ drivers/reset/realtek/Kconfig | 11 + drivers/reset/realtek/Makefile | 1 + drivers/reset/realtek/reset-rtd1625-crt.c | 187 +++++ 6 files changed, 1007 insertions(+) create mode 100644 drivers/clk/realtek/clk-rtd1625-crt.c create mode 100644 drivers/reset/realtek/reset-rtd1625-crt.c diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig index 5a832fc3228a..acfbe95014f4 100644 --- a/drivers/clk/realtek/Kconfig +++ b/drivers/clk/realtek/Kconfig @@ -30,4 +30,19 @@ config RTK_CLK_COMMON config RTK_CLK_PLL_MMC tristate +config CLK_RTD1625 + tristate "RTD1625 Clock Controller" + depends on RESET_CONTROLLER + select RESET_RTD1625 + select RTK_CLK_COMMON + select RTK_CLK_PLL_MMC + help + Support for the clock controller on Realtek RTD1625 SoCs. + + This driver provides clock sources, gating, multiplexing, and + reset control for peripherals on the RTD1625 platform. + + Say Y here if your system is based on the RTD1625 and you need + its peripheral devices to function. + endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index fd7d777902c8..f4a62be092d2 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -9,3 +9,4 @@ clk-rtk-y += clk-regmap-mux.o clk-rtk-y += freq_table.o clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) += clk-pll-mmc.o +obj-$(CONFIG_CLK_RTD1625) += clk-rtd1625-crt.o diff --git a/drivers/clk/realtek/clk-rtd1625-crt.c b/drivers/clk/realtek/clk-rtd1625-crt.c new file mode 100644 index 000000000000..6fa1c1f0d4f3 --- /dev/null +++ b/drivers/clk/realtek/clk-rtd1625-crt.c @@ -0,0 +1,792 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include <dt-bindings/clock/realtek,rtd1625-clk.h> +#include <linux/array_size.h> +#include <linux/bits.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/spinlock.h> +#include "clk-pll.h" +#include "clk-regmap-gate.h" +#include "clk-regmap-mux.h" + +#define RTD1625_CRT_CLK_MAX 172 +#define RTD1625_CRT_RSTN_MAX 123 + +#define RTD1625_REG_PLL_ACPU1 0x10c +#define RTD1625_REG_PLL_ACPU2 0x110 +#define RTD1625_REG_PLL_SSC_DIG_ACPU0 0x5c0 +#define RTD1625_REG_PLL_SSC_DIG_ACPU1 0x5c4 +#define RTD1625_REG_PLL_SSC_DIG_ACPU2 0x5c8 +#define RTD1625_REG_PLL_SSC_DIG_ACPU_DBG2 0x5dc + +#define RTD1625_REG_PLL_VE1_1 0x114 +#define RTD1625_REG_PLL_VE1_2 0x118 +#define RTD1625_REG_PLL_SSC_DIG_VE1_0 0x580 +#define RTD1625_REG_PLL_SSC_DIG_VE1_1 0x584 +#define RTD1625_REG_PLL_SSC_DIG_VE1_2 0x588 +#define RTD1625_REG_PLL_SSC_DIG_VE1_DBG2 0x59c + +#define RTD1625_REG_PLL_GPU1 0x1c0 +#define RTD1625_REG_PLL_GPU2 0x1c4 +#define RTD1625_REG_PLL_SSC_DIG_GPU0 0x5a0 +#define RTD1625_REG_PLL_SSC_DIG_GPU1 0x5a4 +#define RTD1625_REG_PLL_SSC_DIG_GPU2 0x5a8 +#define RTD1625_REG_PLL_SSC_DIG_GPU_DBG2 0x5bc + +#define RTD1625_REG_PLL_NPU1 0x1c8 +#define RTD1625_REG_PLL_NPU2 0x1cc +#define RTD1625_REG_PLL_SSC_DIG_NPU0 0x800 +#define RTD1625_REG_PLL_SSC_DIG_NPU1 0x804 +#define RTD1625_REG_PLL_SSC_DIG_NPU2 0x808 +#define RTD1625_REG_PLL_SSC_DIG_NPU_DBG2 0x81c + +#define RTD1625_REG_PLL_VE2_1 0x1d0 +#define RTD1625_REG_PLL_VE2_2 0x1d4 +#define RTD1625_REG_PLL_SSC_DIG_VE2_0 0x5e0 +#define RTD1625_REG_PLL_SSC_DIG_VE2_1 0x5e4 +#define RTD1625_REG_PLL_SSC_DIG_VE2_2 0x5e8 +#define RTD1625_REG_PLL_SSC_DIG_VE2_DBG2 0x5fc + +#define RTD1625_REG_PLL_HIFI1 0x1d8 +#define RTD1625_REG_PLL_HIFI2 0x1dc +#define RTD1625_REG_PLL_SSC_DIG_HIFI0 0x6e0 +#define RTD1625_REG_PLL_SSC_DIG_HIFI1 0x6e4 +#define RTD1625_REG_PLL_SSC_DIG_HIFI2 0x6e8 +#define RTD1625_REG_PLL_SSC_DIG_HIFI_DBG2 0x6fc + +#define RTD1625_REG_PLL_BUS1 0x524 + +#define RTD1625_REG_PLL_SSC_DIG_DDSA1 0x564 + +#define RTD1625_REG_PLL_SSC_DIG_DCSB1 0x544 + +static const char * const clk_gpu_parents[] = {"pll_gpu", "clk_sys"}; +static CLK_REGMAP_MUX(clk_gpu, clk_gpu_parents, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x28, 12, 0x1); +static const char * const clk_ve_parents[] = {"pll_vo", "clk_sysh", "pll_ve1", "pll_ve2"}; +static CLK_REGMAP_MUX(clk_ve1, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x4c, 0, 0x3); +static CLK_REGMAP_MUX(clk_ve2, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x4c, 3, 0x3); +static CLK_REGMAP_MUX(clk_ve4, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x4c, 6, 0x3); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_misc, CLK_IS_CRITICAL, 0x50, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie0, 0, 0x50, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_gspi, 0, 0x50, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_iso_misc, 0, 0x50, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sds, 0, 0x50, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmi, 0, 0x50, 14, 1); +static CLK_REGMAP_GATE(clk_en_gpu, "clk_gpu", CLK_SET_RATE_PARENT, 0x50, 18, 1); +static CLK_REGMAP_GATE(clk_en_ve1, "clk_ve1", CLK_SET_RATE_PARENT, 0x50, 20, 1); +static CLK_REGMAP_GATE(clk_en_ve2, "clk_ve2", CLK_SET_RATE_PARENT, 0x50, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_se, 0, 0x50, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_md, 0, 0x54, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tp, CLK_IS_CRITICAL, 0x54, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_rcic, 0, 0x54, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_nf, 0, 0x54, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_emmc, 0, 0x54, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sd, 0, 0x54, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sdio_ip, 0, 0x54, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mipi_csi, 0, 0x54, 18, 1); +static CLK_REGMAP_GATE(clk_en_emmc_ip, "pll_emmc", CLK_SET_RATE_PARENT, 0x54, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sdio, 0, 0x54, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sd_ip, 0, 0x54, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tpb, 0, 0x54, 28, 1); +static CLK_REGMAP_GATE(clk_en_misc_sc1, "clk_en_misc", 0, 0x54, 30, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_3, "clk_en_misc", 0, 0x58, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_jpeg, 0, 0x58, 4, 1); +static CLK_REGMAP_GATE(clk_en_acpu, "pll_acpu", CLK_SET_RATE_PARENT, + 0x58, 6, 1); +static CLK_REGMAP_GATE(clk_en_misc_sc0, "clk_en_misc", 0, 0x58, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmirx, 0, 0x58, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hse, CLK_IS_CRITICAL, 0x58, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_fan, 0, 0x5c, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_wrap_sys, 0, 0x5c, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_wrap_sysh, 0, 0x5c, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_mac_sysh, 0, 0x5c, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_r2rdsc, 0, 0x5c, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie1, 0, 0x5c, 18, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_4, "clk_en_misc", 0, 0x5c, 20, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_5, "clk_en_misc", 0, 0x5c, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tsio, 0, 0x5c, 24, 1); +static CLK_REGMAP_GATE(clk_en_ve4, "clk_ve4", CLK_SET_RATE_PARENT, + 0x5c, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_edp, 0, 0x5c, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tsio_trx, 0, 0x5c, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie2, 0, 0x8c, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_earc, 0, 0x8c, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lite, 0, 0x8c, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mipi_dsi, 0, 0x8c, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npupp, 0, 0x8c, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npu, 0, 0x8c, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu0, 0, 0x8c, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu1, 0, 0x8c, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_nsram, 0, 0x8c, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmitop, 0, 0x8c, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu_iso_npu, 0, 0x8c, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_keyladder, 0, 0x8c, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ifcp_klm, 0, 0x8c, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ifcp, 0, 0x8c, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_genpw, 0, 0xb0, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_chip, 0, 0xb0, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_ip, 0, 0xb0, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdlm2m, 0, 0xb0, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_xtal, 0, 0xb0, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_test_mux, 0, 0xb0, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_dla, 0, 0xb0, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tpcw, 0, 0xb0, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_gpu_ts_src, 0, 0xb0, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_vi, 0, 0xb0, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lvds1, 0, 0xb0, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lvds2, 0, 0xb0, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu, 0, 0xb0, 28, 1); +static CLK_REGMAP_GATE(clk_en_ur1, "clk_en_ur_top", 0, 0x884, 0, 1); +static CLK_REGMAP_GATE(clk_en_ur2, "clk_en_ur_top", 0, 0x884, 2, 1); +static CLK_REGMAP_GATE(clk_en_ur3, "clk_en_ur_top", 0, 0x884, 4, 1); +static CLK_REGMAP_GATE(clk_en_ur4, "clk_en_ur_top", 0, 0x884, 6, 1); +static CLK_REGMAP_GATE(clk_en_ur5, "clk_en_ur_top", 0, 0x884, 8, 1); +static CLK_REGMAP_GATE(clk_en_ur6, "clk_en_ur_top", 0, 0x884, 10, 1); +static CLK_REGMAP_GATE(clk_en_ur7, "clk_en_ur_top", 0, 0x884, 12, 1); +static CLK_REGMAP_GATE(clk_en_ur8, "clk_en_ur_top", 0, 0x884, 14, 1); +static CLK_REGMAP_GATE(clk_en_ur9, "clk_en_ur_top", 0, 0x884, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ur_top, CLK_IS_CRITICAL, 0x884, 18, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_7, "clk_en_misc", 0, 0x884, 28, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_6, "clk_en_misc", 0, 0x884, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi0, 0, 0x894, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi1, 0, 0x894, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi2, 0, 0x894, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lsadc0, 0, 0x894, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lsadc1, 0, 0x894, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_isomis_dma, 0, 0x894, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_dptx, 0, 0x894, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npu_mipi_csi, 0, 0x894, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_edptx, 0, 0x894, 28, 1); + +#define FREQ_NF_MASK 0x7ffff +#define FREQ_NF(_r, _nf) {.rate = _r, .val = (_nf),} + +static const struct freq_table acpu_tbl[] = { + FREQ_NF(513000000, 0x11000), + FREQ_TABLE_END +}; + +static const struct freq_table ve_tbl[] = { + FREQ_NF(553500000, 0x12800), + FREQ_NF(661500000, 0x16800), + FREQ_NF(688500000, 0x17800), + FREQ_TABLE_END +}; + +static const struct freq_table bus_tbl[] = { + FREQ_NF(513000000, 0x11000), + FREQ_NF(540000000, 0x12000), + FREQ_NF(553500000, 0x12800), + FREQ_TABLE_END +}; + +static const struct freq_table ddsa_tbl[] = { + FREQ_NF(432000000, 0xe000), + FREQ_TABLE_END +}; + +static const struct freq_table gpu_tbl[] = { + FREQ_NF(405000000, 0xd000), + FREQ_NF(540000000, 0x12000), + FREQ_NF(661500000, 0x16800), + FREQ_NF(729000000, 0x19000), + FREQ_NF(810000000, 0x1c000), + FREQ_NF(850500000, 0x1d800), + FREQ_TABLE_END +}; + +static const struct freq_table hifi_tbl[] = { + FREQ_NF(756000000, 0x1a000), + FREQ_NF(810000000, 0x1c000), + FREQ_TABLE_END +}; + +static const struct freq_table npu_tbl[] = { + FREQ_NF(661500000, 0x16800), + FREQ_NF(729000000, 0x19000), + FREQ_NF(810000000, 0x1c000), + FREQ_TABLE_END +}; + +static const struct reg_sequence pll_acpu_seq_power_on[] = { + {RTD1625_REG_PLL_ACPU2, 0x5}, + {RTD1625_REG_PLL_ACPU2, 0x7}, + {RTD1625_REG_PLL_ACPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_ACPU2, 0x1e1f8e}, + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x5, 200}, + {RTD1625_REG_PLL_ACPU2, 0x3}, +}; + +static const struct reg_sequence pll_acpu_seq_power_off[] = { + {RTD1625_REG_PLL_ACPU2, 0x4}, +}; + +static const struct reg_sequence pll_acpu_seq_pre_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x4}, +}; + +static const struct reg_sequence pll_acpu_seq_post_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x5}, +}; + +static struct clk_pll pll_acpu = { + .clkr.hw.init = CLK_HW_INIT("pll_acpu", "osc27m", &rtk_clk_pll_ops, CLK_GET_RATE_NOCACHE), + .seq_power_on = pll_acpu_seq_power_on, + .num_seq_power_on = ARRAY_SIZE(pll_acpu_seq_power_on), + .seq_power_off = pll_acpu_seq_power_off, + .num_seq_power_off = ARRAY_SIZE(pll_acpu_seq_power_off), + .seq_pre_set_freq = pll_acpu_seq_pre_set_freq, + .num_seq_pre_set_freq = ARRAY_SIZE(pll_acpu_seq_pre_set_freq), + .seq_post_set_freq = pll_acpu_seq_post_set_freq, + .num_seq_post_set_freq = ARRAY_SIZE(pll_acpu_seq_post_set_freq), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_ACPU1, + .freq_tbl = acpu_tbl, + .freq_mask = FREQ_NF_MASK, + .freq_ready_reg = RTD1625_REG_PLL_SSC_DIG_ACPU_DBG2, + .freq_ready_mask = BIT(20), + .freq_ready_val = BIT(20), + .power_reg = RTD1625_REG_PLL_ACPU2, + .power_mask = 0x7, + .power_val_on = 0x3, + .lock = __SPIN_LOCK_UNLOCKED(pll_acpu.lock), +}; + +static const struct reg_sequence pll_ve1_seq_power_on[] = { + {RTD1625_REG_PLL_VE1_2, 0x5}, + {RTD1625_REG_PLL_VE1_2, 0x7}, + {RTD1625_REG_PLL_VE1_1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x5, 200}, + {RTD1625_REG_PLL_VE1_2, 0x3}, +}; + +static const struct reg_sequence pll_ve1_seq_power_off[] = { + {RTD1625_REG_PLL_VE1_2, 0x4}, +}; + +static const struct reg_sequence pll_ve1_seq_pre_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x4}, +}; + +static const struct reg_sequence pll_ve1_seq_post_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x5}, +}; + +static struct clk_pll pll_ve1 = { + .clkr.hw.init = CLK_HW_INIT("pll_ve1", "osc27m", &rtk_clk_pll_ops, CLK_GET_RATE_NOCACHE), + .seq_power_on = pll_ve1_seq_power_on, + .num_seq_power_on = ARRAY_SIZE(pll_ve1_seq_power_on), + .seq_power_off = pll_ve1_seq_power_off, + .num_seq_power_off = ARRAY_SIZE(pll_ve1_seq_power_off), + .seq_pre_set_freq = pll_ve1_seq_pre_set_freq, + .num_seq_pre_set_freq = ARRAY_SIZE(pll_ve1_seq_pre_set_freq), + .seq_post_set_freq = pll_ve1_seq_post_set_freq, + .num_seq_post_set_freq = ARRAY_SIZE(pll_ve1_seq_post_set_freq), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_VE1_1, + .freq_tbl = ve_tbl, + .freq_mask = FREQ_NF_MASK, + .freq_ready_reg = RTD1625_REG_PLL_SSC_DIG_VE1_DBG2, + .freq_ready_mask = BIT(20), + .freq_ready_val = BIT(20), + .power_reg = RTD1625_REG_PLL_VE1_2, + .power_mask = 0x7, + .power_val_on = 0x3, + .lock = __SPIN_LOCK_UNLOCKED(pll_ve1.lock), +}; + +static struct clk_pll pll_ddsa = { + .clkr.hw.init = CLK_HW_INIT("pll_ddsa", "osc27m", &rtk_clk_pll_ro_ops, + CLK_GET_RATE_NOCACHE), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_DDSA1, + .freq_tbl = ddsa_tbl, + .freq_mask = FREQ_NF_MASK, + .lock = __SPIN_LOCK_UNLOCKED(pll_ddsa.lock), +}; + +static struct clk_pll pll_bus = { + .clkr.hw.init = CLK_HW_INIT("pll_bus", "osc27m", &rtk_clk_pll_ro_ops, + CLK_GET_RATE_NOCACHE), + .freq_reg = RTD1625_REG_PLL_BUS1, + .freq_tbl = bus_tbl, + .freq_mask = FREQ_NF_MASK, + .lock = __SPIN_LOCK_UNLOCKED(pll_bus.lock), +}; + +static CLK_FIXED_FACTOR(clk_sys, "clk_sys", "pll_bus", 2, 1, 0); + +static struct clk_pll pll_dcsb = { + .clkr.hw.init = CLK_HW_INIT("pll_dcsb", "osc27m", &rtk_clk_pll_ro_ops, + CLK_GET_RATE_NOCACHE), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_DCSB1, + .freq_tbl = bus_tbl, + .freq_mask = FREQ_NF_MASK, + .lock = __SPIN_LOCK_UNLOCKED(pll_dcsb.lock), +}; + +static CLK_FIXED_FACTOR(clk_sysh, "clk_sysh", "pll_dcsb", 1, 1, 0); + +static const struct reg_sequence pll_gpu_seq_power_on[] = { + {RTD1625_REG_PLL_GPU2, 0x5}, + {RTD1625_REG_PLL_GPU2, 0x7}, + {RTD1625_REG_PLL_GPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x5, 200}, + {RTD1625_REG_PLL_GPU2, 0x3}, +}; + +static const struct reg_sequence pll_gpu_seq_power_off[] = { + {RTD1625_REG_PLL_GPU2, 0x4}, +}; + +static const struct reg_sequence pll_gpu_seq_pre_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x4}, +}; + +static const struct reg_sequence pll_gpu_seq_post_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x5}, +}; + +static struct clk_pll pll_gpu = { + .clkr.hw.init = CLK_HW_INIT("pll_gpu", "osc27m", &rtk_clk_pll_ops, CLK_GET_RATE_NOCACHE), + .seq_power_on = pll_gpu_seq_power_on, + .num_seq_power_on = ARRAY_SIZE(pll_gpu_seq_power_on), + .seq_power_off = pll_gpu_seq_power_off, + .num_seq_power_off = ARRAY_SIZE(pll_gpu_seq_power_off), + .seq_pre_set_freq = pll_gpu_seq_pre_set_freq, + .num_seq_pre_set_freq = ARRAY_SIZE(pll_gpu_seq_pre_set_freq), + .seq_post_set_freq = pll_gpu_seq_post_set_freq, + .num_seq_post_set_freq = ARRAY_SIZE(pll_gpu_seq_post_set_freq), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_GPU1, + .freq_tbl = gpu_tbl, + .freq_mask = FREQ_NF_MASK, + .freq_ready_reg = RTD1625_REG_PLL_SSC_DIG_GPU_DBG2, + .freq_ready_mask = BIT(20), + .freq_ready_val = BIT(20), + .power_reg = RTD1625_REG_PLL_GPU2, + .power_mask = 0x7, + .power_val_on = 0x3, + .lock = __SPIN_LOCK_UNLOCKED(pll_gpu.lock), +}; + +static const struct reg_sequence pll_npu_seq_power_on[] = { + {RTD1625_REG_PLL_NPU2, 0x5}, + {RTD1625_REG_PLL_NPU2, 0x7}, + {RTD1625_REG_PLL_NPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x5, 200}, + {RTD1625_REG_PLL_NPU2, 0x3}, +}; + +static const struct reg_sequence pll_npu_seq_power_off[] = { + {RTD1625_REG_PLL_NPU2, 0x4}, + {RTD1625_REG_PLL_NPU1, 0x54010}, +}; + +static const struct reg_sequence pll_npu_seq_pre_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x4}, +}; + +static const struct reg_sequence pll_npu_seq_post_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x5}, +}; + +static struct clk_pll pll_npu = { + .clkr.hw.init = CLK_HW_INIT("pll_npu", "osc27m", &rtk_clk_pll_ops, + CLK_GET_RATE_NOCACHE), + .seq_power_on = pll_npu_seq_power_on, + .num_seq_power_on = ARRAY_SIZE(pll_npu_seq_power_on), + .seq_power_off = pll_npu_seq_power_off, + .num_seq_power_off = ARRAY_SIZE(pll_npu_seq_power_off), + .seq_pre_set_freq = pll_npu_seq_pre_set_freq, + .num_seq_pre_set_freq = ARRAY_SIZE(pll_npu_seq_pre_set_freq), + .seq_post_set_freq = pll_npu_seq_post_set_freq, + .num_seq_post_set_freq = ARRAY_SIZE(pll_npu_seq_post_set_freq), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_NPU1, + .freq_tbl = npu_tbl, + .freq_mask = FREQ_NF_MASK, + .freq_ready_reg = RTD1625_REG_PLL_SSC_DIG_NPU_DBG2, + .freq_ready_mask = BIT(20), + .freq_ready_val = BIT(20), + .power_reg = RTD1625_REG_PLL_NPU2, + .power_mask = 0x7, + .power_val_on = 0x3, + .lock = __SPIN_LOCK_UNLOCKED(pll_npu.lock), +}; + +static CLK_FIXED_FACTOR(clk_npu, "clk_npu", "pll_npu", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(clk_npu_mipi_csi, "clk_npu_mipi_csi", "pll_npu", 1, 1, + CLK_SET_RATE_PARENT); + +static const struct reg_sequence pll_ve2_seq_power_on[] = { + {RTD1625_REG_PLL_VE2_2, 0x5}, + {RTD1625_REG_PLL_VE2_2, 0x7}, + {RTD1625_REG_PLL_VE2_1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x5, 200}, + {RTD1625_REG_PLL_VE2_2, 0x3}, +}; + +static const struct reg_sequence pll_ve2_seq_power_off[] = { + {RTD1625_REG_PLL_VE2_2, 0x4}, +}; + +static const struct reg_sequence pll_ve2_seq_pre_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x4}, +}; + +static const struct reg_sequence pll_ve2_seq_post_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x5}, +}; + +static struct clk_pll pll_ve2 = { + .clkr.hw.init = CLK_HW_INIT("pll_ve2", "osc27m", &rtk_clk_pll_ops, CLK_GET_RATE_NOCACHE), + .seq_power_on = pll_ve2_seq_power_on, + .num_seq_power_on = ARRAY_SIZE(pll_ve2_seq_power_on), + .seq_power_off = pll_ve2_seq_power_off, + .num_seq_power_off = ARRAY_SIZE(pll_ve2_seq_power_off), + .seq_pre_set_freq = pll_ve2_seq_pre_set_freq, + .num_seq_pre_set_freq = ARRAY_SIZE(pll_ve2_seq_pre_set_freq), + .seq_post_set_freq = pll_ve2_seq_post_set_freq, + .num_seq_post_set_freq = ARRAY_SIZE(pll_ve2_seq_post_set_freq), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_VE2_1, + .freq_tbl = ve_tbl, + .freq_mask = FREQ_NF_MASK, + .freq_ready_reg = RTD1625_REG_PLL_SSC_DIG_VE2_DBG2, + .freq_ready_mask = BIT(20), + .freq_ready_val = BIT(20), + .power_reg = RTD1625_REG_PLL_VE2_2, + .power_mask = 0x7, + .power_val_on = 0x3, + .lock = __SPIN_LOCK_UNLOCKED(pll_ve2.lock), +}; + +static const struct reg_sequence pll_hifi_seq_power_on[] = { + {RTD1625_REG_PLL_HIFI2, 0x5}, + {RTD1625_REG_PLL_HIFI2, 0x7}, + {RTD1625_REG_PLL_HIFI1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x5, 200}, + {RTD1625_REG_PLL_HIFI2, 0x3}, +}; + +static const struct reg_sequence pll_hifi_seq_power_off[] = { + {RTD1625_REG_PLL_HIFI2, 0x4}, +}; + +static const struct reg_sequence pll_hifi_seq_pre_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x4}, +}; + +static const struct reg_sequence pll_hifi_seq_post_set_freq[] = { + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x5}, +}; + +static struct clk_pll pll_hifi = { + .clkr.hw.init = CLK_HW_INIT("pll_hifi", "osc27m", &rtk_clk_pll_ops, CLK_GET_RATE_NOCACHE), + .seq_power_on = pll_hifi_seq_power_on, + .num_seq_power_on = ARRAY_SIZE(pll_hifi_seq_power_on), + .seq_power_off = pll_hifi_seq_power_off, + .num_seq_power_off = ARRAY_SIZE(pll_hifi_seq_power_off), + .seq_pre_set_freq = pll_hifi_seq_pre_set_freq, + .num_seq_pre_set_freq = ARRAY_SIZE(pll_hifi_seq_pre_set_freq), + .seq_post_set_freq = pll_hifi_seq_post_set_freq, + .num_seq_post_set_freq = ARRAY_SIZE(pll_hifi_seq_post_set_freq), + .freq_reg = RTD1625_REG_PLL_SSC_DIG_HIFI1, + .freq_tbl = hifi_tbl, + .freq_mask = FREQ_NF_MASK, + .freq_ready_reg = RTD1625_REG_PLL_SSC_DIG_HIFI_DBG2, + .freq_ready_mask = BIT(20), + .freq_ready_val = BIT(20), + .power_reg = RTD1625_REG_PLL_HIFI2, + .power_mask = 0x7, + .power_val_on = 0x3, + .lock = __SPIN_LOCK_UNLOCKED(pll_hifi.lock), +}; + +static CLK_FIXED_FACTOR(pll_emmc_ref, "pll_emmc_ref", "osc27m", 1, 1, 0); + +static struct clk_pll_mmc pll_emmc = { + .pll_ofs = 0x1f0, + .ssc_dig_ofs = 0x6b0, + .clkr.hw.init = CLK_HW_INIT("pll_emmc", "pll_emmc_ref", &rtk_clk_pll_mmc_ops, 0), + .phase0_hw.init = CLK_HW_INIT("pll_emmc_vp0", "pll_emmc", &rtk_clk_pll_mmc_phase_ops, 0), + .phase1_hw.init = CLK_HW_INIT("pll_emmc_vp1", "pll_emmc", &rtk_clk_pll_mmc_phase_ops, 0), +}; + +static struct clk_regmap * const rtd1625_crt_regmap_clks[] = { + &clk_en_misc.clkr, + &clk_en_pcie0.clkr, + &clk_en_gspi.clkr, + &clk_en_iso_misc.clkr, + &clk_en_sds.clkr, + &clk_en_hdmi.clkr, + &clk_en_gpu.clkr, + &clk_en_ve1.clkr, + &clk_en_ve2.clkr, + &clk_en_se.clkr, + &clk_en_md.clkr, + &clk_en_tp.clkr, + &clk_en_rcic.clkr, + &clk_en_nf.clkr, + &clk_en_emmc.clkr, + &clk_en_sd.clkr, + &clk_en_sdio_ip.clkr, + &clk_en_mipi_csi.clkr, + &clk_en_emmc_ip.clkr, + &clk_en_sdio.clkr, + &clk_en_sd_ip.clkr, + &clk_en_tpb.clkr, + &clk_en_misc_sc1.clkr, + &clk_en_misc_i2c_3.clkr, + &clk_en_jpeg.clkr, + &clk_en_acpu.clkr, + &clk_en_misc_sc0.clkr, + &clk_en_hdmirx.clkr, + &clk_en_hse.clkr, + &clk_en_fan.clkr, + &clk_en_sata_wrap_sys.clkr, + &clk_en_sata_wrap_sysh.clkr, + &clk_en_sata_mac_sysh.clkr, + &clk_en_r2rdsc.clkr, + &clk_en_pcie1.clkr, + &clk_en_misc_i2c_4.clkr, + &clk_en_misc_i2c_5.clkr, + &clk_en_tsio.clkr, + &clk_en_ve4.clkr, + &clk_en_edp.clkr, + &clk_en_tsio_trx.clkr, + &clk_en_pcie2.clkr, + &clk_en_earc.clkr, + &clk_en_lite.clkr, + &clk_en_mipi_dsi.clkr, + &clk_en_npupp.clkr, + &clk_en_npu.clkr, + &clk_en_aucpu0.clkr, + &clk_en_aucpu1.clkr, + &clk_en_nsram.clkr, + &clk_en_hdmitop.clkr, + &clk_en_aucpu_iso_npu.clkr, + &clk_en_keyladder.clkr, + &clk_en_ifcp_klm.clkr, + &clk_en_ifcp.clkr, + &clk_en_mdl_genpw.clkr, + &clk_en_mdl_chip.clkr, + &clk_en_mdl_ip.clkr, + &clk_en_mdlm2m.clkr, + &clk_en_mdl_xtal.clkr, + &clk_en_test_mux.clkr, + &clk_en_dla.clkr, + &clk_en_tpcw.clkr, + &clk_en_gpu_ts_src.clkr, + &clk_en_vi.clkr, + &clk_en_lvds1.clkr, + &clk_en_lvds2.clkr, + &clk_en_aucpu.clkr, + &clk_en_ur1.clkr, + &clk_en_ur2.clkr, + &clk_en_ur3.clkr, + &clk_en_ur4.clkr, + &clk_en_ur5.clkr, + &clk_en_ur6.clkr, + &clk_en_ur7.clkr, + &clk_en_ur8.clkr, + &clk_en_ur9.clkr, + &clk_en_ur_top.clkr, + &clk_en_misc_i2c_7.clkr, + &clk_en_misc_i2c_6.clkr, + &clk_en_spi0.clkr, + &clk_en_spi1.clkr, + &clk_en_spi2.clkr, + &clk_en_lsadc0.clkr, + &clk_en_lsadc1.clkr, + &clk_en_isomis_dma.clkr, + &clk_en_dptx.clkr, + &clk_en_npu_mipi_csi.clkr, + &clk_en_edptx.clkr, + &clk_gpu.clkr, + &clk_ve1.clkr, + &clk_ve2.clkr, + &clk_ve4.clkr, + &pll_ve1.clkr, + &pll_ddsa.clkr, + &pll_bus.clkr, + &pll_dcsb.clkr, + &pll_gpu.clkr, + &pll_npu.clkr, + &pll_ve2.clkr, + &pll_hifi.clkr, + &pll_emmc.clkr, + &pll_acpu.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_crt_hw_data = { + .num = RTD1625_CRT_CLK_MAX, + .hws = { + [RTD1625_CRT_CLK_EN_MISC] = &__clk_regmap_gate_hw(&clk_en_misc), + [RTD1625_CRT_CLK_EN_PCIE0] = &__clk_regmap_gate_hw(&clk_en_pcie0), + [RTD1625_CRT_CLK_EN_GSPI] = &__clk_regmap_gate_hw(&clk_en_gspi), + [RTD1625_CRT_CLK_EN_ISO_MISC] = &__clk_regmap_gate_hw(&clk_en_iso_misc), + [RTD1625_CRT_CLK_EN_SDS] = &__clk_regmap_gate_hw(&clk_en_sds), + [RTD1625_CRT_CLK_EN_HDMI] = &__clk_regmap_gate_hw(&clk_en_hdmi), + [RTD1625_CRT_CLK_EN_GPU] = &__clk_regmap_gate_hw(&clk_en_gpu), + [RTD1625_CRT_CLK_EN_VE1] = &__clk_regmap_gate_hw(&clk_en_ve1), + [RTD1625_CRT_CLK_EN_VE2] = &__clk_regmap_gate_hw(&clk_en_ve2), + [RTD1625_CRT_CLK_EN_MD] = &__clk_regmap_gate_hw(&clk_en_md), + [RTD1625_CRT_CLK_EN_TP] = &__clk_regmap_gate_hw(&clk_en_tp), + [RTD1625_CRT_CLK_EN_RCIC] = &__clk_regmap_gate_hw(&clk_en_rcic), + [RTD1625_CRT_CLK_EN_NF] = &__clk_regmap_gate_hw(&clk_en_nf), + [RTD1625_CRT_CLK_EN_EMMC] = &__clk_regmap_gate_hw(&clk_en_emmc), + [RTD1625_CRT_CLK_EN_SD] = &__clk_regmap_gate_hw(&clk_en_sd), + [RTD1625_CRT_CLK_EN_SDIO_IP] = &__clk_regmap_gate_hw(&clk_en_sdio_ip), + [RTD1625_CRT_CLK_EN_MIPI_CSI] = &__clk_regmap_gate_hw(&clk_en_mipi_csi), + [RTD1625_CRT_CLK_EN_EMMC_IP] = &__clk_regmap_gate_hw(&clk_en_emmc_ip), + [RTD1625_CRT_CLK_EN_SDIO] = &__clk_regmap_gate_hw(&clk_en_sdio), + [RTD1625_CRT_CLK_EN_SD_IP] = &__clk_regmap_gate_hw(&clk_en_sd_ip), + [RTD1625_CRT_CLK_EN_TPB] = &__clk_regmap_gate_hw(&clk_en_tpb), + [RTD1625_CRT_CLK_EN_MISC_SC1] = &__clk_regmap_gate_hw(&clk_en_misc_sc1), + [RTD1625_CRT_CLK_EN_MISC_I2C_3] = &__clk_regmap_gate_hw(&clk_en_misc_i2c_3), + [RTD1625_CRT_CLK_EN_ACPU] = &__clk_regmap_gate_hw(&clk_en_acpu), + [RTD1625_CRT_CLK_EN_JPEG] = &__clk_regmap_gate_hw(&clk_en_jpeg), + [RTD1625_CRT_CLK_EN_MISC_SC0] = &__clk_regmap_gate_hw(&clk_en_misc_sc0), + [RTD1625_CRT_CLK_EN_HDMIRX] = &__clk_regmap_gate_hw(&clk_en_hdmirx), + [RTD1625_CRT_CLK_EN_HSE] = &__clk_regmap_gate_hw(&clk_en_hse), + [RTD1625_CRT_CLK_EN_FAN] = &__clk_regmap_gate_hw(&clk_en_fan), + [RTD1625_CRT_CLK_EN_SATA_WRAP_SYS] = &__clk_regmap_gate_hw(&clk_en_sata_wrap_sys), + [RTD1625_CRT_CLK_EN_SATA_WRAP_SYSH] = &__clk_regmap_gate_hw(&clk_en_sata_wrap_sysh), + [RTD1625_CRT_CLK_EN_SATA_MAC_SYSH] = &__clk_regmap_gate_hw(&clk_en_sata_mac_sysh), + [RTD1625_CRT_CLK_EN_R2RDSC] = &__clk_regmap_gate_hw(&clk_en_r2rdsc), + [RTD1625_CRT_CLK_EN_PCIE1] = &__clk_regmap_gate_hw(&clk_en_pcie1), + [RTD1625_CRT_CLK_EN_MISC_I2C_4] = &__clk_regmap_gate_hw(&clk_en_misc_i2c_4), + [RTD1625_CRT_CLK_EN_MISC_I2C_5] = &__clk_regmap_gate_hw(&clk_en_misc_i2c_5), + [RTD1625_CRT_CLK_EN_TSIO] = &__clk_regmap_gate_hw(&clk_en_tsio), + [RTD1625_CRT_CLK_EN_VE4] = &__clk_regmap_gate_hw(&clk_en_ve4), + [RTD1625_CRT_CLK_EN_EDP] = &__clk_regmap_gate_hw(&clk_en_edp), + [RTD1625_CRT_CLK_EN_TSIO_TRX] = &__clk_regmap_gate_hw(&clk_en_tsio_trx), + [RTD1625_CRT_CLK_EN_PCIE2] = &__clk_regmap_gate_hw(&clk_en_pcie2), + [RTD1625_CRT_CLK_EN_EARC] = &__clk_regmap_gate_hw(&clk_en_earc), + [RTD1625_CRT_CLK_EN_LITE] = &__clk_regmap_gate_hw(&clk_en_lite), + [RTD1625_CRT_CLK_EN_MIPI_DSI] = &__clk_regmap_gate_hw(&clk_en_mipi_dsi), + [RTD1625_CRT_CLK_EN_NPUPP] = &__clk_regmap_gate_hw(&clk_en_npupp), + [RTD1625_CRT_CLK_EN_NPU] = &__clk_regmap_gate_hw(&clk_en_npu), + [RTD1625_CRT_CLK_EN_AUCPU0] = &__clk_regmap_gate_hw(&clk_en_aucpu0), + [RTD1625_CRT_CLK_EN_AUCPU1] = &__clk_regmap_gate_hw(&clk_en_aucpu1), + [RTD1625_CRT_CLK_EN_NSRAM] = &__clk_regmap_gate_hw(&clk_en_nsram), + [RTD1625_CRT_CLK_EN_HDMITOP] = &__clk_regmap_gate_hw(&clk_en_hdmitop), + [RTD1625_CRT_CLK_EN_AUCPU_ISO_NPU] = &__clk_regmap_gate_hw(&clk_en_aucpu_iso_npu), + [RTD1625_CRT_CLK_EN_KEYLADDER] = &__clk_regmap_gate_hw(&clk_en_keyladder), + [RTD1625_CRT_CLK_EN_IFCP_KLM] = &__clk_regmap_gate_hw(&clk_en_ifcp_klm), + [RTD1625_CRT_CLK_EN_IFCP] = &__clk_regmap_gate_hw(&clk_en_ifcp), + [RTD1625_CRT_CLK_EN_MDL_GENPW] = &__clk_regmap_gate_hw(&clk_en_mdl_genpw), + [RTD1625_CRT_CLK_EN_MDL_CHIP] = &__clk_regmap_gate_hw(&clk_en_mdl_chip), + [RTD1625_CRT_CLK_EN_MDL_IP] = &__clk_regmap_gate_hw(&clk_en_mdl_ip), + [RTD1625_CRT_CLK_EN_MDLM2M] = &__clk_regmap_gate_hw(&clk_en_mdlm2m), + [RTD1625_CRT_CLK_EN_MDL_XTAL] = &__clk_regmap_gate_hw(&clk_en_mdl_xtal), + [RTD1625_CRT_CLK_EN_TEST_MUX] = &__clk_regmap_gate_hw(&clk_en_test_mux), + [RTD1625_CRT_CLK_EN_DLA] = &__clk_regmap_gate_hw(&clk_en_dla), + [RTD1625_CRT_CLK_EN_TPCW] = &__clk_regmap_gate_hw(&clk_en_tpcw), + [RTD1625_CRT_CLK_EN_GPU_TS_SRC] = &__clk_regmap_gate_hw(&clk_en_gpu_ts_src), + [RTD1625_CRT_CLK_EN_VI] = &__clk_regmap_gate_hw(&clk_en_vi), + [RTD1625_CRT_CLK_EN_LVDS1] = &__clk_regmap_gate_hw(&clk_en_lvds1), + [RTD1625_CRT_CLK_EN_LVDS2] = &__clk_regmap_gate_hw(&clk_en_lvds2), + [RTD1625_CRT_CLK_EN_AUCPU] = &__clk_regmap_gate_hw(&clk_en_aucpu), + [RTD1625_CRT_CLK_EN_UR1] = &__clk_regmap_gate_hw(&clk_en_ur1), + [RTD1625_CRT_CLK_EN_UR2] = &__clk_regmap_gate_hw(&clk_en_ur2), + [RTD1625_CRT_CLK_EN_UR3] = &__clk_regmap_gate_hw(&clk_en_ur3), + [RTD1625_CRT_CLK_EN_UR4] = &__clk_regmap_gate_hw(&clk_en_ur4), + [RTD1625_CRT_CLK_EN_UR5] = &__clk_regmap_gate_hw(&clk_en_ur5), + [RTD1625_CRT_CLK_EN_UR6] = &__clk_regmap_gate_hw(&clk_en_ur6), + [RTD1625_CRT_CLK_EN_UR7] = &__clk_regmap_gate_hw(&clk_en_ur7), + [RTD1625_CRT_CLK_EN_UR8] = &__clk_regmap_gate_hw(&clk_en_ur8), + [RTD1625_CRT_CLK_EN_UR9] = &__clk_regmap_gate_hw(&clk_en_ur9), + [RTD1625_CRT_CLK_EN_UR_TOP] = &__clk_regmap_gate_hw(&clk_en_ur_top), + [RTD1625_CRT_CLK_EN_MISC_I2C_7] = &__clk_regmap_gate_hw(&clk_en_misc_i2c_7), + [RTD1625_CRT_CLK_EN_MISC_I2C_6] = &__clk_regmap_gate_hw(&clk_en_misc_i2c_6), + [RTD1625_CRT_CLK_EN_SPI0] = &__clk_regmap_gate_hw(&clk_en_spi0), + [RTD1625_CRT_CLK_EN_SPI1] = &__clk_regmap_gate_hw(&clk_en_spi1), + [RTD1625_CRT_CLK_EN_SPI2] = &__clk_regmap_gate_hw(&clk_en_spi2), + [RTD1625_CRT_CLK_EN_LSADC0] = &__clk_regmap_gate_hw(&clk_en_lsadc0), + [RTD1625_CRT_CLK_EN_LSADC1] = &__clk_regmap_gate_hw(&clk_en_lsadc1), + [RTD1625_CRT_CLK_EN_ISOMIS_DMA] = &__clk_regmap_gate_hw(&clk_en_isomis_dma), + [RTD1625_CRT_CLK_EN_DPTX] = &__clk_regmap_gate_hw(&clk_en_dptx), + [RTD1625_CRT_CLK_EN_NPU_MIPI_CSI] = &__clk_regmap_gate_hw(&clk_en_npu_mipi_csi), + [RTD1625_CRT_CLK_EN_EDPTX] = &__clk_regmap_gate_hw(&clk_en_edptx), + [RTD1625_CRT_CLK_GPU] = &__clk_regmap_mux_hw(&clk_gpu), + [RTD1625_CRT_CLK_VE1] = &__clk_regmap_mux_hw(&clk_ve1), + [RTD1625_CRT_CLK_VE2] = &__clk_regmap_mux_hw(&clk_ve2), + [RTD1625_CRT_CLK_VE4] = &__clk_regmap_mux_hw(&clk_ve4), + [RTD1625_CRT_PLL_VE1] = &__clk_pll_hw(&pll_ve1), + [RTD1625_CRT_PLL_DDSA] = &__clk_pll_hw(&pll_ddsa), + [RTD1625_CRT_PLL_BUS] = &__clk_pll_hw(&pll_bus), + [RTD1625_CRT_CLK_SYS] = &clk_sys.hw, + [RTD1625_CRT_PLL_DCSB] = &__clk_pll_hw(&pll_dcsb), + [RTD1625_CRT_CLK_SYSH] = &clk_sysh.hw, + [RTD1625_CRT_PLL_GPU] = &__clk_pll_hw(&pll_gpu), + [RTD1625_CRT_PLL_NPU] = &__clk_pll_hw(&pll_npu), + [RTD1625_CRT_PLL_VE2] = &__clk_pll_hw(&pll_ve2), + [RTD1625_CRT_PLL_HIFI] = &__clk_pll_hw(&pll_hifi), + [RTD1625_CRT_PLL_EMMC_REF] = &pll_emmc_ref.hw, + [RTD1625_CRT_PLL_EMMC] = &__clk_pll_mmc_hw(&pll_emmc), + [RTD1625_CRT_PLL_EMMC_VP0] = &pll_emmc.phase0_hw, + [RTD1625_CRT_PLL_EMMC_VP1] = &pll_emmc.phase1_hw, + [RTD1625_CRT_PLL_ACPU] = &__clk_pll_hw(&pll_acpu), + [RTD1625_CRT_CLK_NPU] = &clk_npu.hw, + [RTD1625_CRT_CLK_NPU_MIPI_CSI] = &clk_npu_mipi_csi.hw, + [RTD1625_CRT_CLK_MAX - 1] = NULL, + }, +}; + +static const struct rtk_clk_desc rtd1625_crt_desc = { + .clk_data = &rtd1625_crt_hw_data, + .clks = rtd1625_crt_regmap_clks, + .num_clks = ARRAY_SIZE(rtd1625_crt_regmap_clks), +}; + +static int rtd1625_crt_probe(struct platform_device *pdev) +{ + const struct rtk_clk_desc *desc; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + return rtk_clk_probe(pdev, desc, "crt_rst"); +} + +static const struct of_device_id rtd1625_crt_match[] = { + {.compatible = "realtek,rtd1625-crt-clk", .data = &rtd1625_crt_desc,}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtd1625_crt_match); + +static struct platform_driver rtd1625_crt_driver = { + .probe = rtd1625_crt_probe, + .driver = { + .name = "rtk-rtd1625-crt-clk", + .of_match_table = rtd1625_crt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init rtd1625_crt_init(void) +{ + return platform_driver_register(&rtd1625_crt_driver); +} +subsys_initcall(rtd1625_crt_init); + +MODULE_DESCRIPTION("Realtek RTD1625 CRT Clock Controller Driver"); +MODULE_AUTHOR("Cheng-Yu Lee <cylee12@realtek.com>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("REALTEK_CLK"); diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig index bb6dd856a64a..b122e6334508 100644 --- a/drivers/reset/realtek/Kconfig +++ b/drivers/reset/realtek/Kconfig @@ -6,3 +6,14 @@ config RESET_RTK_COMMON Realtek SoCs. It provides shared reset control operations (assert, deassert, status) and a registration helper function that other Realtek-specific reset drivers can use. + +config RESET_RTD1625 + tristate "RTD1625 Reset Controller" + depends on ARCH_REALTEK || COMPILE_TEST + select RESET_RTK_COMMON + select AUXILIARY_BUS + help + This enables the reset controller driver for Realtek RTD1625 SoC. + The driver controls reset lines for various peripherals including + PCIe, SATA, HDMI, display, video encoder/decoder, USB, SD, audio, + and other subsystems. diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile index b59a3f7f2453..65c29a12524d 100644 --- a/drivers/reset/realtek/Makefile +++ b/drivers/reset/realtek/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_RESET_RTK_COMMON) += common.o +obj-$(CONFIG_RESET_RTD1625) += reset-rtd1625-crt.o diff --git a/drivers/reset/realtek/reset-rtd1625-crt.c b/drivers/reset/realtek/reset-rtd1625-crt.c new file mode 100644 index 000000000000..9de0e9808f7c --- /dev/null +++ b/drivers/reset/realtek/reset-rtd1625-crt.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + */ + +#include <dt-bindings/reset/realtek,rtd1625.h> +#include <linux/auxiliary_bus.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/slab.h> +#include "common.h" + +#define RTD1625_CRT_RSTN_MAX 123 + +static const struct rtk_reset_desc rtd1625_crt_reset_descs[] = { + /* Bank 0: offset 0x0 */ + [RTD1625_CRT_RSTN_MISC] = { .ofs = 0x0, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_DIP] = { .ofs = 0x0, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_GSPI] = { .ofs = 0x0, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDS] = { .ofs = 0x0, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDS_REG] = { .ofs = 0x0, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDS_PHY] = { .ofs = 0x0, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_GPU2D] = { .ofs = 0x0, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_DC_PHY] = { .ofs = 0x0, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_DCPHY_CRT] = { .ofs = 0x0, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_LSADC] = { .ofs = 0x0, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_SE] = { .ofs = 0x0, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_DLA] = { .ofs = 0x0, .bit = 30, .write_en = 1 }, + /* Bank 1: offset 0x4 */ + [RTD1625_CRT_RSTN_JPEG] = { .ofs = 0x4, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_SD] = { .ofs = 0x4, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_SDIO] = { .ofs = 0x4, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCR_CNT] = { .ofs = 0x4, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_STITCH] = { .ofs = 0x4, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY] = { .ofs = 0x4, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0] = { .ofs = 0x4, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_CORE] = { .ofs = 0x4, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_POWER] = { .ofs = 0x4, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_NONSTICH] = { .ofs = 0x4, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY_MDIO] = { .ofs = 0x4, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE0_SGMII_MDIO] = { .ofs = 0x4, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_VO2] = { .ofs = 0x4, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_MISC_SC0] = { .ofs = 0x4, .bit = 30, .write_en = 1 }, + /* Bank 2: offset 0x8 */ + [RTD1625_CRT_RSTN_MD] = { .ofs = 0x8, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_LVDS1] = { .ofs = 0x8, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_LVDS2] = { .ofs = 0x8, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_MISC_SC1] = { .ofs = 0x8, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_3] = { .ofs = 0x8, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_FAN] = { .ofs = 0x8, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_TVE] = { .ofs = 0x8, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_AIO] = { .ofs = 0x8, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_VO] = { .ofs = 0x8, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_MIPI_CSI] = { .ofs = 0x8, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMIRX] = { .ofs = 0x8, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMIRX_WRAP] = { .ofs = 0x8, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMI] = { .ofs = 0x8, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_DISP] = { .ofs = 0x8, .bit = 30, .write_en = 1 }, + /* Bank 3: offset 0xc */ + [RTD1625_CRT_RSTN_SATA_PHY_POW1] = { .ofs = 0xc, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_PHY_POW0] = { .ofs = 0xc, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO1] = { .ofs = 0xc, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO0] = { .ofs = 0xc, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_WRAP] = { .ofs = 0xc, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P1] = { .ofs = 0xc, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P0] = { .ofs = 0xc, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_COM] = { .ofs = 0xc, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_STITCH] = { .ofs = 0xc, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY] = { .ofs = 0xc, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1] = { .ofs = 0xc, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_CORE] = { .ofs = 0xc, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_POWER] = { .ofs = 0xc, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_NONSTICH] = { .ofs = 0xc, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY_MDIO] = { .ofs = 0xc, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_HDMITOP] = { .ofs = 0xc, .bit = 30, .write_en = 1 }, + /* Bank 4: offset 0x68 */ + [RTD1625_CRT_RSTN_I2C_4] = { .ofs = 0x68, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_5] = { .ofs = 0x68, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_TSIO] = { .ofs = 0x68, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_VI] = { .ofs = 0x68, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_EDP] = { .ofs = 0x68, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1_MMU] = { .ofs = 0x68, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1_MMU_FUNC] = { .ofs = 0x68, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_HSE_MMU] = { .ofs = 0x68, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_HSE_MMU_FUNC] = { .ofs = 0x68, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDLM2M] = { .ofs = 0x68, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_ISO_GSPI] = { .ofs = 0x68, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_SOFT_NPU] = { .ofs = 0x68, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_SPI2EMMC] = { .ofs = 0x68, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_EARC] = { .ofs = 0x68, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1] = { .ofs = 0x68, .bit = 30, .write_en = 1 }, + /* Bank 5: offset 0x90 */ + [RTD1625_CRT_RSTN_PCIE2_STITCH] = { .ofs = 0x90, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY] = { .ofs = 0x90, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2] = { .ofs = 0x90, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_CORE] = { .ofs = 0x90, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_POWER] = { .ofs = 0x90, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_NONSTICH] = { .ofs = 0x90, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY_MDIO] = { .ofs = 0x90, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_DCPHY_UMCTL2] = { .ofs = 0x90, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_MIPI_DSI] = { .ofs = 0x90, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_HIFM] = { .ofs = 0x90, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_NSRAM] = { .ofs = 0x90, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_AUCPU0_REG] = { .ofs = 0x90, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDL_GENPW] = { .ofs = 0x90, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDL_CHIP] = { .ofs = 0x90, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_MDL_IP] = { .ofs = 0x90, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_TEST_MUX] = { .ofs = 0x90, .bit = 30, .write_en = 1 }, + /* Bank 6: offset 0xb8 */ + [RTD1625_CRT_RSTN_ISO_BIST] = { .ofs = 0xb8, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_MAIN_BIST] = { .ofs = 0xb8, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_MAIN2_BIST] = { .ofs = 0xb8, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE1_BIST] = { .ofs = 0xb8, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE2_BIST] = { .ofs = 0xb8, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_DCPHY_BIST] = { .ofs = 0xb8, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_GPU_BIST] = { .ofs = 0xb8, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_DISP_BIST] = { .ofs = 0xb8, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_NPU_BIST] = { .ofs = 0xb8, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_CAS_BIST] = { .ofs = 0xb8, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_VE4_BIST] = { .ofs = 0xb8, .bit = 20, .write_en = 1 }, + /* Bank 7: offset 0x454 (DUMMY0, no write_en) */ + [RTD1625_CRT_RSTN_EMMC] = { .ofs = 0x454, .bit = 0 }, + /* Bank 8: offset 0x458 (DUMMY1, no write_en) */ + [RTD1625_CRT_RSTN_GPU] = { .ofs = 0x458, .bit = 0 }, + /* Bank 9: offset 0x464 (DUMMY4, no write_en) */ + [RTD1625_CRT_RSTN_VE2] = { .ofs = 0x464, .bit = 0 }, + /* Bank 10: offset 0x880 */ + [RTD1625_CRT_RSTN_UR1] = { .ofs = 0x880, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR2] = { .ofs = 0x880, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR3] = { .ofs = 0x880, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR4] = { .ofs = 0x880, .bit = 6, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR5] = { .ofs = 0x880, .bit = 8, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR6] = { .ofs = 0x880, .bit = 10, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR7] = { .ofs = 0x880, .bit = 12, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR8] = { .ofs = 0x880, .bit = 14, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR9] = { .ofs = 0x880, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_UR_TOP] = { .ofs = 0x880, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_7] = { .ofs = 0x880, .bit = 28, .write_en = 1 }, + [RTD1625_CRT_RSTN_I2C_6] = { .ofs = 0x880, .bit = 30, .write_en = 1 }, + /* Bank 11: offset 0x890 */ + [RTD1625_CRT_RSTN_SPI0] = { .ofs = 0x890, .bit = 0, .write_en = 1 }, + [RTD1625_CRT_RSTN_SPI1] = { .ofs = 0x890, .bit = 2, .write_en = 1 }, + [RTD1625_CRT_RSTN_SPI2] = { .ofs = 0x890, .bit = 4, .write_en = 1 }, + [RTD1625_CRT_RSTN_LSADC0] = { .ofs = 0x890, .bit = 16, .write_en = 1 }, + [RTD1625_CRT_RSTN_LSADC1] = { .ofs = 0x890, .bit = 18, .write_en = 1 }, + [RTD1625_CRT_RSTN_ISOMIS_DMA] = { .ofs = 0x890, .bit = 20, .write_en = 1 }, + [RTD1625_CRT_RSTN_AUDIO_ADC] = { .ofs = 0x890, .bit = 22, .write_en = 1 }, + [RTD1625_CRT_RSTN_DPTX] = { .ofs = 0x890, .bit = 24, .write_en = 1 }, + [RTD1625_CRT_RSTN_AUCPU1_REG] = { .ofs = 0x890, .bit = 26, .write_en = 1 }, + [RTD1625_CRT_RSTN_EDPTX] = { .ofs = 0x890, .bit = 28, .write_en = 1 }, +}; + +static int rtd1625_crt_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + struct rtk_reset_data *data; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->descs = rtd1625_crt_reset_descs; + data->rcdev.nr_resets = RTD1625_CRT_RSTN_MAX; + data->rcdev.owner = THIS_MODULE; + + return rtk_reset_controller_add(dev, data); +} + +static const struct auxiliary_device_id rtd1625_crt_reset_ids[] = { + { .name = "clk_rtk.crt_rst" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, rtd1625_crt_reset_ids); + +static struct auxiliary_driver rtd1625_crt_driver = { + .probe = rtd1625_crt_reset_probe, + .id_table = rtd1625_crt_reset_ids, + .driver = { + .name = "rtd1625-crt-reset", + }, +}; +module_auxiliary_driver(rtd1625_crt_driver); + +MODULE_DESCRIPTION("Realtek RTD1625 CRT Reset Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("REALTEK_RESET"); -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 09/10] clk: realtek: Add RTD1625-ISO clock controller driver 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin ` (7 preceding siblings ...) 2026-06-10 8:08 ` [PATCH v8 08/10] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 10/10] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin 9 siblings, 0 replies; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin From: Cheng-Yu Lee <cylee12@realtek.com> Add support for the ISO (Isolation) domain clock controller on the Realtek RTD1625 SoC. This controller manages clocks in the always-on power domain, ensuring essential services remain functional even when the main system power is gated. Since the reset controller shares the same register space with the ISO clock controller, it is instantiated as an auxiliary device by the core clock driver. This patch also includes the corresponding auxiliary reset driver to handle the ISO domain resets. Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - Remove the trailing NULL element ([RTD1625_XX_CLK_MAX] = NULL) from the clk_hw_onecell_data arrays. - Add MODULE_DEVICE_TABLE(of, ...) for the tristate config. - Add `.suppress_bind_attrs = true`, to avoid handling pointer problem, cause clock should not allow to manually disable by users. - Fix a typo. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-rtd1625-iso.c | 151 ++++++++++++++++++++++ drivers/reset/realtek/Makefile | 2 +- drivers/reset/realtek/reset-rtd1625-iso.c | 99 ++++++++++++++ 4 files changed, 252 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/realtek/clk-rtd1625-iso.c create mode 100644 drivers/reset/realtek/reset-rtd1625-iso.c diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index f4a62be092d2..7627eb67ab66 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -10,3 +10,4 @@ clk-rtk-y += freq_table.o clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) += clk-pll-mmc.o obj-$(CONFIG_CLK_RTD1625) += clk-rtd1625-crt.o +obj-$(CONFIG_CLK_RTD1625) += clk-rtd1625-iso.o diff --git a/drivers/clk/realtek/clk-rtd1625-iso.c b/drivers/clk/realtek/clk-rtd1625-iso.c new file mode 100644 index 000000000000..52c4a4304284 --- /dev/null +++ b/drivers/clk/realtek/clk-rtd1625-iso.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee <cylee12@realtek.com> + */ + +#include <dt-bindings/clock/realtek,rtd1625-clk.h> +#include <linux/array_size.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "clk-regmap-gate.h" + +#define RTD1625_ISO_CLK_MAX 19 +#define RTD1625_ISO_RSTN_MAX 29 +#define RTD1625_ISO_S_CLK_MAX 5 +#define RTD1625_ISO_S_RSTN_MAX 5 + +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_p4, 0, 0x4, 0, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_p3, 0, 0x4, 1, 0); +static CLK_REGMAP_GATE(clk_en_misc_cec0, "clk_en_misc", 0, 0x4, 2, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbusrx_sys, 0, 0x4, 3, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbustx_sys, 0, 0x4, 4, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbus_sys, 0, 0x4, 5, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbus_osc, 0, 0x4, 6, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_i2c0, 0, 0x4, 9, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_i2c1, 0, 0x4, 10, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_etn_250m, 0, 0x4, 11, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_etn_sys, 0, 0x4, 12, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_drd, 0, 0x4, 13, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_host, 0, 0x4, 14, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_u3_host, 0, 0x4, 15, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb, 0, 0x4, 16, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_vtc, 0, 0x4, 17, 0); +static CLK_REGMAP_GATE(clk_en_misc_vfd, "clk_en_misc", 0, 0x4, 18, 0); + +static struct clk_regmap * const rtd1625_clk_regmap_list[] = { + &clk_en_usb_p4.clkr, + &clk_en_usb_p3.clkr, + &clk_en_misc_cec0.clkr, + &clk_en_cbusrx_sys.clkr, + &clk_en_cbustx_sys.clkr, + &clk_en_cbus_sys.clkr, + &clk_en_cbus_osc.clkr, + &clk_en_i2c0.clkr, + &clk_en_i2c1.clkr, + &clk_en_etn_250m.clkr, + &clk_en_etn_sys.clkr, + &clk_en_usb_drd.clkr, + &clk_en_usb_host.clkr, + &clk_en_usb_u3_host.clkr, + &clk_en_usb.clkr, + &clk_en_vtc.clkr, + &clk_en_misc_vfd.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_iso_clk_data = { + .num = RTD1625_ISO_CLK_MAX, + .hws = { + [RTD1625_ISO_CLK_EN_USB_P4] = &__clk_regmap_gate_hw(&clk_en_usb_p4), + [RTD1625_ISO_CLK_EN_USB_P3] = &__clk_regmap_gate_hw(&clk_en_usb_p3), + [RTD1625_ISO_CLK_EN_MISC_CEC0] = &__clk_regmap_gate_hw(&clk_en_misc_cec0), + [RTD1625_ISO_CLK_EN_CBUSRX_SYS] = &__clk_regmap_gate_hw(&clk_en_cbusrx_sys), + [RTD1625_ISO_CLK_EN_CBUSTX_SYS] = &__clk_regmap_gate_hw(&clk_en_cbustx_sys), + [RTD1625_ISO_CLK_EN_CBUS_SYS] = &__clk_regmap_gate_hw(&clk_en_cbus_sys), + [RTD1625_ISO_CLK_EN_CBUS_OSC] = &__clk_regmap_gate_hw(&clk_en_cbus_osc), + [RTD1625_ISO_CLK_EN_I2C0] = &__clk_regmap_gate_hw(&clk_en_i2c0), + [RTD1625_ISO_CLK_EN_I2C1] = &__clk_regmap_gate_hw(&clk_en_i2c1), + [RTD1625_ISO_CLK_EN_ETN_250M] = &__clk_regmap_gate_hw(&clk_en_etn_250m), + [RTD1625_ISO_CLK_EN_ETN_SYS] = &__clk_regmap_gate_hw(&clk_en_etn_sys), + [RTD1625_ISO_CLK_EN_USB_DRD] = &__clk_regmap_gate_hw(&clk_en_usb_drd), + [RTD1625_ISO_CLK_EN_USB_HOST] = &__clk_regmap_gate_hw(&clk_en_usb_host), + [RTD1625_ISO_CLK_EN_USB_U3_HOST] = &__clk_regmap_gate_hw(&clk_en_usb_u3_host), + [RTD1625_ISO_CLK_EN_USB] = &__clk_regmap_gate_hw(&clk_en_usb), + [RTD1625_ISO_CLK_EN_VTC] = &__clk_regmap_gate_hw(&clk_en_vtc), + [RTD1625_ISO_CLK_EN_MISC_VFD] = &__clk_regmap_gate_hw(&clk_en_misc_vfd), + }, +}; + +static const struct rtk_clk_desc rtd1625_iso_desc = { + .clk_data = &rtd1625_iso_clk_data, + .clks = rtd1625_clk_regmap_list, + .num_clks = ARRAY_SIZE(rtd1625_clk_regmap_list), +}; + +static CLK_REGMAP_GATE_NO_PARENT(clk_en_irda, 0, 0x4, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ur10, 0, 0x4, 8, 1); + +static struct clk_regmap * const rtd1625_iso_s_clk_regmap_list[] = { + &clk_en_irda.clkr, + &clk_en_ur10.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_iso_s_clk_data = { + .num = RTD1625_ISO_S_CLK_MAX, + .hws = { + [RTD1625_ISO_S_CLK_EN_IRDA] = &__clk_regmap_gate_hw(&clk_en_irda), + [RTD1625_ISO_S_CLK_EN_UR10] = &__clk_regmap_gate_hw(&clk_en_ur10), + }, +}; + +static const struct rtk_clk_desc rtd1625_iso_s_desc = { + .clk_data = &rtd1625_iso_s_clk_data, + .clks = rtd1625_iso_s_clk_regmap_list, + .num_clks = ARRAY_SIZE(rtd1625_iso_s_clk_regmap_list), +}; + +static int rtd1625_iso_probe(struct platform_device *pdev) +{ + const struct rtk_clk_desc *desc; + const char *aux_name = NULL; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + if (of_device_is_compatible(pdev->dev.of_node, "realtek,rtd1625-iso-clk")) + aux_name = "iso_rst"; + else + aux_name = "iso_s_rst"; + + return rtk_clk_probe(pdev, desc, aux_name); +} + +static const struct of_device_id rtd1625_iso_match[] = { + {.compatible = "realtek,rtd1625-iso-clk", .data = &rtd1625_iso_desc}, + {.compatible = "realtek,rtd1625-iso-s-clk", .data = &rtd1625_iso_s_desc}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtd1625_iso_match); + +static struct platform_driver rtd1625_iso_driver = { + .probe = rtd1625_iso_probe, + .driver = { + .name = "rtk-rtd1625-iso-clk", + .of_match_table = rtd1625_iso_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init rtd1625_iso_init(void) +{ + return platform_driver_register(&rtd1625_iso_driver); +} +subsys_initcall(rtd1625_iso_init); + +MODULE_DESCRIPTION("Realtek RTD1625 ISO Clock Controller Driver"); +MODULE_AUTHOR("Cheng-Yu Lee <cylee12@realtek.com>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("REALTEK_CLK"); diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile index 65c29a12524d..e46a3831b582 100644 --- a/drivers/reset/realtek/Makefile +++ b/drivers/reset/realtek/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_RESET_RTK_COMMON) += common.o -obj-$(CONFIG_RESET_RTD1625) += reset-rtd1625-crt.o +obj-$(CONFIG_RESET_RTD1625) += reset-rtd1625-crt.o reset-rtd1625-iso.o diff --git a/drivers/reset/realtek/reset-rtd1625-iso.c b/drivers/reset/realtek/reset-rtd1625-iso.c new file mode 100644 index 000000000000..08a5d1e36fbc --- /dev/null +++ b/drivers/reset/realtek/reset-rtd1625-iso.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + */ + +#include <dt-bindings/reset/realtek,rtd1625.h> +#include <linux/auxiliary_bus.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/of.h> +#include <linux/slab.h> +#include "common.h" + +#define RTD1625_ISO_RSTN_MAX 29 +#define RTD1625_ISO_S_RSTN_MAX 5 + +static const struct rtk_reset_desc rtd1625_iso_reset_descs[] = { + [RTD1625_ISO_RSTN_VFD] = { .ofs = 0x88, .bit = 0 }, + [RTD1625_ISO_RSTN_CEC0] = { .ofs = 0x88, .bit = 2 }, + [RTD1625_ISO_RSTN_CEC1] = { .ofs = 0x88, .bit = 3 }, + [RTD1625_ISO_RSTN_CBUSTX] = { .ofs = 0x88, .bit = 5 }, + [RTD1625_ISO_RSTN_CBUSRX] = { .ofs = 0x88, .bit = 6 }, + [RTD1625_ISO_RSTN_USB3_PHY2_XTAL_POW] = { .ofs = 0x88, .bit = 7 }, + [RTD1625_ISO_RSTN_UR0] = { .ofs = 0x88, .bit = 8 }, + [RTD1625_ISO_RSTN_GMAC] = { .ofs = 0x88, .bit = 9 }, + [RTD1625_ISO_RSTN_GPHY] = { .ofs = 0x88, .bit = 10 }, + [RTD1625_ISO_RSTN_I2C_0] = { .ofs = 0x88, .bit = 11 }, + [RTD1625_ISO_RSTN_I2C_1] = { .ofs = 0x88, .bit = 12 }, + [RTD1625_ISO_RSTN_CBUS] = { .ofs = 0x88, .bit = 13 }, + [RTD1625_ISO_RSTN_USB_DRD] = { .ofs = 0x88, .bit = 14 }, + [RTD1625_ISO_RSTN_USB_HOST] = { .ofs = 0x88, .bit = 15 }, + [RTD1625_ISO_RSTN_USB_PHY_0] = { .ofs = 0x88, .bit = 16 }, + [RTD1625_ISO_RSTN_USB_PHY_1] = { .ofs = 0x88, .bit = 17 }, + [RTD1625_ISO_RSTN_USB_PHY_2] = { .ofs = 0x88, .bit = 18 }, + [RTD1625_ISO_RSTN_USB] = { .ofs = 0x88, .bit = 19 }, + [RTD1625_ISO_RSTN_TYPE_C] = { .ofs = 0x88, .bit = 20 }, + [RTD1625_ISO_RSTN_USB_U3_HOST] = { .ofs = 0x88, .bit = 21 }, + [RTD1625_ISO_RSTN_USB3_PHY0_POW] = { .ofs = 0x88, .bit = 22 }, + [RTD1625_ISO_RSTN_USB3_P0_MDIO] = { .ofs = 0x88, .bit = 23 }, + [RTD1625_ISO_RSTN_USB3_PHY1_POW] = { .ofs = 0x88, .bit = 24 }, + [RTD1625_ISO_RSTN_USB3_P1_MDIO] = { .ofs = 0x88, .bit = 25 }, + [RTD1625_ISO_RSTN_VTC] = { .ofs = 0x88, .bit = 26 }, + [RTD1625_ISO_RSTN_USB3_PHY2_POW] = { .ofs = 0x88, .bit = 27 }, + [RTD1625_ISO_RSTN_USB3_P2_MDIO] = { .ofs = 0x88, .bit = 28 }, + [RTD1625_ISO_RSTN_USB_PHY_3] = { .ofs = 0x88, .bit = 29 }, + [RTD1625_ISO_RSTN_USB_PHY_4] = { .ofs = 0x88, .bit = 30 }, +}; + +static const struct rtk_reset_desc rtd1625_iso_s_reset_descs[] = { + [RTD1625_ISO_S_RSTN_ISOM_MIS] = { .ofs = 0x310, .bit = 0, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_GPIOM] = { .ofs = 0x310, .bit = 2, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_TIMER7] = { .ofs = 0x310, .bit = 4, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_IRDA] = { .ofs = 0x310, .bit = 6, .write_en = 1 }, + [RTD1625_ISO_S_RSTN_UR10] = { .ofs = 0x310, .bit = 8, .write_en = 1 }, +}; + +static int rtd1625_iso_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + struct device *parent = dev->parent; + struct rtk_reset_data *data; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + if (of_device_is_compatible(parent->of_node, "realtek,rtd1625-iso-s-clk")) { + data->descs = rtd1625_iso_s_reset_descs; + data->rcdev.nr_resets = RTD1625_ISO_S_RSTN_MAX; + } else { + data->descs = rtd1625_iso_reset_descs; + data->rcdev.nr_resets = RTD1625_ISO_RSTN_MAX; + } + + data->rcdev.owner = THIS_MODULE; + + return rtk_reset_controller_add(dev, data); +} + +static const struct auxiliary_device_id rtd1625_iso_reset_ids[] = { + { .name = "clk_rtk.iso_rst" }, + { .name = "clk_rtk.iso_s_rst" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, rtd1625_iso_reset_ids); + +static struct auxiliary_driver rtd1625_iso_driver = { + .probe = rtd1625_iso_reset_probe, + .id_table = rtd1625_iso_reset_ids, + .driver = { + .name = "rtd1625-iso-reset", + }, +}; +module_auxiliary_driver(rtd1625_iso_driver); + +MODULE_DESCRIPTION("Realtek RTD1625 ISO Reset Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("REALTEK_RESET"); -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 10/10] arm64: dts: realtek: Add clock support for RTD1625 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin ` (8 preceding siblings ...) 2026-06-10 8:08 ` [PATCH v8 09/10] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin @ 2026-06-10 8:08 ` Yu-Chun Lin 9 siblings, 0 replies; 15+ messages in thread From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw) To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12, afaerber, jyanchou Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel, linux-realtek-soc, james.tai, cy.huang, stanley_chang, eleanor.lin Add the clock controller nodes and osc27m fixed clock for the Realtek RTD1625 SoC. Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> --- Changes in v8: - Sort device nodes by unit address. --- arch/arm64/boot/dts/realtek/kent.dtsi | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi index ae006ce24420..69f28cb35585 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -26,6 +26,15 @@ timer { <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + clocks { + osc27m: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "osc27m"; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -141,6 +150,22 @@ rbus: bus@98000000 { #address-cells = <1>; #size-cells = <1>; + cc: clock-controller@0 { + compatible = "realtek,rtd1625-crt-clk"; + reg = <0x0 0x900>; + clocks = <&osc27m>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ic: clock-controller@7088 { + compatible = "realtek,rtd1625-iso-clk"; + reg = <0x7088 0x8>; + clocks = <&osc27m>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@7800 { compatible = "snps,dw-apb-uart"; reg = <0x7800 0x100>; @@ -150,6 +175,14 @@ uart0: serial@7800 { reg-shift = <2>; status = "disabled"; }; + + iso_s_cc: clock-controller@146310 { + compatible = "realtek,rtd1625-iso-s-clk"; + reg = <0x146310 0x8>; + clocks = <&osc27m>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; gic: interrupt-controller@ff100000 { -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2026-06-10 8:19 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-10 8:08 [PATCH v8 00/10] clk: realtek: Add RTD1625 clock support Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 02/10] reset: Add Realtek basic reset support Yu-Chun Lin 2026-06-10 8:18 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 03/10] clk: realtek: Introduce a common probe() Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 04/10] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin 2026-06-10 8:18 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 05/10] clk: realtek: Add support for gate clock Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 06/10] clk: realtek: Add support for mux clock Yu-Chun Lin 2026-06-10 8:19 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 07/10] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin 2026-06-10 8:19 ` sashiko-bot 2026-06-10 8:08 ` [PATCH v8 08/10] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 09/10] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin 2026-06-10 8:08 ` [PATCH v8 10/10] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin
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