Re: [PATCH 1/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine

[Chen Pei <cp0613@linux.alibaba.com>]

On Tue, 9 Jun 2026 13:41:01 +0100, Jonathan Cameron <jic23@kernel.org> wrote:

Hi Jonathan,

Thanks for the review.

> > @@ -1426,6 +1446,15 @@ static void virt_machine_done(Notifier *notifier, void *data)
> >                                       machine_done);
> >      MachineState *machine = MACHINE(s);
> >      hwaddr start_addr = s->memmap[VIRT_DRAM].base;
> > +
> > +    if (s->bus) {
> 
> There is a guard against !s->bus inside the function so you should be
> able to do this unconditionally.

You're right. Will drop the outer if (s->bus) guard in v2.

> > @@ -64,6 +65,8 @@ struct RISCVVirtState {
> >      struct GPEXHost *gpex_host;
> >      OnOffAuto iommu_sys;
> >      uint16_t pci_iommu_bdf;
> > +    CXLState cxl_devices_state;
> > +    PCIBus *bus;
> 
> That's a very vague bit of naming.  I'd make it explicit what PCIBus this is.

Agreed. Will rename it to `pci_bus` in v2 to make it clear this is
the root bus of the PCIe host bridge (PCI0).

Best,
Pei