From: Jonathan Cameron <jic23@kernel.org>
To: Shrihari E S <shrihari.s@samsung.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
qemu-devel@nongnu.org, cpgs@samsung.com, arun.george@samsung.com,
vikash.k5@samsung.com, s.neeraj@samsung.com,
dongjoo.seo1@samsung.com, dave@stgolabs.net,
gost.dev@samsung.com
Subject: Re: [RFC 1/8] hw/pci: Refactor flitmode from PCIESlot to PCIEPort.
Date: Tue, 16 Jun 2026 14:27:30 +0100 [thread overview]
Message-ID: <20260616142730.7fb0a465@jic23-huawei> (raw)
In-Reply-To: <20260609105836.3702787-2-shrihari.s@samsung.com>
On Tue, 9 Jun 2026 16:28:29 +0530
Shrihari E S <shrihari.s@samsung.com> wrote:
> Move the 'flitmode' property from PCIESlot to PCIEPort. This change
> allows all the derived ports (PCIe ports or CXL ports) to use this
> property.
>
> This is a structural refactor only. There is no functional change in
> existing behavior.
>
> Note: This property was added from Davidlohr's BI patch series[1].
>
> [1]: https://lore.kernel.org/all/20251103195209.1319917-2-dave@stgolabs.net/
>
> Signed-off-by: Shrihari E S <shrihari.s@samsung.com>
This seems fine to me other than one small thing below.
Given the main changes are in PCIe code though it'll need review from
appropriate maintainers.
> diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
> index 0ee18ef5c3..df69c5200f 100644
> --- a/hw/pci-bridge/cxl_root_port.c
> +++ b/hw/pci-bridge/cxl_root_port.c
> static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> index 1de0b1e4fd..d452199d85 100644
> --- a/hw/pci/pcie.c
> +++ b/hw/pci/pcie.c
> @@ -217,7 +217,7 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
> /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */
> }
>
> - pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->flitmode);
> + pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->parent_obj.flitmode);
I think we should use a cast to the parent object type rather than going directly
into s->parent_obj. PCIE_PORT(s)->flitmode.
> }
next prev parent reply other threads:[~2026-06-16 13:27 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20260609104453epcas5p327a974e978790e693c0660f27f9b43ef@epcas5p3.samsung.com>
2026-06-09 10:58 ` [RFC 0/8] pci: cxl: Add enumeration support for Unordered I/O (UIO) feature Shrihari E S
2026-06-09 10:58 ` [RFC 1/8] hw/pci: Refactor flitmode from PCIESlot to PCIEPort Shrihari E S
2026-06-16 13:27 ` Jonathan Cameron [this message]
2026-06-24 14:01 ` Shrihari E S
2026-06-09 10:58 ` [RFC 2/8] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port Shrihari E S
2026-06-09 10:58 ` [RFC 3/8] hw/pci: Add SVC capability and UIO properties to PCIe ports Shrihari E S
2026-06-16 17:20 ` Jonathan Cameron
2026-06-24 14:18 ` Shrihari E S
2026-06-09 10:58 ` [RFC 4/8] hw/cxl: Add Streamlined Virtual Channel (SVC) property to CXL ports Shrihari E S
2026-06-16 17:21 ` Jonathan Cameron
2026-06-24 14:21 ` Shrihari E S
2026-06-09 10:58 ` [RFC 5/8] hw/cxl: Wire UIO capability into HDM decoder registers Shrihari E S
2026-06-16 17:40 ` Jonathan Cameron
2026-06-24 14:47 ` Shrihari E S
2026-06-17 15:45 ` Junjie Cao
2026-06-24 15:04 ` Shrihari E S
2026-06-09 10:58 ` [RFC 6/8] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability Shrihari E S
2026-06-16 18:46 ` Jonathan Cameron
2026-06-24 15:00 ` Shrihari E S
2026-06-17 15:45 ` Junjie Cao
2026-06-24 15:09 ` Shrihari E S
2026-06-09 10:58 ` [RFC 7/8] hw/pci: hw/cxl: Wire SVC initialization into port realize functions Shrihari E S
2026-06-17 15:45 ` Junjie Cao
2026-06-24 15:18 ` Shrihari E S
2026-06-09 10:58 ` [RFC 8/8] cxl: Add documentation for UIO-enabled CXL devices Shrihari E S
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