Re: [RFC 5/8] hw/cxl: Wire UIO capability into HDM decoder registers

[Shrihari E S <shrihari.s@samsung.com>]

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On 17/06/26 11:45PM, Junjie Cao wrote:
>Hi Shrihari,
>
>On Tue,  9 Jun 2026 16:28:33 +0530, Shrihari E S wrote:
>> +    ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO,
>> +                     (type == CXL2_TYPE3_DEVICE || CXL2_UPSTREAM_PORT) && uio);
>>      ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
>> -                     UIO_DECODER_COUNT, 0);
>> +                     UIO_DECODER_COUNT,
>> +                     (type == CXL2_TYPE3_DEVICE || CXL2_UPSTREAM_PORT) && uio ?
>> +                     decoder_count : 0);
>
>CXL2_UPSTREAM_PORT is an enum constant with a non-zero value, so
>"|| CXL2_UPSTREAM_PORT" is always true and the type check collapses
>to just "uio" -- every type that reaches hdm_init_common() with
>uio=true gets the UIO bit set.  Presumably the intent was:
>
>    (type == CXL2_TYPE3_DEVICE || type == CXL2_UPSTREAM_PORT) && uio
>
>I haven't proposed which types should be in that set -- patch 7 sets
>crp->uio_capable on the cxl-rp, so a root port may well be intended
>here too.  Either way the current expression isn't gating on type.
>The same applies to the UIO_DECODER_COUNT line just below.
>
>Many thanks,
>Junjie

Hi Junjie,

   Thanks for pointing out. Will rectify it in the next version of the patch.

Thanks,

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