From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Subject: [PULL 07/48] system/memory: Constify various MemoryRegionCache arguments
Date: Thu, 18 Jun 2026 14:27:44 +0200 [thread overview]
Message-ID: <20260618122825.90331-8-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260618122825.90331-1-philmd@oss.qualcomm.com>
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Mark the MemoryRegionCache structure const when it is only
accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260616020359.18627-7-philmd@oss.qualcomm.com>
---
include/system/memory_cached.h | 18 +++++++++---------
include/system/memory_ldst_cached.h.inc | 15 +++++++++------
system/physmem.c | 10 +++++-----
3 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/include/system/memory_cached.h b/include/system/memory_cached.h
index 760ecb38c19..09d46821bec 100644
--- a/include/system/memory_cached.h
+++ b/include/system/memory_cached.h
@@ -51,12 +51,12 @@ struct MemoryRegionCache {
#define SUFFIX _cached_slow
#define ARG1 cache
-#define ARG1_DECL MemoryRegionCache *cache
+#define ARG1_DECL const MemoryRegionCache *cache
#include "system/memory_ldst.h.inc"
/* Inline fast path for direct RAM access. */
static inline
-uint8_t address_space_ldub_cached(MemoryRegionCache *cache, hwaddr addr,
+uint8_t address_space_ldub_cached(const MemoryRegionCache *cache, hwaddr addr,
MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len);
@@ -68,7 +68,7 @@ uint8_t address_space_ldub_cached(MemoryRegionCache *cache, hwaddr addr,
}
static inline
-void address_space_stb_cached(MemoryRegionCache *cache,
+void address_space_stb_cached(const MemoryRegionCache *cache,
hwaddr addr, uint8_t val,
MemTxAttrs attrs, MemTxResult *result)
{
@@ -93,7 +93,7 @@ void address_space_stb_cached(MemoryRegionCache *cache,
#define SUFFIX _cached
#define ARG1 cache
-#define ARG1_DECL MemoryRegionCache *cache
+#define ARG1_DECL const MemoryRegionCache *cache
#include "system/memory_ldst_phys.h.inc"
/**
@@ -145,7 +145,7 @@ static inline void address_space_cache_init_empty(MemoryRegionCache *cache)
* address that was passed to @address_space_cache_init.
* @access_len: The number of bytes that were written starting at @addr.
*/
-void address_space_cache_invalidate(MemoryRegionCache *cache,
+void address_space_cache_invalidate(const MemoryRegionCache *cache,
hwaddr addr,
hwaddr access_len);
@@ -160,9 +160,9 @@ void address_space_cache_destroy(MemoryRegionCache *cache);
* Internal functions, part of the implementation of address_space_read_cached
* and address_space_write_cached.
*/
-MemTxResult address_space_read_cached_slow(MemoryRegionCache *cache,
+MemTxResult address_space_read_cached_slow(const MemoryRegionCache *cache,
hwaddr addr, void *buf, hwaddr len);
-MemTxResult address_space_write_cached_slow(MemoryRegionCache *cache,
+MemTxResult address_space_write_cached_slow(const MemoryRegionCache *cache,
hwaddr addr, const void *buf,
hwaddr len);
@@ -175,7 +175,7 @@ MemTxResult address_space_write_cached_slow(MemoryRegionCache *cache,
* @len: length of the data transferred
*/
static inline MemTxResult
-address_space_read_cached(MemoryRegionCache *cache, hwaddr addr,
+address_space_read_cached(const MemoryRegionCache *cache, hwaddr addr,
void *buf, hwaddr len)
{
assert(addr < cache->len && len <= cache->len - addr);
@@ -197,7 +197,7 @@ address_space_read_cached(MemoryRegionCache *cache, hwaddr addr,
* @len: length of the data transferred
*/
static inline MemTxResult
-address_space_write_cached(MemoryRegionCache *cache, hwaddr addr,
+address_space_write_cached(const MemoryRegionCache *cache, hwaddr addr,
const void *buf, hwaddr len)
{
assert(addr < cache->len && len <= cache->len - addr);
diff --git a/include/system/memory_ldst_cached.h.inc b/include/system/memory_ldst_cached.h.inc
index d7834f852c4..b4c696bff1f 100644
--- a/include/system/memory_ldst_cached.h.inc
+++ b/include/system/memory_ldst_cached.h.inc
@@ -24,7 +24,8 @@
#define LD_P(size) \
glue(glue(ld, size), glue(ENDIANNESS, _p))
-static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
+static inline
+uint16_t ADDRESS_SPACE_LD_CACHED(uw)(const MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
@@ -36,7 +37,8 @@ static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
}
}
-static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
+static inline
+uint32_t ADDRESS_SPACE_LD_CACHED(l)(const MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 4 <= cache->len - addr);
@@ -48,7 +50,8 @@ static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
}
}
-static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
+static inline
+uint64_t ADDRESS_SPACE_LD_CACHED(q)(const MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 8 <= cache->len - addr);
@@ -71,7 +74,7 @@ static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
#define ST_P(size) \
glue(glue(st, size), glue(ENDIANNESS, _p))
-static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
+static inline void ADDRESS_SPACE_ST_CACHED(w)(const MemoryRegionCache *cache,
hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
@@ -82,7 +85,7 @@ static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
}
}
-static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
+static inline void ADDRESS_SPACE_ST_CACHED(l)(const MemoryRegionCache *cache,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 4 <= cache->len - addr);
@@ -93,7 +96,7 @@ static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
}
}
-static inline void ADDRESS_SPACE_ST_CACHED(q)(MemoryRegionCache *cache,
+static inline void ADDRESS_SPACE_ST_CACHED(q)(const MemoryRegionCache *cache,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 8 <= cache->len - addr);
diff --git a/system/physmem.c b/system/physmem.c
index 7ea65395863..9b3f461b123 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -3878,7 +3878,7 @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
return l;
}
-void address_space_cache_invalidate(MemoryRegionCache *cache,
+void address_space_cache_invalidate(const MemoryRegionCache *cache,
hwaddr addr,
hwaddr access_len)
{
@@ -3909,7 +3909,7 @@ void address_space_cache_destroy(MemoryRegionCache *cache)
* address_space_cache_init.
*/
static inline MemoryRegion *address_space_translate_cached(
- MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
+ const MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
hwaddr *plen, bool is_write, MemTxAttrs attrs)
{
MemoryRegionSection section;
@@ -3990,7 +3990,7 @@ static MemTxResult address_space_read_continue_cached(MemTxAttrs attrs,
* out of line function when the target is an MMIO or IOMMU region.
*/
MemTxResult
-address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
+address_space_read_cached_slow(const MemoryRegionCache *cache, hwaddr addr,
void *buf, hwaddr len)
{
hwaddr mr_addr, l;
@@ -4007,7 +4007,7 @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
* out of line function when the target is an MMIO or IOMMU region.
*/
MemTxResult
-address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
+address_space_write_cached_slow(const MemoryRegionCache *cache, hwaddr addr,
const void *buf, hwaddr len)
{
hwaddr mr_addr, l;
@@ -4020,7 +4020,7 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
buf, len, mr_addr, l, mr);
}
-#define ARG1_DECL MemoryRegionCache *cache
+#define ARG1_DECL const MemoryRegionCache *cache
#define ARG1 cache
#define SUFFIX _cached_slow
#define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
--
2.53.0
next prev parent reply other threads:[~2026-06-18 12:29 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-18 12:27 [PULL 00/48] Accel patches for 2026-06-18 Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 01/48] system/cpu: Reset vCPU %exception_index before resuming it Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 02/48] system/memory: Constify various AddressSpace arguments (checks) Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 03/48] system/memory: Constify various AddressSpace arguments (flat-range) Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 04/48] system/memory: Constify various AddressSpace arguments (notify) Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 05/48] system/memory: Constify various AddressSpace arguments (cache) Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 06/48] system/memory: Constify various AddressSpace arguments (access) Philippe Mathieu-Daudé
2026-06-18 12:27 ` Philippe Mathieu-Daudé [this message]
2026-06-18 12:27 ` [PULL 08/48] system: Document cpu_physical_memory_*() declarations Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 09/48] accel/kvm: Replace legacy cpu_physical_memory_write() call Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 10/48] gdbstub/system: Replace legacy cpu_physical_memory_read/write() calls Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 11/48] target/s390x: Factor common s390_ipl_read/write() helpers Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 12/48] target/s390x: Replace legacy cpu_physical_memory_read/write() calls Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 13/48] system: Move cpu_physical_memory_*() declarations to 'system/physmem.h' Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 14/48] hw/xen/interface: Remove pre-C99 checks Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 15/48] qom/object: Remove pre-C11 check Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 16/48] tcg: Include missing 'qemu/bitops.h' header in tcg-gvec-desc.h Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 17/48] target/i386: Report TPR accesses to HVF Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 18/48] target/arm: Only set CPU_INTERRUPT_EXITTB for TCG Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 19/48] target/arm: Remove vcpu_dirty=true assigments in hvf_handle_exception() Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 20/48] target/arm: Better describe PMU depends on TCG or HVF Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 21/48] target/arm/ptw: Restrict PMSAv8 code to TCG Philippe Mathieu-Daudé
2026-06-18 12:27 ` [PULL 22/48] target/arm: Restrict TCG specific headers Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 23/48] target/ppc: Restrict TCGTBCPUState to TCG Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 24/48] target/loongarch: Remove unused 'accel/accel-cpu-target.h' header Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 25/48] target/sparc: Include missing 'accel/tcg/cpu-ops.h' header in cpu.c Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 26/48] accel/hvf: fix double hv_vcpu_destroy() causing teardown error on ARM Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 27/48] accel/hvf: Reduce hvf_kernel_irqchip_override scope Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 28/48] accel/tcg: remove duplicate include Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 29/48] accel/tcg: Restrict IOMMU declarations Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 30/48] meson: build macOS signed binary as part of the default target Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 31/48] configure: honor --extra-ldflags when forced to use objc_LINKER Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 32/48] util/cutils: drop qemu_strnlen() in favor of strnlen() Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 33/48] ui/cocoa: Use qemu_input_map_osx_to_linux Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 34/48] exec/cpu-common.h: Include missing 'qemu/thread.h' header Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 35/48] exec/cpu-common.h: Avoid including unused 'exec/vaddr.h' header Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 36/48] exec/cpu-common.h: Avoid including unused 'tcg/debug-assert.h' header Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 37/48] exec/cpu-common.h: Avoid including unused exec/page-protection.h header Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 38/48] system/memory: Remove unnecessary CONFIG_USER_ONLY guards Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 39/48] system/memory: Rename cpu_exec_init_all() -> machine_memory_init() Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 40/48] hw/s390x/ipl: Remove TCG dependency in handle_diag_308() Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 41/48] accel/tcg: Remove cpu_loop_exit() stub Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 42/48] accel/tcg: Move cpu_exec() out of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 43/48] accel/tcg: Move cpu_exec_step_atomic() " Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 44/48] accel/tcg: Move cpu_unwind_state_data() " Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 45/48] accel/tcg: Move cpu_restore_state() " Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 46/48] accel/tcg: Have cpu_loop_exit_requested() take const @cpu argument Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 47/48] accel/tcg: Move cpu_loop_exit_*() out of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2026-06-18 12:28 ` [PULL 48/48] accel/tcg: Restrict headers being TCG specific Philippe Mathieu-Daudé
2026-06-18 17:54 ` [PULL 00/48] Accel patches for 2026-06-18 Stefan Hajnoczi
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