* [PATCH v2] hw/i386/x86-iommu: Correctly set pt bit in extended capability register
@ 2026-06-23 8:22 ` no92 via qemu development
0 siblings, 0 replies; 3+ messages in thread
From: no92 via @ 2026-06-23 8:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-trivial, qemu-stable, clement.mathieu--drif, yi.l.liu, mst,
no92, Jason Wang, Paolo Bonzini, Richard Henderson
With the changes in c7b2e22bd957, the `pt` bit was set in the (wrong)
capability register, instead of the (correct) extended capability
register.
Fixes: c7b2e22bd957 ("hw/i386/x86-iommu: Remove X86IOMMUState::pt_supported field")
Signed-off-by: no92 <leo@managarm.org>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
v1: https://lore.kernel.org/qemu-devel/20260622162138.1045170-1-leo@managarm.org/
hw/i386/intel_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 744cdfd2e6..d1af7a3135 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -4988,7 +4988,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
{
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
- s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_ECAP_PT |
+ s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SSLPS | VTD_CAP_DRAIN |
VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits);
if (x86_iommu->dma_translation) {
@@ -4999,7 +4999,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
s->cap |= VTD_CAP_SAGAW_48bit;
}
}
- s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
+ s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO | VTD_ECAP_PT;
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
--
2.54.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v2] hw/i386/x86-iommu: Correctly set pt bit in extended capability register
@ 2026-06-23 8:22 ` no92 via qemu development
0 siblings, 0 replies; 3+ messages in thread
From: no92 via qemu development @ 2026-06-23 8:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-trivial, qemu-stable, clement.mathieu--drif, yi.l.liu, mst,
no92, Jason Wang, Paolo Bonzini, Richard Henderson
With the changes in c7b2e22bd957, the `pt` bit was set in the (wrong)
capability register, instead of the (correct) extended capability
register.
Fixes: c7b2e22bd957 ("hw/i386/x86-iommu: Remove X86IOMMUState::pt_supported field")
Signed-off-by: no92 <leo@managarm.org>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
v1: https://lore.kernel.org/qemu-devel/20260622162138.1045170-1-leo@managarm.org/
hw/i386/intel_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 744cdfd2e6..d1af7a3135 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -4988,7 +4988,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
{
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
- s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_ECAP_PT |
+ s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SSLPS | VTD_CAP_DRAIN |
VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits);
if (x86_iommu->dma_translation) {
@@ -4999,7 +4999,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
s->cap |= VTD_CAP_SAGAW_48bit;
}
}
- s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
+ s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO | VTD_ECAP_PT;
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
--
2.54.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] hw/i386/x86-iommu: Correctly set pt bit in extended capability register
2026-06-23 8:22 ` no92 via qemu development
(?)
@ 2026-06-23 9:12 ` Michael S. Tsirkin
-1 siblings, 0 replies; 3+ messages in thread
From: Michael S. Tsirkin @ 2026-06-23 9:12 UTC (permalink / raw)
To: no92
Cc: qemu-devel, qemu-trivial, qemu-stable, clement.mathieu--drif,
yi.l.liu, Jason Wang, Paolo Bonzini, Richard Henderson
On Tue, Jun 23, 2026 at 10:22:23AM +0200, no92 wrote:
> With the changes in c7b2e22bd957, the `pt` bit was set in the (wrong)
> capability register, instead of the (correct) extended capability
> register.
>
> Fixes: c7b2e22bd957 ("hw/i386/x86-iommu: Remove X86IOMMUState::pt_supported field")
> Signed-off-by: no92 <leo@managarm.org>
> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
> Reviewed-by: Yi Liu <yi.l.liu@intel.com>
> ---
> v1: https://lore.kernel.org/qemu-devel/20260622162138.1045170-1-leo@managarm.org/
changes since v1?
> hw/i386/intel_iommu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 744cdfd2e6..d1af7a3135 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -4988,7 +4988,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
> {
> X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
>
> - s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_ECAP_PT |
> + s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
> VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SSLPS | VTD_CAP_DRAIN |
> VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits);
> if (x86_iommu->dma_translation) {
> @@ -4999,7 +4999,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
> s->cap |= VTD_CAP_SAGAW_48bit;
> }
> }
> - s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
> + s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO | VTD_ECAP_PT;
>
> if (x86_iommu_ir_supported(x86_iommu)) {
> s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
> --
> 2.54.0
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-06-23 9:13 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2026-06-23 8:22 [PATCH v2] hw/i386/x86-iommu: Correctly set pt bit in extended capability register no92 via
2026-06-23 8:22 ` no92 via qemu development
2026-06-23 9:12 ` Michael S. Tsirkin
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