[PATCH v2] cxl: Convert PCIBIOS errors to errno on remaining DVSEC/PCIe accesses

[PATCH v2] cxl: Convert PCIBIOS errors to errno on remaining DVSEC/PCIe accesses

[Richard Cheng]

Follow-up to Dav Jiang's commit 26aa60e02762 ("cxl/pci: Convert PCIBIOS
errors to errno on DVSEC config accesses") .

PCI config and PCIe capability accessors return positive PCIBIOS_*
status codes on failure, not negative errnos. update_gpf_port_dvsec()
and cxl_ras_unmask() still return the raw status on their accessor error
paths, inconsistent with the errno convention they otherwise use.
Convert it with pcibios_err_to_errno()

Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
Changelog:

v1->v2:
    - update_gpf_port_dvsec(): Also convert the pci_read_config_word()
      failure path. v1 converted only the write path.
    - Drop patch 2/2. On a failed config read the accessor returns ~0,
      which cxl_decode_regblock() already rejects, so
__cxl_find_regblock_instance() already returns -ENODDEV with
map-resource cleared. There's no bug, so the change is dropped.
    - Fix the commit message, the second call site is cxl_ras_unmask(),
      not cxl_setup_parent_dport(), fix a "Convert" typo.
---
 drivers/cxl/core/pci.c | 4 ++--
 drivers/cxl/port.c     | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index e4338fd7e01b..bf6d566b2d6b 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -838,7 +838,7 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
 
 	rc = pci_read_config_word(pdev, dvsec + offset, &ctrl);
 	if (rc)
-		return rc;
+		return pcibios_err_to_errno(rc);
 
 	if (FIELD_GET(base, ctrl) == GPF_TIMEOUT_BASE_MAX &&
 	    FIELD_GET(scale, ctrl) == GPF_TIMEOUT_SCALE_MAX)
@@ -852,7 +852,7 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
 		pci_dbg(pdev, "Port GPF phase %d timeout: %d0 secs\n",
 			phase, GPF_TIMEOUT_BASE_MAX);
 
-	return rc;
+	return pcibios_err_to_errno(rc);
 }
 
 int cxl_gpf_port_setup(struct cxl_dport *dport)
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 99cf77b6b699..8db4d15e9427 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -92,7 +92,7 @@ static int cxl_ras_unmask(struct cxl_port *port)
 
 	rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
 	if (rc)
-		return rc;
+		return pcibios_err_to_errno(rc);
 
 	if (cap & PCI_EXP_DEVCTL_URRE) {
 		addr = port->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET;

base-commit: ef0c9f75a19532d7675384708fc8621e10850104
-- 
2.43.0