* [PATCH 0/5] gpu: nova-core: Move registers definitions
@ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay
0 siblings, 0 replies; 17+ messages in thread
From: Antonin Malzieu Ridolfi @ 2026-06-16 23:48 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter, Antonin Malzieu Ridolfi
Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida
Split part of the registers definitions grouped in nova root register file
to belonging modules whom actually use them.
To: Danilo Krummrich <dakr@kernel.org>
To: Alexandre Courbot <acourbot@nvidia.com>
To: Alice Ryhl <aliceryhl@google.com>
To: David Airlie <airlied@gmail.com>
To: Simona Vetter <simona@ffwll.ch>
To: Antonin Malzieu Ridolfi <dev@nanonej.com>
Cc: linux-kernel@vger.kernel.org
Cc: nova-gpu@lists.linux.dev
Cc: dri-devel@lists.freedesktop.org
Cc: daniel.almeida@collabora.com
Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
---
Antonin Malzieu Ridolfi (5):
gpu: nova-core: fb: Move PDISP register definition
gpu: nova-core: gsp: Move PBUS register definition
gpu: nova-core: falcon: Move PFALCON2 register
gpu: nova-core: falcon: Move PRISCV register
gpu: nova-core: falcon: Move PFSP register
drivers/gpu/nova-core/falcon.rs | 71 +++++++++++---------
drivers/gpu/nova-core/falcon/fsp.rs | 14 ++--
drivers/gpu/nova-core/falcon/hal/ga102.rs | 32 +++++----
drivers/gpu/nova-core/falcon/hal/tu102.rs | 8 +--
drivers/gpu/nova-core/falcon/regs.rs | 76 +++++++++++++++++++++
drivers/gpu/nova-core/fb.rs | 4 +-
drivers/gpu/nova-core/fb/regs.rs | 25 +++++++
drivers/gpu/nova-core/gsp/hal/tu102.rs | 12 ++--
drivers/gpu/nova-core/gsp/regs.rs | 11 ++++
drivers/gpu/nova-core/regs.rs | 105 +-----------------------------
10 files changed, 191 insertions(+), 167 deletions(-)
---
base-commit: 5f7410aa26524101d34b627fbe16670b1514962c
change-id: 20260616-nova-core-regs-split-e2a8b22caaf4
Best regards,
--
Antonin Malzieu Ridolfi <dev@nanonej.com>
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 0/5] gpu: nova-core: Move registers definitions @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 0 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida Split part of the registers definitions grouped in nova root register file to belonging modules whom actually use them. To: Danilo Krummrich <dakr@kernel.org> To: Alexandre Courbot <acourbot@nvidia.com> To: Alice Ryhl <aliceryhl@google.com> To: David Airlie <airlied@gmail.com> To: Simona Vetter <simona@ffwll.ch> To: Antonin Malzieu Ridolfi <dev@nanonej.com> Cc: linux-kernel@vger.kernel.org Cc: nova-gpu@lists.linux.dev Cc: dri-devel@lists.freedesktop.org Cc: daniel.almeida@collabora.com Suggested-by: Alexandre Courbot <acourbot@nvidia.com> Suggested-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- Antonin Malzieu Ridolfi (5): gpu: nova-core: fb: Move PDISP register definition gpu: nova-core: gsp: Move PBUS register definition gpu: nova-core: falcon: Move PFALCON2 register gpu: nova-core: falcon: Move PRISCV register gpu: nova-core: falcon: Move PFSP register drivers/gpu/nova-core/falcon.rs | 71 +++++++++++--------- drivers/gpu/nova-core/falcon/fsp.rs | 14 ++-- drivers/gpu/nova-core/falcon/hal/ga102.rs | 32 +++++---- drivers/gpu/nova-core/falcon/hal/tu102.rs | 8 +-- drivers/gpu/nova-core/falcon/regs.rs | 76 +++++++++++++++++++++ drivers/gpu/nova-core/fb.rs | 4 +- drivers/gpu/nova-core/fb/regs.rs | 25 +++++++ drivers/gpu/nova-core/gsp/hal/tu102.rs | 12 ++-- drivers/gpu/nova-core/gsp/regs.rs | 11 ++++ drivers/gpu/nova-core/regs.rs | 105 +----------------------------- 10 files changed, 191 insertions(+), 167 deletions(-) --- base-commit: 5f7410aa26524101d34b627fbe16670b1514962c change-id: 20260616-nova-core-regs-split-e2a8b22caaf4 Best regards, -- Antonin Malzieu Ridolfi <dev@nanonej.com> ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/5] gpu: nova-core: fb: Move PDISP register definition 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay -1 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida Move PDISP register definition into fb module and update register visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/fb.rs | 4 ++-- drivers/gpu/nova-core/fb/regs.rs | 25 +++++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 22 ---------------------- 3 files changed, 27 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 725e428154cf..4385b5d53e85 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -23,11 +23,11 @@ firmware::gsp::GspFirmware, gpu::Chipset, gsp, - num::FromSafeCast, - regs, // + num::FromSafeCast // }; mod hal; +mod regs; /// Type holding the sysmem flush memory page, a page of memory to be written into the /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR*` registers and used to maintain memory coherency. diff --git a/drivers/gpu/nova-core/fb/regs.rs b/drivers/gpu/nova-core/fb/regs.rs new file mode 100644 index 000000000000..b2ec02f584be --- /dev/null +++ b/drivers/gpu/nova-core/fb/regs.rs @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::io::register; + +// PDISP + +register! { + pub(super) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { + /// VGA workspace base address divided by 0x10000. + 31:8 addr; + /// Set if the `addr` field is valid. + 3:3 status_valid => bool; + } +} + +impl NV_PDISP_VGA_WORKSPACE_BASE { + /// Returns the base address of the VGA workspace, or `None` if none exists. + pub(super) fn vga_workspace_addr(self) -> Option<u64> { + if self.status_valid() { + Some(u64::from(self.addr()) << 16) + } else { + None + } + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 73339a0cff99..6a86ac05e59f 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -286,28 +286,6 @@ pub(crate) fn usable_fb_size(self) -> u64 { } } -// PDISP - -register! { - pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { - /// VGA workspace base address divided by 0x10000. - 31:8 addr; - /// Set if the `addr` field is valid. - 3:3 status_valid => bool; - } -} - -impl NV_PDISP_VGA_WORKSPACE_BASE { - /// Returns the base address of the VGA workspace, or `None` if none exists. - pub(crate) fn vga_workspace_addr(self) -> Option<u64> { - if self.status_valid() { - Some(u64::from(self.addr()) << 16) - } else { - None - } - } -} - // FUSE pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16; -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/5] gpu: nova-core: fb: Move PDISP register definition @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 0 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida From: Antonin Malzieu Ridolfi <dev@nanonej.com> Move PDISP register definition into fb module and update register visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/fb.rs | 4 ++-- drivers/gpu/nova-core/fb/regs.rs | 25 +++++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 22 ---------------------- 3 files changed, 27 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 725e428154cf..4385b5d53e85 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -23,11 +23,11 @@ firmware::gsp::GspFirmware, gpu::Chipset, gsp, - num::FromSafeCast, - regs, // + num::FromSafeCast // }; mod hal; +mod regs; /// Type holding the sysmem flush memory page, a page of memory to be written into the /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR*` registers and used to maintain memory coherency. diff --git a/drivers/gpu/nova-core/fb/regs.rs b/drivers/gpu/nova-core/fb/regs.rs new file mode 100644 index 000000000000..b2ec02f584be --- /dev/null +++ b/drivers/gpu/nova-core/fb/regs.rs @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::io::register; + +// PDISP + +register! { + pub(super) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { + /// VGA workspace base address divided by 0x10000. + 31:8 addr; + /// Set if the `addr` field is valid. + 3:3 status_valid => bool; + } +} + +impl NV_PDISP_VGA_WORKSPACE_BASE { + /// Returns the base address of the VGA workspace, or `None` if none exists. + pub(super) fn vga_workspace_addr(self) -> Option<u64> { + if self.status_valid() { + Some(u64::from(self.addr()) << 16) + } else { + None + } + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 73339a0cff99..6a86ac05e59f 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -286,28 +286,6 @@ pub(crate) fn usable_fb_size(self) -> u64 { } } -// PDISP - -register! { - pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { - /// VGA workspace base address divided by 0x10000. - 31:8 addr; - /// Set if the `addr` field is valid. - 3:3 status_valid => bool; - } -} - -impl NV_PDISP_VGA_WORKSPACE_BASE { - /// Returns the base address of the VGA workspace, or `None` if none exists. - pub(crate) fn vga_workspace_addr(self) -> Option<u64> { - if self.status_valid() { - Some(u64::from(self.addr()) << 16) - } else { - None - } - } -} - // FUSE pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16; -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/5] gpu: nova-core: fb: Move PDISP register definition 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay (?) @ 2026-06-23 6:18 ` Alexandre Courbot -1 siblings, 0 replies; 17+ messages in thread From: Alexandre Courbot @ 2026-06-23 6:18 UTC (permalink / raw) To: Antonin Malzieu Ridolfi via B4 Relay Cc: dev, Danilo Krummrich, Alice Ryhl, David Airlie, Simona Vetter, linux-kernel, nova-gpu, dri-devel, daniel.almeida On Wed Jun 17, 2026 at 8:48 AM JST, Antonin Malzieu Ridolfi via B4 Relay wrote: > From: Antonin Malzieu Ridolfi <dev@nanonej.com> > > Move PDISP register definition into fb module and update register > visibility. > > Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> Pushed to drm-rust-next, thanks! [acourbot: fix rustfmt issue.] ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/5] gpu: nova-core: gsp: Move PBUS register definition 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay -1 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida Move PBUS register definition into gsp module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/gsp/hal/tu102.rs | 12 ++++++------ drivers/gpu/nova-core/gsp/regs.rs | 11 +++++++++++ drivers/gpu/nova-core/regs.rs | 11 ----------- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core/gsp/hal/tu102.rs index eb7166148cc9..d46e8ec65785 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -37,6 +37,7 @@ GspHal, UnloadBundle, // }, + regs, sequencer::{ GspSequencer, GspSequencerParams, // @@ -44,7 +45,6 @@ Gsp, GspFwWprMeta, // }, - regs, vbios::Vbios, // }; @@ -141,7 +141,7 @@ fn run( .inspect_err(|e| dev_err!(dev, "FWSEC-SB failed to run: {:?}\n", e)); // Remove WPR2 region if set. - let wpr2_hi = bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); + let wpr2_hi = bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); let booter_unloader_res = (|| { if !wpr2_hi.is_wpr2_set() { return Ok(()); @@ -160,7 +160,7 @@ fn run( } // Confirm that the WPR2 region has been removed. - let wpr2_hi = bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); + let wpr2_hi = bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); if wpr2_hi.is_wpr2_set() { dev_err!( dev, @@ -189,7 +189,7 @@ fn run_fwsec_frts( ) -> Result { // Check that the WPR2 region does not already exist - if it does, we cannot run // FWSEC-FRTS until the GPU is reset. - if bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() != 0 { + if bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() != 0 { dev_err!( dev, "WPR2 region already exists - GPU needs to be reset to proceed\n" @@ -234,8 +234,8 @@ fn run_fwsec_frts( // Check that the WPR2 region has been created as we requested. let (wpr2_lo, wpr2_hi) = ( - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(), - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(), + bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(), + bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(), ); match (wpr2_lo, wpr2_hi) { diff --git a/drivers/gpu/nova-core/gsp/regs.rs b/drivers/gpu/nova-core/gsp/regs.rs index a76dea3c3ab0..571b7e0a95ee 100644 --- a/drivers/gpu/nova-core/gsp/regs.rs +++ b/drivers/gpu/nova-core/gsp/regs.rs @@ -2,6 +2,17 @@ use kernel::io::register; +// PBUS + +register! { + pub(super) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} + + /// Scratch register 0xe used as FRTS firmware error code. + pub(super) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) => NV_PBUS_SW_SCRATCH[0xe] { + 31:16 frts_err_code; + } +} + // PGSP register! { diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 6a86ac05e59f..59d36870b92b 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -105,17 +105,6 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { } } -// PBUS - -register! { - pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} - - /// Scratch register 0xe used as FRTS firmware error code. - pub(crate) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) => NV_PBUS_SW_SCRATCH[0xe] { - 31:16 frts_err_code; - } -} - // PFB register! { -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/5] gpu: nova-core: gsp: Move PBUS register definition @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 0 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida From: Antonin Malzieu Ridolfi <dev@nanonej.com> Move PBUS register definition into gsp module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/gsp/hal/tu102.rs | 12 ++++++------ drivers/gpu/nova-core/gsp/regs.rs | 11 +++++++++++ drivers/gpu/nova-core/regs.rs | 11 ----------- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core/gsp/hal/tu102.rs index eb7166148cc9..d46e8ec65785 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -37,6 +37,7 @@ GspHal, UnloadBundle, // }, + regs, sequencer::{ GspSequencer, GspSequencerParams, // @@ -44,7 +45,6 @@ Gsp, GspFwWprMeta, // }, - regs, vbios::Vbios, // }; @@ -141,7 +141,7 @@ fn run( .inspect_err(|e| dev_err!(dev, "FWSEC-SB failed to run: {:?}\n", e)); // Remove WPR2 region if set. - let wpr2_hi = bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); + let wpr2_hi = bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); let booter_unloader_res = (|| { if !wpr2_hi.is_wpr2_set() { return Ok(()); @@ -160,7 +160,7 @@ fn run( } // Confirm that the WPR2 region has been removed. - let wpr2_hi = bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); + let wpr2_hi = bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); if wpr2_hi.is_wpr2_set() { dev_err!( dev, @@ -189,7 +189,7 @@ fn run_fwsec_frts( ) -> Result { // Check that the WPR2 region does not already exist - if it does, we cannot run // FWSEC-FRTS until the GPU is reset. - if bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() != 0 { + if bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() != 0 { dev_err!( dev, "WPR2 region already exists - GPU needs to be reset to proceed\n" @@ -234,8 +234,8 @@ fn run_fwsec_frts( // Check that the WPR2 region has been created as we requested. let (wpr2_lo, wpr2_hi) = ( - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(), - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(), + bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(), + bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(), ); match (wpr2_lo, wpr2_hi) { diff --git a/drivers/gpu/nova-core/gsp/regs.rs b/drivers/gpu/nova-core/gsp/regs.rs index a76dea3c3ab0..571b7e0a95ee 100644 --- a/drivers/gpu/nova-core/gsp/regs.rs +++ b/drivers/gpu/nova-core/gsp/regs.rs @@ -2,6 +2,17 @@ use kernel::io::register; +// PBUS + +register! { + pub(super) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} + + /// Scratch register 0xe used as FRTS firmware error code. + pub(super) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) => NV_PBUS_SW_SCRATCH[0xe] { + 31:16 frts_err_code; + } +} + // PGSP register! { diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 6a86ac05e59f..59d36870b92b 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -105,17 +105,6 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { } } -// PBUS - -register! { - pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} - - /// Scratch register 0xe used as FRTS firmware error code. - pub(crate) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) => NV_PBUS_SW_SCRATCH[0xe] { - 31:16 frts_err_code; - } -} - // PFB register! { -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 2/5] gpu: nova-core: gsp: Move PBUS register definition 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay (?) @ 2026-06-23 6:18 ` Alexandre Courbot -1 siblings, 0 replies; 17+ messages in thread From: Alexandre Courbot @ 2026-06-23 6:18 UTC (permalink / raw) To: Antonin Malzieu Ridolfi via B4 Relay Cc: dev, Danilo Krummrich, Alice Ryhl, David Airlie, Simona Vetter, linux-kernel, nova-gpu, dri-devel, daniel.almeida On Wed Jun 17, 2026 at 8:48 AM JST, Antonin Malzieu Ridolfi via B4 Relay wrote: > From: Antonin Malzieu Ridolfi <dev@nanonej.com> > > Move PBUS register definition into gsp module and update registers > visibility. > > Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> This one also didn't pass `rustfmtcheck` - please make sure to run the checklist [1] (notably `rustfmt`) on each patch before submitting. Some more comments below. [1] https://rust-for-linux.com/contributing#submit-checklist-addendum > --- > drivers/gpu/nova-core/gsp/hal/tu102.rs | 12 ++++++------ > drivers/gpu/nova-core/gsp/regs.rs | 11 +++++++++++ > drivers/gpu/nova-core/regs.rs | 11 ----------- > 3 files changed, 17 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core/gsp/hal/tu102.rs > index eb7166148cc9..d46e8ec65785 100644 > --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs > +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs > @@ -37,6 +37,7 @@ > GspHal, > UnloadBundle, // > }, > + regs, > sequencer::{ > GspSequencer, > GspSequencerParams, // > @@ -44,7 +45,6 @@ > Gsp, > GspFwWprMeta, // > }, > - regs, > vbios::Vbios, // > }; > > @@ -141,7 +141,7 @@ fn run( > .inspect_err(|e| dev_err!(dev, "FWSEC-SB failed to run: {:?}\n", e)); > > // Remove WPR2 region if set. > - let wpr2_hi = bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); > + let wpr2_hi = bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); It would be nice if we could avoid re-scoping registers that don't move, and I think we can achieve that as part of a slightly larger series. Notice how we are accessing `PFB` registers (`WPR2_ADDR_HI` and `WPR_ADDR_LO`) despite being in the `gsp` module. Let's start by fixing that. These two registers are only ever accessed by the GSP's TU102 HAL to check whether a WPR2 region (a memory range going between `ADDR_LO` and `ADDR_HI`) is set and what its range is. The TU102 code manipulates these registers directly, but we could move them to the right place if we did that as a FB service. There could be a function in the `fb` module that reads the registers and returns an `Option<Range<u64>>` - `None` if `is_wpr2_set` is `false`, or the WPR2 range otherwise. Then the GSP TU102 HAL would just use this function instead of poking the register as it currently does. Doing so would move the WPR2 registers to the right place, and provide the right abstraction for the WPR2 region. A patch series doing this could look like this: - Add the `fb` module function abstracting the WPR2 region registers and use it in the GSP's TU102 HAL. - Move the `NV_PFB_PRI_MMU_WPR2_ADDR*` registers under the `fb` module. - Move the `NV_PBUS_SW_SCRATCH_0E_FRTS_ERR` register under the `gsp` module, since it is clearly themed after `FRTS`, which is part of the GSP boot. But, without moving `NV_PBUS_SW_SCRATCH` (the actual register being aliased). I expect you will hit a bug of the `register` macro when doing this one - I'll try to address it, but the first two steps should be safe to do and correct. ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/5] gpu: nova-core: falcon: Move PFALCON2 register 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay -1 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida Move PFALCON2 register definition into falcon module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/falcon.rs | 71 ++++++++++++++++++------------- drivers/gpu/nova-core/falcon/hal/ga102.rs | 38 +++++++++-------- drivers/gpu/nova-core/falcon/regs.rs | 30 +++++++++++++ drivers/gpu/nova-core/regs.rs | 23 ---------- 4 files changed, 92 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 94c7696a6493..c2215ddd9e80 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -37,12 +37,12 @@ self, FromSafeCast, // }, - regs, }; pub(crate) mod fsp; pub(crate) mod gsp; mod hal; +mod regs; pub(crate) mod sec2; /// Alignment (in bytes) of falcon memory blocks. @@ -99,7 +99,7 @@ pub(crate) enum FalconSecurityModel with TryFrom<Bounded<u32, 2>> { bounded_enum! { /// Signing algorithm for a given firmware, used in the - /// [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM + /// [`super::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM /// (BROM) as a parameter. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconModSelAlgo with TryFrom<Bounded<u32, 8>> { @@ -374,13 +374,13 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset) -> Result<Self> { /// Resets DMA-related registers. pub(crate) fn dma_reset(&self, bar: Bar0<'_>) { - bar.update(regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { + bar.update(crate::regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { v.with_allow_phys_no_ctx(true) }); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMACTL::zeroed(), + crate::regs::NV_PFALCON_FALCON_DMACTL::zeroed(), ); } @@ -392,7 +392,8 @@ pub(crate) fn reset(&self, bar: Bar0<'_>) -> Result { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_RM::from(bar.read(regs::NV_PMC_BOOT_0).into_raw()), + crate::regs::NV_PFALCON_FALCON_RM:: + from(bar.read(crate::regs::NV_PMC_BOOT_0).into_raw()), ); Ok(()) @@ -417,7 +418,7 @@ fn pio_wr_imem_slice( bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_IMEMC::zeroed() + crate::regs::NV_PFALCON_FALCON_IMEMC::zeroed() .with_secure(load_offsets.secure) .with_aincw(true) .with_offs(load_offsets.dst_start), @@ -428,13 +429,14 @@ fn pio_wr_imem_slice( let tag: u16 = load_offsets.start_tag.checked_add(n).ok_or(ERANGE)?; bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_IMEMT::zeroed().with_tag(tag), + crate::regs::NV_PFALCON_FALCON_IMEMT::zeroed().with_tag(tag), ); for word in block.chunks_exact(4) { let w = [word[0], word[1], word[2], word[3]]; bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_IMEMD::zeroed().with_data(u32::from_le_bytes(w)), + crate::regs::NV_PFALCON_FALCON_IMEMD::zeroed() + .with_data(u32::from_le_bytes(w)), ); } } @@ -458,7 +460,7 @@ fn pio_wr_dmem_slice( bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_DMEMC::zeroed() + crate::regs::NV_PFALCON_FALCON_DMEMC::zeroed() .with_aincw(true) .with_offs(load_offsets.dst_start), ); @@ -467,7 +469,8 @@ fn pio_wr_dmem_slice( let w = [word[0], word[1], word[2], word[3]]; bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_DMEMD::zeroed().with_data(u32::from_le_bytes(w)), + crate::regs::NV_PFALCON_FALCON_DMEMD::zeroed() + .with_data(u32::from_le_bytes(w)), ); } @@ -480,13 +483,13 @@ pub(crate) fn pio_load<F: FalconFirmware<Target = E> + FalconPioLoadable>( bar: Bar0<'_>, fw: &F, ) -> Result { - bar.update(regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { + bar.update(crate::regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { v.with_allow_phys_no_ctx(true) }); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMACTL::zeroed(), + crate::regs::NV_PFALCON_FALCON_DMACTL::zeroed(), ); if let Some(imem_ns) = fw.imem_ns_load_params() { @@ -501,7 +504,8 @@ pub(crate) fn pio_load<F: FalconFirmware<Target = E> + FalconPioLoadable>( bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_BOOTVEC::zeroed().with_value(fw.boot_addr()), + crate::regs::NV_PFALCON_FALCON_BOOTVEC::zeroed() + .with_value(fw.boot_addr()), ); Ok(()) @@ -573,7 +577,7 @@ fn dma_wr( bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFBASE::zeroed().with_base( + crate::regs::NV_PFALCON_FALCON_DMATRFBASE::zeroed().with_base( // CAST: `as u32` is used on purpose since we do want to strip the upper bits, // which will be written to `NV_PFALCON_FALCON_DMATRFBASE1`. (dma_start >> 8) as u32, @@ -581,10 +585,11 @@ fn dma_wr( ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFBASE1::zeroed().try_with_base(dma_start >> 40)?, + crate::regs::NV_PFALCON_FALCON_DMATRFBASE1::zeroed() + .try_with_base(dma_start >> 40)?, ); - let cmd = regs::NV_PFALCON_FALCON_DMATRFCMD::zeroed() + let cmd = crate::regs::NV_PFALCON_FALCON_DMATRFCMD::zeroed() .with_size(DmaTrfCmdSize::Size256B) .with_falcon_mem(target_mem); @@ -592,12 +597,13 @@ fn dma_wr( // Perform a transfer of size `DMA_LEN`. bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFMOFFS::zeroed() + crate::regs::NV_PFALCON_FALCON_DMATRFMOFFS::zeroed() .try_with_offs(load_offsets.dst_start + pos)?, ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFFBOFFS::zeroed().with_offs(src_start + pos), + crate::regs::NV_PFALCON_FALCON_DMATRFFBOFFS::zeroed() + .with_offs(src_start + pos), ); bar.write(WithBase::of::<E>(), cmd); @@ -606,7 +612,7 @@ fn dma_wr( // TIMEOUT: arbitrarily large value, no DMA transfer to the falcon's small memories // should ever take that long. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_DMATRFCMD::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_DMATRFCMD::of::<E>())), |r| r.idle(), Delta::ZERO, Delta::from_secs(2), @@ -643,7 +649,7 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( }; self.dma_reset(bar); - bar.update(regs::NV_PFALCON_FBIF_TRANSCFG::of::<E>().at(0), |v| { + bar.update(crate::regs::NV_PFALCON_FBIF_TRANSCFG::of::<E>().at(0), |v| { v.with_target(FalconFbifTarget::CoherentSysmem) .with_mem_type(FalconFbifMemType::Physical) }); @@ -661,7 +667,8 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( // Set `BootVec` to start of non-secure code. bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_BOOTVEC::zeroed().with_value(fw.boot_addr()), + crate::regs::NV_PFALCON_FALCON_BOOTVEC::zeroed() + .with_value(fw.boot_addr()), ); Ok(()) @@ -671,7 +678,7 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( pub(crate) fn wait_till_halted(&self, bar: Bar0<'_>) -> Result<()> { // TIMEOUT: arbitrarily large value, firmwares should complete in less than 2 seconds. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_CPUCTL::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_CPUCTL::of::<E>())), |r| r.halted(), Delta::ZERO, Delta::from_secs(2), @@ -683,16 +690,18 @@ pub(crate) fn wait_till_halted(&self, bar: Bar0<'_>) -> Result<()> { /// Start the falcon CPU. pub(crate) fn start(&self, bar: Bar0<'_>) -> Result<()> { match bar - .read(regs::NV_PFALCON_FALCON_CPUCTL::of::<E>()) + .read(crate::regs::NV_PFALCON_FALCON_CPUCTL::of::<E>()) .alias_en() { true => bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_CPUCTL_ALIAS::zeroed().with_startcpu(true), + crate::regs::NV_PFALCON_FALCON_CPUCTL_ALIAS::zeroed() + .with_startcpu(true), ), false => bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_CPUCTL::zeroed().with_startcpu(true), + crate::regs::NV_PFALCON_FALCON_CPUCTL::zeroed() + .with_startcpu(true), ), } @@ -704,27 +713,29 @@ pub(crate) fn write_mailboxes(&self, bar: Bar0<'_>, mbox0: Option<u32>, mbox1: O if let Some(mbox0) = mbox0 { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_MAILBOX0::zeroed().with_value(mbox0), + crate::regs::NV_PFALCON_FALCON_MAILBOX0::zeroed() + .with_value(mbox0), ); } if let Some(mbox1) = mbox1 { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_MAILBOX1::zeroed().with_value(mbox1), + crate::regs::NV_PFALCON_FALCON_MAILBOX1::zeroed() + .with_value(mbox1), ); } } /// Reads the value from `mbox0` register. pub(crate) fn read_mailbox0(&self, bar: Bar0<'_>) -> u32 { - bar.read(regs::NV_PFALCON_FALCON_MAILBOX0::of::<E>()) + bar.read(crate::regs::NV_PFALCON_FALCON_MAILBOX0::of::<E>()) .value() } /// Reads the value from `mbox1` register. pub(crate) fn read_mailbox1(&self, bar: Bar0<'_>) -> u32 { - bar.read(regs::NV_PFALCON_FALCON_MAILBOX1::of::<E>()) + bar.read(crate::regs::NV_PFALCON_FALCON_MAILBOX1::of::<E>()) .value() } @@ -792,7 +803,7 @@ pub(crate) fn load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( pub(crate) fn write_os_version(&self, bar: Bar0<'_>, app_version: u32) { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_OS::zeroed().with_value(app_version), + crate::regs::NV_PFALCON_FALCON_OS::zeroed().with_value(app_version), ); } } diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs index cf6ce47e6b25..cc574fef0fbd 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -24,24 +24,25 @@ FalconBromParams, FalconEngine, FalconModSelAlgo, - PeregrineCoreSelect, // + PeregrineCoreSelect, + regs, // }, - regs, }; use super::FalconHal; fn select_core_ga102<E: FalconEngine>(bar: Bar0<'_>) -> Result { - let bcr_ctrl = bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); + let bcr_ctrl = bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); if bcr_ctrl.core_select() != PeregrineCoreSelect::Falcon { bar.write( WithBase::of::<E>(), - regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed().with_core_select(PeregrineCoreSelect::Falcon), + crate::regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed() + .with_core_select(PeregrineCoreSelect::Falcon), ); // TIMEOUT: falcon core should take less than 10ms to report being enabled. read_poll_timeout( - || Ok(bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), + || Ok(bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), |r| r.valid(), Delta::ZERO, Delta::from_millis(10), @@ -59,7 +60,7 @@ fn signature_reg_fuse_version_ga102( ) -> Result<u32> { // Each engine has 16 ucode version registers numbered from 1 to 16. let ucode_idx = match usize::from(ucode_id) { - ucode_id @ 1..=regs::NV_FUSE_OPT_FPF_SIZE => ucode_id - 1, + ucode_id @ 1..=crate::regs::NV_FUSE_OPT_FPF_SIZE => ucode_id - 1, _ => { dev_err!(dev, "invalid ucode id {:#x}\n", ucode_id); return Err(EINVAL); @@ -69,13 +70,13 @@ fn signature_reg_fuse_version_ga102( // `ucode_idx` is guaranteed to be in the range [0..15], making the `read` calls provable valid // at build-time. let reg_fuse_version: u16 = if engine_id_mask & 0x0001 != 0 { - bar.read(regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx)) + bar.read(crate::regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx)) .data() } else if engine_id_mask & 0x0004 != 0 { - bar.read(regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx)) + bar.read(crate::regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx)) .data() } else if engine_id_mask & 0x0400 != 0 { - bar.read(regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx)) + bar.read(crate::regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx)) .data() } else { dev_err!(dev, "unexpected engine_id_mask {:#x}\n", engine_id_mask); @@ -89,7 +90,8 @@ fn signature_reg_fuse_version_ga102( fn program_brom_ga102<E: FalconEngine>(bar: Bar0<'_>, params: &FalconBromParams) { bar.write( WithBase::of::<E>().at(0), - regs::NV_PFALCON2_FALCON_BROM_PARAADDR::zeroed().with_value(params.pkc_data_offset), + regs::NV_PFALCON2_FALCON_BROM_PARAADDR::zeroed() + .with_value(params.pkc_data_offset), ); bar.write( WithBase::of::<E>(), @@ -98,11 +100,13 @@ fn program_brom_ga102<E: FalconEngine>(bar: Bar0<'_>, params: &FalconBromParams) ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::zeroed().with_ucode_id(params.ucode_id), + regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::zeroed() + .with_ucode_id(params.ucode_id), ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON2_FALCON_MOD_SEL::zeroed().with_algo(FalconModSelAlgo::Rsa3k), + regs::NV_PFALCON2_FALCON_MOD_SEL::zeroed() + .with_algo(FalconModSelAlgo::Rsa3k), ); } @@ -134,14 +138,14 @@ fn program_brom(&self, _falcon: &Falcon<E>, bar: Bar0<'_>, params: &FalconBromPa } fn is_riscv_active(&self, bar: Bar0<'_>) -> bool { - bar.read(regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) + bar.read(crate::regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) .active_stat() } fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { // TIMEOUT: memory scrubbing should complete in less than 20ms. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), |r| r.mem_scrubbing_done(), Delta::ZERO, Delta::from_millis(20), @@ -150,18 +154,18 @@ fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { } fn reset_eng(&self, bar: Bar0<'_>) -> Result { - let _ = bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<E>()); + let _ = bar.read(crate::regs::NV_PFALCON_FALCON_HWCFG2::of::<E>()); // According to OpenRM's `kflcnPreResetWait_GA102` documentation, HW sometimes does not set // RESET_READY so a non-failing timeout is used. let _ = read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), |r| r.reset_ready(), Delta::ZERO, Delta::from_micros(150), ); - regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); + crate::regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); self.reset_wait_mem_scrubbing(bar)?; Ok(()) diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs new file mode 100644 index 000000000000..be8dbb599fc9 --- /dev/null +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::io::register; + +use crate::falcon::{ + PFalcon2Base, + FalconModSelAlgo, // +}; + +/* PFALCON2 */ + +register! { + pub(super) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 { + 7:0 algo ?=> FalconModSelAlgo; + } + + pub(super) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 { + 7:0 ucode_id => u8; + } + + pub(super) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c { + 31:0 value => u32; + } + + /// OpenRM defines this as a register array, but doesn't specify its size and only uses its + /// first element. Be conservative until we know the actual size or need to use more registers. + pub(super) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 { + 31:0 value => u32; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 59d36870b92b..0b048086f54f 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -22,7 +22,6 @@ FalconFbifMemType, FalconFbifTarget, FalconMem, - FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, PFalconBase, @@ -494,28 +493,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } -/* PFALCON2 */ - -register! { - pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 { - 7:0 algo ?=> FalconModSelAlgo; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 { - 7:0 ucode_id => u8; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c { - 31:0 value => u32; - } - - /// OpenRM defines this as a register array, but doesn't specify its size and only uses its - /// first element. Be conservative until we know the actual size or need to use more registers. - pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 { - 31:0 value => u32; - } -} - // PRISCV register! { -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/5] gpu: nova-core: falcon: Move PFALCON2 register @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 0 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida From: Antonin Malzieu Ridolfi <dev@nanonej.com> Move PFALCON2 register definition into falcon module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/falcon.rs | 71 ++++++++++++++++++------------- drivers/gpu/nova-core/falcon/hal/ga102.rs | 38 +++++++++-------- drivers/gpu/nova-core/falcon/regs.rs | 30 +++++++++++++ drivers/gpu/nova-core/regs.rs | 23 ---------- 4 files changed, 92 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 94c7696a6493..c2215ddd9e80 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -37,12 +37,12 @@ self, FromSafeCast, // }, - regs, }; pub(crate) mod fsp; pub(crate) mod gsp; mod hal; +mod regs; pub(crate) mod sec2; /// Alignment (in bytes) of falcon memory blocks. @@ -99,7 +99,7 @@ pub(crate) enum FalconSecurityModel with TryFrom<Bounded<u32, 2>> { bounded_enum! { /// Signing algorithm for a given firmware, used in the - /// [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM + /// [`super::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM /// (BROM) as a parameter. #[derive(Debug, Copy, Clone)] pub(crate) enum FalconModSelAlgo with TryFrom<Bounded<u32, 8>> { @@ -374,13 +374,13 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset) -> Result<Self> { /// Resets DMA-related registers. pub(crate) fn dma_reset(&self, bar: Bar0<'_>) { - bar.update(regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { + bar.update(crate::regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { v.with_allow_phys_no_ctx(true) }); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMACTL::zeroed(), + crate::regs::NV_PFALCON_FALCON_DMACTL::zeroed(), ); } @@ -392,7 +392,8 @@ pub(crate) fn reset(&self, bar: Bar0<'_>) -> Result { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_RM::from(bar.read(regs::NV_PMC_BOOT_0).into_raw()), + crate::regs::NV_PFALCON_FALCON_RM:: + from(bar.read(crate::regs::NV_PMC_BOOT_0).into_raw()), ); Ok(()) @@ -417,7 +418,7 @@ fn pio_wr_imem_slice( bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_IMEMC::zeroed() + crate::regs::NV_PFALCON_FALCON_IMEMC::zeroed() .with_secure(load_offsets.secure) .with_aincw(true) .with_offs(load_offsets.dst_start), @@ -428,13 +429,14 @@ fn pio_wr_imem_slice( let tag: u16 = load_offsets.start_tag.checked_add(n).ok_or(ERANGE)?; bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_IMEMT::zeroed().with_tag(tag), + crate::regs::NV_PFALCON_FALCON_IMEMT::zeroed().with_tag(tag), ); for word in block.chunks_exact(4) { let w = [word[0], word[1], word[2], word[3]]; bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_IMEMD::zeroed().with_data(u32::from_le_bytes(w)), + crate::regs::NV_PFALCON_FALCON_IMEMD::zeroed() + .with_data(u32::from_le_bytes(w)), ); } } @@ -458,7 +460,7 @@ fn pio_wr_dmem_slice( bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_DMEMC::zeroed() + crate::regs::NV_PFALCON_FALCON_DMEMC::zeroed() .with_aincw(true) .with_offs(load_offsets.dst_start), ); @@ -467,7 +469,8 @@ fn pio_wr_dmem_slice( let w = [word[0], word[1], word[2], word[3]]; bar.write( WithBase::of::<E>().at(Self::PIO_PORT), - regs::NV_PFALCON_FALCON_DMEMD::zeroed().with_data(u32::from_le_bytes(w)), + crate::regs::NV_PFALCON_FALCON_DMEMD::zeroed() + .with_data(u32::from_le_bytes(w)), ); } @@ -480,13 +483,13 @@ pub(crate) fn pio_load<F: FalconFirmware<Target = E> + FalconPioLoadable>( bar: Bar0<'_>, fw: &F, ) -> Result { - bar.update(regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { + bar.update(crate::regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { v.with_allow_phys_no_ctx(true) }); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMACTL::zeroed(), + crate::regs::NV_PFALCON_FALCON_DMACTL::zeroed(), ); if let Some(imem_ns) = fw.imem_ns_load_params() { @@ -501,7 +504,8 @@ pub(crate) fn pio_load<F: FalconFirmware<Target = E> + FalconPioLoadable>( bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_BOOTVEC::zeroed().with_value(fw.boot_addr()), + crate::regs::NV_PFALCON_FALCON_BOOTVEC::zeroed() + .with_value(fw.boot_addr()), ); Ok(()) @@ -573,7 +577,7 @@ fn dma_wr( bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFBASE::zeroed().with_base( + crate::regs::NV_PFALCON_FALCON_DMATRFBASE::zeroed().with_base( // CAST: `as u32` is used on purpose since we do want to strip the upper bits, // which will be written to `NV_PFALCON_FALCON_DMATRFBASE1`. (dma_start >> 8) as u32, @@ -581,10 +585,11 @@ fn dma_wr( ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFBASE1::zeroed().try_with_base(dma_start >> 40)?, + crate::regs::NV_PFALCON_FALCON_DMATRFBASE1::zeroed() + .try_with_base(dma_start >> 40)?, ); - let cmd = regs::NV_PFALCON_FALCON_DMATRFCMD::zeroed() + let cmd = crate::regs::NV_PFALCON_FALCON_DMATRFCMD::zeroed() .with_size(DmaTrfCmdSize::Size256B) .with_falcon_mem(target_mem); @@ -592,12 +597,13 @@ fn dma_wr( // Perform a transfer of size `DMA_LEN`. bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFMOFFS::zeroed() + crate::regs::NV_PFALCON_FALCON_DMATRFMOFFS::zeroed() .try_with_offs(load_offsets.dst_start + pos)?, ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_DMATRFFBOFFS::zeroed().with_offs(src_start + pos), + crate::regs::NV_PFALCON_FALCON_DMATRFFBOFFS::zeroed() + .with_offs(src_start + pos), ); bar.write(WithBase::of::<E>(), cmd); @@ -606,7 +612,7 @@ fn dma_wr( // TIMEOUT: arbitrarily large value, no DMA transfer to the falcon's small memories // should ever take that long. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_DMATRFCMD::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_DMATRFCMD::of::<E>())), |r| r.idle(), Delta::ZERO, Delta::from_secs(2), @@ -643,7 +649,7 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( }; self.dma_reset(bar); - bar.update(regs::NV_PFALCON_FBIF_TRANSCFG::of::<E>().at(0), |v| { + bar.update(crate::regs::NV_PFALCON_FBIF_TRANSCFG::of::<E>().at(0), |v| { v.with_target(FalconFbifTarget::CoherentSysmem) .with_mem_type(FalconFbifMemType::Physical) }); @@ -661,7 +667,8 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( // Set `BootVec` to start of non-secure code. bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_BOOTVEC::zeroed().with_value(fw.boot_addr()), + crate::regs::NV_PFALCON_FALCON_BOOTVEC::zeroed() + .with_value(fw.boot_addr()), ); Ok(()) @@ -671,7 +678,7 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( pub(crate) fn wait_till_halted(&self, bar: Bar0<'_>) -> Result<()> { // TIMEOUT: arbitrarily large value, firmwares should complete in less than 2 seconds. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_CPUCTL::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_CPUCTL::of::<E>())), |r| r.halted(), Delta::ZERO, Delta::from_secs(2), @@ -683,16 +690,18 @@ pub(crate) fn wait_till_halted(&self, bar: Bar0<'_>) -> Result<()> { /// Start the falcon CPU. pub(crate) fn start(&self, bar: Bar0<'_>) -> Result<()> { match bar - .read(regs::NV_PFALCON_FALCON_CPUCTL::of::<E>()) + .read(crate::regs::NV_PFALCON_FALCON_CPUCTL::of::<E>()) .alias_en() { true => bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_CPUCTL_ALIAS::zeroed().with_startcpu(true), + crate::regs::NV_PFALCON_FALCON_CPUCTL_ALIAS::zeroed() + .with_startcpu(true), ), false => bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_CPUCTL::zeroed().with_startcpu(true), + crate::regs::NV_PFALCON_FALCON_CPUCTL::zeroed() + .with_startcpu(true), ), } @@ -704,27 +713,29 @@ pub(crate) fn write_mailboxes(&self, bar: Bar0<'_>, mbox0: Option<u32>, mbox1: O if let Some(mbox0) = mbox0 { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_MAILBOX0::zeroed().with_value(mbox0), + crate::regs::NV_PFALCON_FALCON_MAILBOX0::zeroed() + .with_value(mbox0), ); } if let Some(mbox1) = mbox1 { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_MAILBOX1::zeroed().with_value(mbox1), + crate::regs::NV_PFALCON_FALCON_MAILBOX1::zeroed() + .with_value(mbox1), ); } } /// Reads the value from `mbox0` register. pub(crate) fn read_mailbox0(&self, bar: Bar0<'_>) -> u32 { - bar.read(regs::NV_PFALCON_FALCON_MAILBOX0::of::<E>()) + bar.read(crate::regs::NV_PFALCON_FALCON_MAILBOX0::of::<E>()) .value() } /// Reads the value from `mbox1` register. pub(crate) fn read_mailbox1(&self, bar: Bar0<'_>) -> u32 { - bar.read(regs::NV_PFALCON_FALCON_MAILBOX1::of::<E>()) + bar.read(crate::regs::NV_PFALCON_FALCON_MAILBOX1::of::<E>()) .value() } @@ -792,7 +803,7 @@ pub(crate) fn load<F: FalconFirmware<Target = E> + FalconDmaLoadable>( pub(crate) fn write_os_version(&self, bar: Bar0<'_>, app_version: u32) { bar.write( WithBase::of::<E>(), - regs::NV_PFALCON_FALCON_OS::zeroed().with_value(app_version), + crate::regs::NV_PFALCON_FALCON_OS::zeroed().with_value(app_version), ); } } diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs index cf6ce47e6b25..cc574fef0fbd 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -24,24 +24,25 @@ FalconBromParams, FalconEngine, FalconModSelAlgo, - PeregrineCoreSelect, // + PeregrineCoreSelect, + regs, // }, - regs, }; use super::FalconHal; fn select_core_ga102<E: FalconEngine>(bar: Bar0<'_>) -> Result { - let bcr_ctrl = bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); + let bcr_ctrl = bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); if bcr_ctrl.core_select() != PeregrineCoreSelect::Falcon { bar.write( WithBase::of::<E>(), - regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed().with_core_select(PeregrineCoreSelect::Falcon), + crate::regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed() + .with_core_select(PeregrineCoreSelect::Falcon), ); // TIMEOUT: falcon core should take less than 10ms to report being enabled. read_poll_timeout( - || Ok(bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), + || Ok(bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), |r| r.valid(), Delta::ZERO, Delta::from_millis(10), @@ -59,7 +60,7 @@ fn signature_reg_fuse_version_ga102( ) -> Result<u32> { // Each engine has 16 ucode version registers numbered from 1 to 16. let ucode_idx = match usize::from(ucode_id) { - ucode_id @ 1..=regs::NV_FUSE_OPT_FPF_SIZE => ucode_id - 1, + ucode_id @ 1..=crate::regs::NV_FUSE_OPT_FPF_SIZE => ucode_id - 1, _ => { dev_err!(dev, "invalid ucode id {:#x}\n", ucode_id); return Err(EINVAL); @@ -69,13 +70,13 @@ fn signature_reg_fuse_version_ga102( // `ucode_idx` is guaranteed to be in the range [0..15], making the `read` calls provable valid // at build-time. let reg_fuse_version: u16 = if engine_id_mask & 0x0001 != 0 { - bar.read(regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx)) + bar.read(crate::regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx)) .data() } else if engine_id_mask & 0x0004 != 0 { - bar.read(regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx)) + bar.read(crate::regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx)) .data() } else if engine_id_mask & 0x0400 != 0 { - bar.read(regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx)) + bar.read(crate::regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx)) .data() } else { dev_err!(dev, "unexpected engine_id_mask {:#x}\n", engine_id_mask); @@ -89,7 +90,8 @@ fn signature_reg_fuse_version_ga102( fn program_brom_ga102<E: FalconEngine>(bar: Bar0<'_>, params: &FalconBromParams) { bar.write( WithBase::of::<E>().at(0), - regs::NV_PFALCON2_FALCON_BROM_PARAADDR::zeroed().with_value(params.pkc_data_offset), + regs::NV_PFALCON2_FALCON_BROM_PARAADDR::zeroed() + .with_value(params.pkc_data_offset), ); bar.write( WithBase::of::<E>(), @@ -98,11 +100,13 @@ fn program_brom_ga102<E: FalconEngine>(bar: Bar0<'_>, params: &FalconBromParams) ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::zeroed().with_ucode_id(params.ucode_id), + regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::zeroed() + .with_ucode_id(params.ucode_id), ); bar.write( WithBase::of::<E>(), - regs::NV_PFALCON2_FALCON_MOD_SEL::zeroed().with_algo(FalconModSelAlgo::Rsa3k), + regs::NV_PFALCON2_FALCON_MOD_SEL::zeroed() + .with_algo(FalconModSelAlgo::Rsa3k), ); } @@ -134,14 +138,14 @@ fn program_brom(&self, _falcon: &Falcon<E>, bar: Bar0<'_>, params: &FalconBromPa } fn is_riscv_active(&self, bar: Bar0<'_>) -> bool { - bar.read(regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) + bar.read(crate::regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) .active_stat() } fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { // TIMEOUT: memory scrubbing should complete in less than 20ms. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), |r| r.mem_scrubbing_done(), Delta::ZERO, Delta::from_millis(20), @@ -150,18 +154,18 @@ fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { } fn reset_eng(&self, bar: Bar0<'_>) -> Result { - let _ = bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<E>()); + let _ = bar.read(crate::regs::NV_PFALCON_FALCON_HWCFG2::of::<E>()); // According to OpenRM's `kflcnPreResetWait_GA102` documentation, HW sometimes does not set // RESET_READY so a non-failing timeout is used. let _ = read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_HWCFG2::of::<E>())), |r| r.reset_ready(), Delta::ZERO, Delta::from_micros(150), ); - regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); + crate::regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); self.reset_wait_mem_scrubbing(bar)?; Ok(()) diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs new file mode 100644 index 000000000000..be8dbb599fc9 --- /dev/null +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::io::register; + +use crate::falcon::{ + PFalcon2Base, + FalconModSelAlgo, // +}; + +/* PFALCON2 */ + +register! { + pub(super) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 { + 7:0 algo ?=> FalconModSelAlgo; + } + + pub(super) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 { + 7:0 ucode_id => u8; + } + + pub(super) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c { + 31:0 value => u32; + } + + /// OpenRM defines this as a register array, but doesn't specify its size and only uses its + /// first element. Be conservative until we know the actual size or need to use more registers. + pub(super) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 { + 31:0 value => u32; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 59d36870b92b..0b048086f54f 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -22,7 +22,6 @@ FalconFbifMemType, FalconFbifTarget, FalconMem, - FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, PFalconBase, @@ -494,28 +493,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } -/* PFALCON2 */ - -register! { - pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 { - 7:0 algo ?=> FalconModSelAlgo; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 { - 7:0 ucode_id => u8; - } - - pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c { - 31:0 value => u32; - } - - /// OpenRM defines this as a register array, but doesn't specify its size and only uses its - /// first element. Be conservative until we know the actual size or need to use more registers. - pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 { - 31:0 value => u32; - } -} - // PRISCV register! { -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/5] gpu: nova-core: falcon: Move PFALCON2 register 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay (?) @ 2026-06-23 6:22 ` Alexandre Courbot -1 siblings, 0 replies; 17+ messages in thread From: Alexandre Courbot @ 2026-06-23 6:22 UTC (permalink / raw) To: Antonin Malzieu Ridolfi via B4 Relay Cc: dev, Danilo Krummrich, Alice Ryhl, David Airlie, Simona Vetter, linux-kernel, nova-gpu, dri-devel, daniel.almeida On Wed Jun 17, 2026 at 8:48 AM JST, Antonin Malzieu Ridolfi via B4 Relay wrote: > From: Antonin Malzieu Ridolfi <dev@nanonej.com> > > Move PFALCON2 register definition into falcon module and update registers > visibility. > > Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> > --- > drivers/gpu/nova-core/falcon.rs | 71 ++++++++++++++++++------------- > drivers/gpu/nova-core/falcon/hal/ga102.rs | 38 +++++++++-------- > drivers/gpu/nova-core/falcon/regs.rs | 30 +++++++++++++ > drivers/gpu/nova-core/regs.rs | 23 ---------- > 4 files changed, 92 insertions(+), 70 deletions(-) > > diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs > index 94c7696a6493..c2215ddd9e80 100644 > --- a/drivers/gpu/nova-core/falcon.rs > +++ b/drivers/gpu/nova-core/falcon.rs > @@ -37,12 +37,12 @@ > self, > FromSafeCast, // > }, > - regs, > }; > > pub(crate) mod fsp; > pub(crate) mod gsp; > mod hal; > +mod regs; > pub(crate) mod sec2; > > /// Alignment (in bytes) of falcon memory blocks. > @@ -99,7 +99,7 @@ pub(crate) enum FalconSecurityModel with TryFrom<Bounded<u32, 2>> { > > bounded_enum! { > /// Signing algorithm for a given firmware, used in the > - /// [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM > + /// [`super::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM > /// (BROM) as a parameter. > #[derive(Debug, Copy, Clone)] > pub(crate) enum FalconModSelAlgo with TryFrom<Bounded<u32, 8>> { > @@ -374,13 +374,13 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset) -> Result<Self> { > > /// Resets DMA-related registers. > pub(crate) fn dma_reset(&self, bar: Bar0<'_>) { > - bar.update(regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { > + bar.update(crate::regs::NV_PFALCON_FBIF_CTL::of::<E>(), |v| { It's a bit of a bummer that we need to rescope all these registers because a few have moved. I think we should try and take the same approach as patch 2, i.e. make sure each register is only used in one module by introducing the right abstractions, and move all the registers of that module in one go. The `falcon` module is definitely the most register-rich, so it's probably a good idea to keep it for last, unless you have the patience to check each of its registers one by one. (LSP can make the task easier though :)). ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/5] gpu: nova-core: falcon: Move PFALCON2 register 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay (?) (?) @ 2026-06-23 20:12 ` sashiko-bot -1 siblings, 0 replies; 17+ messages in thread From: sashiko-bot @ 2026-06-23 20:12 UTC (permalink / raw) To: Antonin Malzieu Ridolfi via B4 Relay Cc: Alexandre Courbot, dri-devel, Danilo Krummrich Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Broken intra-doc link for `FalconModSelAlgo` causes rustdoc build failures. -- commit 38e6d24ce9170693f7e3057866f61c8d872b90e3 Author: Antonin Malzieu Ridolfi <dev@nanonej.com> gpu: nova-core: falcon: Move PFALCON2 register This commit moves the PFALCON2 register definition into the falcon module and updates register visibility. > diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs > index 94c7696a64935..c2215ddd9e804 100644 > --- a/drivers/gpu/nova-core/falcon.rs > +++ b/drivers/gpu/nova-core/falcon.rs [ ... ] > @@ -99,7 +99,7 @@ pub(crate) enum FalconSecurityModel with TryFrom<Bounded<u32, 2>> { > > bounded_enum! { > /// Signing algorithm for a given firmware, used in the > - /// [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM > + /// [`super::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM [Severity: Low] This isn't a bug, but does this create a broken intra-doc link for rustdoc? Since this enum is in the falcon module, super::regs would resolve to crate::regs, but the register definition was just moved into the falcon module. Would it be better to use regs::NV_PFALCON2_FALCON_MOD_SEL instead to prevent rustdoc build warnings or failures? > /// (BROM) as a parameter. > #[derive(Debug, Copy, Clone)] > pub(crate) enum FalconModSelAlgo with TryFrom<Bounded<u32, 8>> { -- Sashiko AI review · https://sashiko.dev/#/patchset/20260617-nova-core-regs-split-v1-0-4c7dc4450ea7@nanonej.com?part=3 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/5] gpu: nova-core: falcon: Move PRISCV register 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay -1 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida Move PRISCV register definition into falcon module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/falcon/hal/ga102.rs | 8 ++++---- drivers/gpu/nova-core/falcon/hal/tu102.rs | 8 ++++---- drivers/gpu/nova-core/falcon/regs.rs | 27 ++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 28 +--------------------------- 4 files changed, 35 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs index cc574fef0fbd..3adfa8dd1cfb 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -32,17 +32,17 @@ use super::FalconHal; fn select_core_ga102<E: FalconEngine>(bar: Bar0<'_>) -> Result { - let bcr_ctrl = bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); + let bcr_ctrl = bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); if bcr_ctrl.core_select() != PeregrineCoreSelect::Falcon { bar.write( WithBase::of::<E>(), - crate::regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed() + regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed() .with_core_select(PeregrineCoreSelect::Falcon), ); // TIMEOUT: falcon core should take less than 10ms to report being enabled. read_poll_timeout( - || Ok(bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), + || Ok(bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), |r| r.valid(), Delta::ZERO, Delta::from_millis(10), @@ -138,7 +138,7 @@ fn program_brom(&self, _falcon: &Falcon<E>, bar: Bar0<'_>, params: &FalconBromPa } fn is_riscv_active(&self, bar: Bar0<'_>) -> bool { - bar.read(crate::regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) + bar.read(regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) .active_stat() } diff --git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-core/falcon/hal/tu102.rs index 3aaee3869312..1b06607e1ace 100644 --- a/drivers/gpu/nova-core/falcon/hal/tu102.rs +++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs @@ -18,9 +18,9 @@ hal::LoadMethod, Falcon, FalconBromParams, - FalconEngine, // + FalconEngine, + regs, // }, - regs, // }; use super::FalconHal; @@ -58,7 +58,7 @@ fn is_riscv_active(&self, bar: Bar0<'_>) -> bool { fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { // TIMEOUT: memory scrubbing should complete in less than 10ms. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_DMACTL::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_DMACTL::of::<E>())), |r| r.mem_scrubbing_done(), Delta::ZERO, Delta::from_millis(10), @@ -67,7 +67,7 @@ fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { } fn reset_eng(&self, bar: Bar0<'_>) -> Result { - regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); + crate::regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); self.reset_wait_mem_scrubbing(bar)?; Ok(()) diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs index be8dbb599fc9..4d4e69b235fc 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -4,7 +4,8 @@ use crate::falcon::{ PFalcon2Base, - FalconModSelAlgo, // + FalconModSelAlgo, + PeregrineCoreSelect, // }; /* PFALCON2 */ @@ -28,3 +29,27 @@ 31:0 value => u32; } } + +// PRISCV + +register! { + /// RISC-V status register for debug (Turing and GA100 only). + /// Reflects current RISC-V core status. + pub(super) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 { + /// RISC-V core active/inactive status. + 0:0 active_stat => bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { + 7:7 active_stat => bool; + 0:0 halted => bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { + 8:8 br_fetch => bool; + 4:4 core_select => PeregrineCoreSelect; + 0:0 valid => bool; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0b048086f54f..b21a5adc723a 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -23,9 +23,7 @@ FalconFbifTarget, FalconMem, FalconSecurityModel, - PFalcon2Base, - PFalconBase, - PeregrineCoreSelect, // + PFalconBase, // }, gpu::{ Architecture, @@ -493,30 +491,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } -// PRISCV - -register! { - /// RISC-V status register for debug (Turing and GA100 only). - /// Reflects current RISC-V core status. - pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 { - /// RISC-V core active/inactive status. - 0:0 active_stat => bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { - 7:7 active_stat => bool; - 0:0 halted => bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { - 8:8 br_fetch => bool; - 4:4 core_select => PeregrineCoreSelect; - 0:0 valid => bool; - } -} - // FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. // These registers manage falcon EMEM communication queues. -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/5] gpu: nova-core: falcon: Move PRISCV register @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 0 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida From: Antonin Malzieu Ridolfi <dev@nanonej.com> Move PRISCV register definition into falcon module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/falcon/hal/ga102.rs | 8 ++++---- drivers/gpu/nova-core/falcon/hal/tu102.rs | 8 ++++---- drivers/gpu/nova-core/falcon/regs.rs | 27 ++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 28 +--------------------------- 4 files changed, 35 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs index cc574fef0fbd..3adfa8dd1cfb 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -32,17 +32,17 @@ use super::FalconHal; fn select_core_ga102<E: FalconEngine>(bar: Bar0<'_>) -> Result { - let bcr_ctrl = bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); + let bcr_ctrl = bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>()); if bcr_ctrl.core_select() != PeregrineCoreSelect::Falcon { bar.write( WithBase::of::<E>(), - crate::regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed() + regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed() .with_core_select(PeregrineCoreSelect::Falcon), ); // TIMEOUT: falcon core should take less than 10ms to report being enabled. read_poll_timeout( - || Ok(bar.read(crate::regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), + || Ok(bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::<E>())), |r| r.valid(), Delta::ZERO, Delta::from_millis(10), @@ -138,7 +138,7 @@ fn program_brom(&self, _falcon: &Falcon<E>, bar: Bar0<'_>, params: &FalconBromPa } fn is_riscv_active(&self, bar: Bar0<'_>) -> bool { - bar.read(crate::regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) + bar.read(regs::NV_PRISCV_RISCV_CPUCTL::of::<E>()) .active_stat() } diff --git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-core/falcon/hal/tu102.rs index 3aaee3869312..1b06607e1ace 100644 --- a/drivers/gpu/nova-core/falcon/hal/tu102.rs +++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs @@ -18,9 +18,9 @@ hal::LoadMethod, Falcon, FalconBromParams, - FalconEngine, // + FalconEngine, + regs, // }, - regs, // }; use super::FalconHal; @@ -58,7 +58,7 @@ fn is_riscv_active(&self, bar: Bar0<'_>) -> bool { fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { // TIMEOUT: memory scrubbing should complete in less than 10ms. read_poll_timeout( - || Ok(bar.read(regs::NV_PFALCON_FALCON_DMACTL::of::<E>())), + || Ok(bar.read(crate::regs::NV_PFALCON_FALCON_DMACTL::of::<E>())), |r| r.mem_scrubbing_done(), Delta::ZERO, Delta::from_millis(10), @@ -67,7 +67,7 @@ fn reset_wait_mem_scrubbing(&self, bar: Bar0<'_>) -> Result { } fn reset_eng(&self, bar: Bar0<'_>) -> Result { - regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); + crate::regs::NV_PFALCON_FALCON_ENGINE::reset_engine::<E>(bar); self.reset_wait_mem_scrubbing(bar)?; Ok(()) diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs index be8dbb599fc9..4d4e69b235fc 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -4,7 +4,8 @@ use crate::falcon::{ PFalcon2Base, - FalconModSelAlgo, // + FalconModSelAlgo, + PeregrineCoreSelect, // }; /* PFALCON2 */ @@ -28,3 +29,27 @@ 31:0 value => u32; } } + +// PRISCV + +register! { + /// RISC-V status register for debug (Turing and GA100 only). + /// Reflects current RISC-V core status. + pub(super) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 { + /// RISC-V core active/inactive status. + 0:0 active_stat => bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { + 7:7 active_stat => bool; + 0:0 halted => bool; + } + + /// GA102 and later. + pub(super) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { + 8:8 br_fetch => bool; + 4:4 core_select => PeregrineCoreSelect; + 0:0 valid => bool; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 0b048086f54f..b21a5adc723a 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -23,9 +23,7 @@ FalconFbifTarget, FalconMem, FalconSecurityModel, - PFalcon2Base, - PFalconBase, - PeregrineCoreSelect, // + PFalconBase, // }, gpu::{ Architecture, @@ -493,30 +491,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } -// PRISCV - -register! { - /// RISC-V status register for debug (Turing and GA100 only). - /// Reflects current RISC-V core status. - pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 { - /// RISC-V core active/inactive status. - 0:0 active_stat => bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { - 7:7 active_stat => bool; - 0:0 halted => bool; - } - - /// GA102 and later. - pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { - 8:8 br_fetch => bool; - 4:4 core_select => PeregrineCoreSelect; - 0:0 valid => bool; - } -} - // FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. // These registers manage falcon EMEM communication queues. -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/5] gpu: nova-core: falcon: Move PFSP register 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay -1 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida Move PFSP register definition into falcon module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/falcon/fsp.rs | 14 +++++++------- drivers/gpu/nova-core/falcon/regs.rs | 21 +++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 21 --------------------- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs index 52cdb84ef0e8..547843e6483c 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -26,10 +26,10 @@ Falcon, FalconEngine, PFalcon2Base, - PFalconBase, // + PFalconBase, + regs, // }, - num, - regs, // + num, // }; /// FSP message timeout in milliseconds. @@ -61,7 +61,7 @@ fn write_emem(&mut self, bar: Bar0<'_>, data: &[u8]) -> Result { // Begin a write burst at offset `0`, auto-incrementing on each write. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincw(true), + crate::regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincw(true), ); for chunk in data.chunks_exact(4) { @@ -70,7 +70,7 @@ fn write_emem(&mut self, bar: Bar0<'_>, data: &[u8]) -> Result { // Write the next 32-bit `value`; hardware advances the offset. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMD::zeroed().with_data(value), + crate::regs::NV_PFALCON_FALCON_EMEMD::zeroed().with_data(value), ); } @@ -89,12 +89,12 @@ fn read_emem(&mut self, bar: Bar0<'_>, data: &mut [u8]) -> Result { // Begin a read burst at offset `0`, auto-incrementing on each read. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincr(true), + crate::regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincr(true), ); for chunk in data.chunks_exact_mut(4) { // Read the next 32-bit word; hardware advances the offset. - let value = bar.read(regs::NV_PFALCON_FALCON_EMEMD::of::<Fsp>()).data(); + let value = bar.read(crate::regs::NV_PFALCON_FALCON_EMEMD::of::<Fsp>()).data(); chunk.copy_from_slice(&value.to_le_bytes()); } diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs index 4d4e69b235fc..81530abfb54c 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -53,3 +53,24 @@ 0:0 valid => bool; } } + +// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. +// These registers manage falcon EMEM communication queues. + +register! { + pub(super) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { + 31:0 address => u32; + } + + pub(super) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { + 31:0 address => u32; + } + + pub(super) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { + 31:0 val => u32; + } + + pub(super) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { + 31:0 val => u32; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b21a5adc723a..9069aeff1ee4 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -491,27 +491,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } -// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. -// These registers manage falcon EMEM communication queues. - -register! { - pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { - 31:0 address => u32; - } - - pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { - 31:0 address => u32; - } - - pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { - 31:0 val => u32; - } - - pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { - 31:0 val => u32; - } -} - // The modules below provide registers that are not identical on all supported chips. They should // only be used in HAL modules. -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/5] gpu: nova-core: falcon: Move PFSP register @ 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 0 siblings, 0 replies; 17+ messages in thread From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-06-16 23:48 UTC (permalink / raw) To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie, Simona Vetter, Antonin Malzieu Ridolfi Cc: linux-kernel, nova-gpu, dri-devel, daniel.almeida From: Antonin Malzieu Ridolfi <dev@nanonej.com> Move PFSP register definition into falcon module and update registers visibility. Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com> --- drivers/gpu/nova-core/falcon/fsp.rs | 14 +++++++------- drivers/gpu/nova-core/falcon/regs.rs | 21 +++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 21 --------------------- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs index 52cdb84ef0e8..547843e6483c 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -26,10 +26,10 @@ Falcon, FalconEngine, PFalcon2Base, - PFalconBase, // + PFalconBase, + regs, // }, - num, - regs, // + num, // }; /// FSP message timeout in milliseconds. @@ -61,7 +61,7 @@ fn write_emem(&mut self, bar: Bar0<'_>, data: &[u8]) -> Result { // Begin a write burst at offset `0`, auto-incrementing on each write. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincw(true), + crate::regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincw(true), ); for chunk in data.chunks_exact(4) { @@ -70,7 +70,7 @@ fn write_emem(&mut self, bar: Bar0<'_>, data: &[u8]) -> Result { // Write the next 32-bit `value`; hardware advances the offset. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMD::zeroed().with_data(value), + crate::regs::NV_PFALCON_FALCON_EMEMD::zeroed().with_data(value), ); } @@ -89,12 +89,12 @@ fn read_emem(&mut self, bar: Bar0<'_>, data: &mut [u8]) -> Result { // Begin a read burst at offset `0`, auto-incrementing on each read. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincr(true), + crate::regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincr(true), ); for chunk in data.chunks_exact_mut(4) { // Read the next 32-bit word; hardware advances the offset. - let value = bar.read(regs::NV_PFALCON_FALCON_EMEMD::of::<Fsp>()).data(); + let value = bar.read(crate::regs::NV_PFALCON_FALCON_EMEMD::of::<Fsp>()).data(); chunk.copy_from_slice(&value.to_le_bytes()); } diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs index 4d4e69b235fc..81530abfb54c 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -53,3 +53,24 @@ 0:0 valid => bool; } } + +// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. +// These registers manage falcon EMEM communication queues. + +register! { + pub(super) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { + 31:0 address => u32; + } + + pub(super) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { + 31:0 address => u32; + } + + pub(super) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { + 31:0 val => u32; + } + + pub(super) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { + 31:0 val => u32; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b21a5adc723a..9069aeff1ee4 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -491,27 +491,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } -// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. -// These registers manage falcon EMEM communication queues. - -register! { - pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { - 31:0 address => u32; - } - - pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { - 31:0 address => u32; - } - - pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { - 31:0 val => u32; - } - - pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { - 31:0 val => u32; - } -} - // The modules below provide registers that are not identical on all supported chips. They should // only be used in HAL modules. -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] gpu: nova-core: falcon: Move PFSP register 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay (?) @ 2026-06-23 20:24 ` sashiko-bot -1 siblings, 0 replies; 17+ messages in thread From: sashiko-bot @ 2026-06-23 20:24 UTC (permalink / raw) To: Antonin Malzieu Ridolfi via B4 Relay Cc: Alexandre Courbot, dri-devel, Danilo Krummrich Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: New issues: - [Low] The commit modifies import statements without migrating them to the kernel's vertical import style. Pre-existing issues: - [High] FSP queue registers are defined as arrays of 8 elements without a `stride` parameter, defaulting to a 4-byte stride which silently overlaps with adjacent registers. - [High] Unbounded allocation in `recv_msg` based on untrusted hardware input can trigger an Out-of-Memory (OOM) condition or kernel panic. -- commit 2170d35504c32c252c52eca31b351aad8e873b56 Author: Antonin Malzieu Ridolfi <dev@nanonej.com> gpu: nova-core: falcon: Move PFSP register This patch moves the PFSP register definitions into the falcon module and updates the registers' visibility. > diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs > index 52cdb84ef0e80..547843e6483c6 100644 > --- a/drivers/gpu/nova-core/falcon/fsp.rs > +++ b/drivers/gpu/nova-core/falcon/fsp.rs > @@ -26,10 +26,10 @@ > Falcon, > FalconEngine, > PFalcon2Base, > - PFalconBase, // > + PFalconBase, > + regs, // > }, > - num, > - regs, // > + num, // > }; [Severity: Low] Does this import block need to be updated to match the kernel vertical import style? The Rust subsystem coding guidelines require flattening nested imports when they are modified. [ ... ] > diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs > index 4d4e69b235fc6..81530abfb54c3 100644 > --- a/drivers/gpu/nova-core/falcon/regs.rs > +++ b/drivers/gpu/nova-core/falcon/regs.rs [ ... ] > +register! { > + pub(super) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { > + 31:0 address => u32; > + } > + > + pub(super) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { > + 31:0 address => u32; > + } [Severity: High] This is a pre-existing issue, but does NV_PFSP_QUEUE_HEAD need a stride parameter? Since the elements are 4 bytes, omitting the stride defaults it to 4 bytes. This would place index 1 of NV_PFSP_QUEUE_HEAD at 0x008f2c04, which overlaps with NV_PFSP_QUEUE_TAIL. Should this be defined as [8, stride = 8] to prevent accessing the wrong register for indices > 0? [ ... ] [Severity: High] This isn't a bug introduced by this patch, but is there an unbounded allocation risk in recv_msg()? Looking at fsp.rs, poll_msgq() derives the message size directly from the hardware MMIO registers without bounds checking: tail.saturating_sub(head).saturating_add(4) This untrusted size is then used to allocate kernel memory: drivers/gpu/nova-core/falcon/fsp.rs:recv_msg() { ... let mut buffer = KVec::<u8>::new(); buffer.resize(msg_size, 0, GFP_KERNEL)?; ... } Could a compromised or misbehaving FSP firmware provide a massive message size, exhausting kernel memory and triggering an OOM condition? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260617-nova-core-regs-split-v1-0-4c7dc4450ea7@nanonej.com?part=5 ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2026-06-23 20:24 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-16 23:48 [PATCH 0/5] gpu: nova-core: Move registers definitions Antonin Malzieu Ridolfi 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 2026-06-16 23:48 ` [PATCH 1/5] gpu: nova-core: fb: Move PDISP register definition Antonin Malzieu Ridolfi 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 2026-06-23 6:18 ` Alexandre Courbot 2026-06-16 23:48 ` [PATCH 2/5] gpu: nova-core: gsp: Move PBUS " Antonin Malzieu Ridolfi 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 2026-06-23 6:18 ` Alexandre Courbot 2026-06-16 23:48 ` [PATCH 3/5] gpu: nova-core: falcon: Move PFALCON2 register Antonin Malzieu Ridolfi 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 2026-06-23 6:22 ` Alexandre Courbot 2026-06-23 20:12 ` sashiko-bot 2026-06-16 23:48 ` [PATCH 4/5] gpu: nova-core: falcon: Move PRISCV register Antonin Malzieu Ridolfi 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 2026-06-16 23:48 ` [PATCH 5/5] gpu: nova-core: falcon: Move PFSP register Antonin Malzieu Ridolfi 2026-06-16 23:48 ` Antonin Malzieu Ridolfi via B4 Relay 2026-06-23 20:24 ` sashiko-bot
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