[PATCH 6.18.y] Revert "PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support"

[PATCH 6.18.y] Revert "PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support"

[Manivannan Sadhasivam]

This reverts commit f176c47683bf6365e2f6d580d557fae49169a703.

When the Qcom PCIe Root Port advertises itself as hotplug capable, the
PCI core pre-allocates a conservative 2MB non-prefetchable bridge window
with 1MB alignment during the initial bus scan. However, the WLAN device
(17cb:1103) on the ThinkPad X13s requires a 2MB BAR with 2MB alignment,
which cannot be satisfied from within the pre-allocated bridge window.
This causes the device to fail enumeration:

  ath11k_pci 0006:01:00.0: BAR 0 [mem size 0x00200000 64bit]: can't assign; no space
  ath11k_pci 0006:01:00.0: BAR 0 [??? 0x00000000 flags 0x20000000]: can't assign; bogus alignment
  ath11k_pci 0006:01:00.0: failed to assign pci resource: -22
  ath11k_pci 0006:01:00.0: failed to claim device: -22
  ath11k_pci 0006:01:00.0: probe with driver ath11k_pci failed with error -22

Before this commit, the bridge was not marked hotplug capable, so the PCI
core deferred resource allocation until the device appeared on the bus
during rescan, at which point the BAR was correctly sized and aligned.

On mainline kernel and recent stable kernels, (v7.0+), this regression is
masked by a set of changes in the pwrctrl core that defers PCIe controller
probe until the endpoint driver is ready, ensuring the endpoint is visible
on the bus when bridge resources are first allocated. But those changes
cannot be backported as they are not bug fixes.

So simply revert the offending commit to restore the wireless functionality
on the Qcom platforms.

Reported-by: Paul Guder <paul.guder@example.com>
Closes: https://lore.kernel.org/linux-pci/CAH-zrtu1Bci7M-tQc9Vme9z+Bw=1gthM7z6=XX33Jjd_Q6itcg@mail.gmail.com
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 43555ad9e5dc..789cc0e3c10d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -341,20 +341,15 @@ static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
 	dw_pcie_dbi_ro_wr_dis(pci);
 }
 
-static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci)
+static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
 {
 	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	u32 val;
 
 	dw_pcie_dbi_ro_wr_en(pci);
 
-	/*
-	 * Qcom PCIe Root Ports do not support generating command completion
-	 * notifications for the Hot-Plug commands. So set the NCCS field to
-	 * avoid waiting for the completions.
-	 */
 	val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
-	val |= PCI_EXP_SLTCAP_NCCS;
+	val &= ~PCI_EXP_SLTCAP_HPC;
 	writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
 	dw_pcie_dbi_ro_wr_dis(pci);
@@ -554,7 +549,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
 	writel(CFG_BRIDGE_SB_INIT,
 	       pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
 
-	qcom_pcie_set_slot_nccs(pcie->pci);
+	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;
 }
@@ -634,7 +629,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
 	}
 
-	qcom_pcie_set_slot_nccs(pcie->pci);
+	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;
 }
@@ -727,7 +722,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
 	val |= EN;
 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 
-	qcom_pcie_set_slot_nccs(pcie->pci);
+	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;
 }
@@ -1033,7 +1028,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
 		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
 
-	qcom_pcie_set_slot_nccs(pcie->pci);
+	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;
 }
-- 
2.51.0

Re: [PATCH 6.18.y] Revert "PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support"

[sashiko-bot]

> This reverts commit f176c47683bf6365e2f6d580d557fae49169a703.
> 
> When the Qcom PCIe Root Port advertises itself as hotplug capable, the
> PCI core pre-allocates a conservative 2MB non-prefetchable bridge window
> with 1MB alignment during the initial bus scan. However, the WLAN device
> (17cb:1103) on the ThinkPad X13s requires a 2MB BAR with 2MB alignment,
> which cannot be satisfied from within the pre-allocated bridge window.
> This causes the device to fail enumeration:
> 
>   ath11k_pci 0006:01:00.0: BAR 0 [mem size 0x00200000 64bit]: can't assign; no space
>   ath11k_pci 0006:01:00.0: BAR 0 [??? 0x00000000 flags 0x20000000]: can't assign; bogus alignment
>   ath11k_pci 0006:01:00.0: failed to assign pci resource: -22
>   ath11k_pci 0006:01:00.0: failed to claim device: -22
>   ath11k_pci 0006:01:00.0: probe with driver ath11k_pci failed with error -22
> 
> [ ... ]
> on the Qcom platforms.
> 
> Reported-by: Paul Guder <paul.guder@example.com>
> Closes: https://lore.kernel.org/linux-pci/CAH-zrtu1Bci7M-tQc9Vme9z+Bw=1gthM7z6=XX33Jjd_Q6itcg@mail.gmail.com
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260627080702.11517-1-manivannan.sadhasivam@oss.qualcomm.com?part=1

Re: [PATCH 6.18.y] Revert "PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support"

[Sasha Levin]

On Sat, 27 Jun 2026 13:37 +0530, Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> wrote:
> [PATCH 6.18.y] Revert "PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support"

Queued for 6.18.

-- 
Thanks,
Sasha