Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The pinctrl_cmgp controller and its first child bank gpm0 both claim the exact same GIC interrupt (SPI 114), and the driver configuration is fundamentally broken for CMGP interrupts.
- [Medium] The asymmetric big.LITTLE CPU topology (Cortex-A520 and Cortex-A720) is missing CPU capacity definitions.
--

commit 46c39da58bc865179bf89eb7be4c747cacdd7227
Author: Alim Akhtar <alim.akhtar@samsung.com>

arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk

This commit adds initial devicetree support for the Samsung SMDK board using
the Exynos8855 SoC. The SoC features an Octa-core CPU with a tri-cluster
architecture, a custom GPU, and an NPU supporting up to 14.7 TOPS.

Link: https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/

> diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> new file mode 100644
> index 0000000000000..b65f1698cd74a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
[ ... ]
> +&pinctrl_cmgp {
> +	gpm0: gpm0-gpio-bank {
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +	};

[Severity: High]
Does this child bank gpm0 claim the exact same SPI 114 interrupt as its
parent pinctrl_cmgp node?

If the child explicitly requests SPI 114 here, it might create an IRQ
resource conflict with the parent.

[ ... ]
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> new file mode 100644
> index 0000000000000..9d82fceb5130a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
[ ... ]
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;

[Severity: Medium]
Will the Energy Aware Scheduler function properly without the
capacity-dmips-mhz property defined here for the asymmetric Cortex-A520 and
Cortex-A720 nodes?

Without this property and lacking OPP tables, the scheduler might assume a
symmetric topology, which could cause it to schedule heavy tasks on the
small A520 cores or background tasks on the big A720 cores.

[ ... ]
> +		pinctrl_cmgp: pinctrl@12030000 {
> +			compatible = "samsung,exynos8855-pinctrl";
> +			reg = <0x12030000 0x1000>;
> +			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +		};

[Severity: High]
Could claiming GIC_SPI 114 here in the parent node lead to initialization
failures for CMGP interrupts?

The Exynos driver configures CMGP to use exynos_eint_gpio_init, which
expects a single demultiplexed IRQ on the parent. However, the gpm banks
are Wakeup EINTs with direct per-bank GIC interrupts (like the SPI 114
requested by gpm0).

Because exynos_eint_gpio_init skips EINT_TYPE_WKUP banks, the parent
successfully claims SPI 114 for a non-functional demux handler, blocking
gpm0. Any peripheral attempting to map an interrupt from a CMGP bank might
fail to probe. Should this instead have a wakeup-interrupt-controller
child node without claiming a parent interrupt?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260627171228.2687857-1-alim.akhtar@samsung.com?part=5