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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org, stefanha@redhat.com, peter.maydell@linaro.org
Cc: brian.cain@oss.qualcomm.com, Brian Cain <bcain@quicinc.com>,
	Taylor Simpson <ltaylorsimpson@gmail.com>,
	Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PULL v5 27/77] target/hexagon: Add sysemu TCG overrides
Date: Mon, 29 Jun 2026 06:11:42 -0700	[thread overview]
Message-ID: <20260629131232.2487780-28-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260629131232.2487780-1-brian.cain@oss.qualcomm.com>

From: Brian Cain <bcain@quicinc.com>

Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}).

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/cpu_helper.h  | 18 ++++++++++++
 target/hexagon/gen_tcg_sys.h | 55 ++++++++++++++++++++++++++++++++++++
 target/hexagon/helper.h      |  1 +
 target/hexagon/genptr.c      |  4 +++
 target/hexagon/op_helper.c   |  9 +++++-
 target/hexagon/hex_common.py |  2 ++
 target/hexagon/meson.build   | 13 +++++----
 7 files changed, 95 insertions(+), 7 deletions(-)
 create mode 100644 target/hexagon/cpu_helper.h
 create mode 100644 target/hexagon/gen_tcg_sys.h

diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
new file mode 100644
index 00000000000..75a28fc10f9
--- /dev/null
+++ b/target/hexagon/cpu_helper.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HEXAGON_CPU_HELPER_H
+#define HEXAGON_CPU_HELPER_H
+
+uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index);
+uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env);
+uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env);
+uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env);
+void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val);
+void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t val);
+void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t val);
+
+#endif
diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h
new file mode 100644
index 00000000000..f78c9635c3f
--- /dev/null
+++ b/target/hexagon/gen_tcg_sys.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HEXAGON_GEN_TCG_SYS_H
+#define HEXAGON_GEN_TCG_SYS_H
+
+#define fGEN_TCG_Y2_setprio(SHORTCODE) \
+    gen_helper_setprio(tcg_env, PtV, RsV)
+
+#define fGEN_TCG_Y2_crswap0(SHORTCODE) \
+    do { \
+        TCGv_i32 tmp = tcg_temp_new_i32(); \
+        tcg_gen_mov_tl(tmp, RxV); \
+        tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP0]); \
+        if (ctx->need_commit) { \
+            tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \
+        } else { \
+            tcg_gen_mov_tl(hex_t_sreg[HEX_SREG_SGP0], tmp); \
+        } \
+    } while (0)
+
+#define fGEN_TCG_Y4_crswap1(SHORTCODE) \
+    do { \
+        TCGv_i32 tmp = tcg_temp_new_i32(); \
+        tcg_gen_mov_tl(tmp, RxV); \
+        tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP1]); \
+        if (ctx->need_commit) { \
+            tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \
+        } else { \
+            tcg_gen_mov_tl(hex_t_sreg[HEX_SREG_SGP1], tmp); \
+        } \
+    } while (0)
+
+#define fGEN_TCG_Y4_crswap10(SHORTCODE) \
+    do { \
+        TCGv_i64 tmp = tcg_temp_new_i64(); \
+        tcg_gen_mov_i64(tmp, RxxV); \
+        tcg_gen_concat_i32_i64(RxxV, \
+                               hex_t_sreg[HEX_SREG_SGP0], \
+                               hex_t_sreg[HEX_SREG_SGP1]); \
+        if (ctx->need_commit) { \
+            tcg_gen_extrl_i64_i32( \
+                ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \
+            tcg_gen_extrh_i64_i32( \
+                ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \
+        } else { \
+            tcg_gen_extrl_i64_i32(hex_t_sreg[HEX_SREG_SGP0], tmp); \
+            tcg_gen_extrh_i64_i32(hex_t_sreg[HEX_SREG_SGP1], tmp); \
+        } \
+    } while (0)
+
+#endif
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 28b9b59e0f2..5405342f798 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -114,4 +114,5 @@ DEF_HELPER_2(sreg_read_pair, i64, env, i32)
 DEF_HELPER_2(greg_read, i32, env, i32)
 DEF_HELPER_2(greg_read_pair, i64, env, i32)
 DEF_HELPER_3(sreg_write_masked, void, env, i32, i32)
+DEF_HELPER_3(setprio, void, env, i32, i32)
 #endif
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 8f191f80619..ee69feae4b0 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -31,6 +31,10 @@
 #undef QEMU_GENERATE
 #include "gen_tcg.h"
 #include "gen_tcg_hvx.h"
+#ifndef CONFIG_USER_ONLY
+#include "gen_tcg_sys.h"
+#endif
+
 #include "genptr.h"
 
 TCGv gen_read_reg(TCGv result, int num)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 0f43a666341..3236ce0c8f0 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -20,9 +20,9 @@
 #include "accel/tcg/cpu-ldst.h"
 #include "accel/tcg/cpu-loop.h"
 #include "accel/tcg/probe.h"
+#include "cpu.h"
 #include "exec/helper-proto.h"
 #include "fpu/softfloat.h"
-#include "cpu.h"
 #include "internal.h"
 #include "macros.h"
 #include "sys_macros.h"
@@ -32,6 +32,7 @@
 #include "mmvec/mmvec.h"
 #include "mmvec/macros.h"
 #include "op_helper.h"
+#include "cpu_helper.h"
 #include "translate.h"
 #ifndef CONFIG_USER_ONLY
 #include "hexswi.h"
@@ -1413,6 +1414,12 @@ uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg)
 {
     g_assert_not_reached();
 }
+
+void HELPER(setprio)(CPUHexagonState *env, uint32_t thread, uint32_t prio)
+{
+    g_assert_not_reached();
+}
+
 #endif
 
 
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index b555e2b663b..8c6a0589f88 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -1369,6 +1369,7 @@ def parse_common_args(desc):
     parser.add_argument("semantics", help="semantics file")
     parser.add_argument("overrides", help="overrides file")
     parser.add_argument("overrides_vec", help="vector overrides file")
+    parser.add_argument("overrides_sys", help="system overrides file")
     parser.add_argument("out", help="output file")
     parser.add_argument("--idef-parser",
                         help="file of instructions translated by idef-parser")
@@ -1376,6 +1377,7 @@ def parse_common_args(desc):
     read_semantics_file(args.semantics)
     read_overrides_file(args.overrides)
     read_overrides_file(args.overrides_vec)
+    read_overrides_file(args.overrides_sys)
     if args.idef_parser:
         read_idef_parser_enabled_file(args.idef_parser)
     calculate_attribs()
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index ff22b4e4706..fd3d69feffd 100644
--- a/target/hexagon/meson.build
+++ b/target/hexagon/meson.build
@@ -20,6 +20,7 @@ hexagon_ss = ss.source_set()
 hex_common_py = 'hex_common.py'
 gen_tcg_h = meson.current_source_dir() / 'gen_tcg.h'
 gen_tcg_hvx_h = meson.current_source_dir() / 'gen_tcg_hvx.h'
+gen_tcg_sys_h = meson.current_source_dir() / 'gen_tcg_sys.h'
 idef_parser_dir = meson.current_source_dir() / 'idef-parser'
 
 #
@@ -337,12 +338,12 @@ if idef_parser_enabled and 'hexagon-linux-user' in target_dirs
     # Setup input and dependencies for the next step, this depends on whether or
     # not idef-parser is enabled
     helper_dep = [semantics_generated, idef_generated_tcg_c, idef_generated_tcg]
-    helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, '--idef-parser', idef_generated_list]
+    helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h, '--idef-parser', idef_generated_list]
 else
     # Setup input and dependencies for the next step, this depends on whether or
     # not idef-parser is enabled
     helper_dep = [semantics_generated]
-    helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h]
+    helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h]
 endif
 
 #
@@ -356,7 +357,7 @@ helper_protos_generated = custom_target(
     'helper_protos_generated.h.inc',
     output: 'helper_protos_generated.h.inc',
     depends: helper_dep,
-    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
     command: [python, files('gen_helper_protos.py'), helper_in, '@OUTPUT@'],
 )
 hexagon_ss.add(helper_protos_generated)
@@ -365,7 +366,7 @@ helper_funcs_generated = custom_target(
     'helper_funcs_generated.c.inc',
     output: 'helper_funcs_generated.c.inc',
     depends: helper_dep,
-    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
     command: [python, files('gen_helper_funcs.py'), helper_in, '@OUTPUT@'],
 )
 hexagon_ss.add(helper_funcs_generated)
@@ -374,7 +375,7 @@ tcg_funcs_generated = custom_target(
     'tcg_funcs_generated.c.inc',
     output: 'tcg_funcs_generated.c.inc',
     depends: helper_dep,
-    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
     command: [python, files('gen_tcg_funcs.py'), helper_in, '@OUTPUT@'],
 )
 hexagon_ss.add(tcg_funcs_generated)
@@ -383,7 +384,7 @@ analyze_funcs_generated = custom_target(
     'analyze_funcs_generated.c.inc',
     output: 'analyze_funcs_generated.c.inc',
     depends: helper_dep,
-    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+    depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
     command: [python, files('gen_analyze_funcs.py'), helper_in, '@OUTPUT@'],
 )
 hexagon_ss.add(analyze_funcs_generated)
-- 
2.34.1


  parent reply	other threads:[~2026-06-29 13:16 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-29 13:11 [PULL v5 00/77] hex queue Brian Cain
2026-06-29 13:11 ` [PULL v5 01/77] tests/docker: add flex and bison to emsdk-wasm64-cross Brian Cain
2026-06-29 13:11 ` [PULL v5 02/77] configs/meson: disable hexagon idef-parser for emscripten builds Brian Cain
2026-06-29 13:11 ` [PULL v5 03/77] target/hexagon: use cmd_array() instead of get_id() Brian Cain
2026-06-29 13:11 ` [PULL v5 04/77] target/hexagon/idef-parser: open input file in binary mode Brian Cain
2026-06-29 13:11 ` [PULL v5 05/77] docs: Add hexagon sysemu docs Brian Cain
2026-06-29 13:11 ` [PULL v5 06/77] docs/system: Add hexagon CPU emulation Brian Cain
2026-06-29 13:11 ` [PULL v5 07/77] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-06-29 13:11 ` [PULL v5 08/77] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-06-29 13:11 ` [PULL v5 09/77] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-06-29 13:11 ` [PULL v5 10/77] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-06-29 13:11 ` [PULL v5 11/77] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain
2026-06-29 13:11 ` [PULL v5 12/77] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-06-29 13:11 ` [PULL v5 13/77] target/hexagon: Add a placeholder fp exception Brian Cain
2026-06-29 13:11 ` [PULL v5 14/77] target/hexagon: Add guest, system reg number defs Brian Cain
2026-06-29 13:11 ` [PULL v5 15/77] target/hexagon: Add guest, system reg number state Brian Cain
2026-06-29 13:11 ` [PULL v5 16/77] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-06-29 13:11 ` [PULL v5 17/77] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-06-29 13:11 ` [PULL v5 18/77] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-06-29 13:11 ` [PULL v5 19/77] target/hexagon: Add new macro definitions " Brian Cain
2026-06-29 13:11 ` [PULL v5 20/77] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-06-29 13:11 ` [PULL v5 21/77] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 22/77] target/hexagon: Add vmstate representation Brian Cain
2026-06-29 13:11 ` [PULL v5 23/77] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-06-29 13:11 ` [PULL v5 24/77] target/hexagon: Define register fields for system regs Brian Cain
2026-06-29 13:11 ` [PULL v5 25/77] target/hexagon: Implement do_raise_exception() Brian Cain
2026-06-29 13:11 ` [PULL v5 26/77] target/hexagon: Add system reg insns Brian Cain
2026-06-29 13:11 ` Brian Cain [this message]
2026-06-29 13:11 ` [PULL v5 28/77] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-06-29 13:11 ` [PULL v5 29/77] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-06-29 13:11 ` [PULL v5 30/77] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-06-29 13:11 ` [PULL v5 31/77] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-06-29 13:11 ` [PULL v5 32/77] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 33/77] target/hexagon: Add representation to count cycles Brian Cain
2026-06-29 13:11 ` [PULL v5 34/77] target/hexagon: Add implementation of cycle counters Brian Cain
2026-06-29 13:11 ` [PULL v5 35/77] target/hexagon: Add pcycle setting functionality Brian Cain
2026-06-29 13:11 ` [PULL v5 36/77] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-06-29 13:11 ` [PULL v5 37/77] hw/hexagon: Declare hexagon TLB device interface Brian Cain
2026-06-29 13:11 ` [PULL v5 38/77] target/hexagon: Update TARGET_PAGE_BITS, stubs for modify_ssr/get_exe_mode Brian Cain
2026-07-03 10:46   ` Peter Maydell
2026-06-29 13:11 ` [PULL v5 39/77] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-06-29 13:11 ` [PULL v5 40/77] target/hexagon: Add hex_interrupts support Brian Cain
2026-06-29 13:11 ` [PULL v5 41/77] target/hexagon: Implement {c,}swi helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 42/77] target/hexagon: Implement iassign{r,w} helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 43/77] target/hexagon: Implement start/stop helpers, soft reset Brian Cain
2026-06-29 13:11 ` [PULL v5 44/77] target/hexagon: Implement {g,s}etimask helpers Brian Cain
2026-06-29 13:12 ` [PULL v5 45/77] target/hexagon: Implement wait helper Brian Cain
2026-06-29 13:12 ` [PULL v5 46/77] target/hexagon: Implement get_exe_mode() Brian Cain
2026-06-29 13:12 ` [PULL v5 47/77] target/hexagon: Implement hex_tlb_entry_get_perm() Brian Cain
2026-06-29 13:12 ` [PULL v5 48/77] target/hexagon: Implement software interrupt Brian Cain
2026-06-29 13:12 ` [PULL v5 49/77] target/hexagon: Implement stack overflow exception Brian Cain
2026-06-29 13:12 ` [PULL v5 50/77] target/hexagon: Implement exec_interrupt, set_irq Brian Cain
2026-06-29 13:12 ` [PULL v5 51/77] target/hexagon: add simple cpu_exec_reset and pointer_wrap Brian Cain
2026-06-29 13:12 ` [PULL v5 52/77] target/hexagon: Implement hexagon_tlb_fill() Brian Cain
2026-06-29 13:12 ` [PULL v5 53/77] target/hexagon: Implement siad inst Brian Cain
2026-06-29 13:12 ` [PULL v5 54/77] target/hexagon: Implement hexagon_resume_threads() Brian Cain
2026-06-29 13:12 ` [PULL v5 55/77] target/hexagon: Implement setprio, resched Brian Cain
2026-06-29 13:12 ` [PULL v5 56/77] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug() Brian Cain
2026-06-29 13:12 ` [PULL v5 57/77] target/hexagon: extend hexagon_cpu_mmu_index() for sysemu Brian Cain
2026-06-29 13:12 ` [PULL v5 58/77] target/hexagon: Decode trap1, rte as COF Brian Cain
2026-06-29 13:12 ` [PULL v5 59/77] target/hexagon: Implement modify_ssr, resched, pending_interrupt Brian Cain
2026-06-29 13:12 ` [PULL v5 60/77] target/hexagon: Add pkt_ends_tb to translation Brian Cain
2026-06-29 13:12 ` [PULL v5 61/77] target/hexagon: Add next_PC, {s,g}reg writes Brian Cain
2026-06-29 13:12 ` [PULL v5 62/77] target/hexagon: Add implicit sysreg writes Brian Cain
2026-06-29 13:12 ` [PULL v5 63/77] target/hexagon: Define system, guest reg names Brian Cain
2026-06-29 13:12 ` [PULL v5 64/77] target/hexagon: Add k0 {un,}lock Brian Cain
2026-07-03 10:48   ` Peter Maydell
2026-06-29 13:12 ` [PULL v5 65/77] target/hexagon: Add PC to raise_exception, use fTRAP() helper Brian Cain
2026-06-29 13:12 ` [PULL v5 66/77] target/hexagon: Add TCG overrides for transfer insts Brian Cain
2026-06-29 13:12 ` [PULL v5 67/77] target/hexagon: Add support for loadw_phys Brian Cain
2026-06-29 13:12 ` [PULL v5 68/77] target/hexagon: Add guest reg reading functionality Brian Cain
2026-06-29 13:12 ` [PULL v5 69/77] hw/hexagon: Add globalreg model Brian Cain
2026-06-29 13:12 ` [PULL v5 70/77] hw/hexagon: Add global register tracing Brian Cain
2026-06-29 13:12 ` [PULL v5 71/77] hw/hexagon: Add hexagon TLB device implementation Brian Cain
2026-06-29 13:12 ` [PULL v5 72/77] hw/hexagon: Add machine configs for sysemu Brian Cain
2026-06-29 13:12 ` [PULL v5 73/77] hw/hexagon: Add v68, sa8775-cdsp0 defs Brian Cain
2026-06-29 13:12 ` [PULL v5 74/77] hw/hexagon: Add support for cfgbase Brian Cain
2026-06-29 13:12 ` [PULL v5 75/77] target/hexagon: add build config for softmmu Brian Cain
2026-06-29 13:12 ` [PULL v5 76/77] hw/hexagon: Define hexagon "virt" machine Brian Cain
2026-06-29 13:12 ` [PULL v5 77/77] tests/qtest: Add hexagon boot-serial-test Brian Cain
2026-06-29 18:28 ` [PULL v5 00/77] hex queue Stefan Hajnoczi
2026-06-30  4:37   ` Philippe Mathieu-Daudé

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