From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org, stefanha@redhat.com, peter.maydell@linaro.org
Cc: brian.cain@oss.qualcomm.com, Brian Cain <bcain@quicinc.com>,
Taylor Simpson <ltaylorsimpson@gmail.com>,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PULL v5 60/77] target/hexagon: Add pkt_ends_tb to translation
Date: Mon, 29 Jun 2026 06:12:15 -0700 [thread overview]
Message-ID: <20260629131232.2487780-61-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260629131232.2487780-1-brian.cain@oss.qualcomm.com>
From: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/translate.h | 1 -
target/hexagon/translate.c | 102 ++++++++++++++++++++++++++++++++++++-
2 files changed, 100 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index f79bdedd7b6..fea88cb2db7 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -86,7 +86,6 @@ typedef struct DisasContext {
TCGv branch_taken;
TCGv dczero_addr;
bool pcycle_enabled;
- bool pkt_ends_tb;
uint32_t num_cycles;
} DisasContext;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index ce5bbe92d5d..35e90362880 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -270,6 +270,16 @@ static bool check_for_attrib(Packet *pkt, int attrib)
return false;
}
+static bool check_for_opcode(Packet *pkt, uint16_t opcode)
+{
+ for (int i = 0; i < pkt->num_insns; i++) {
+ if (pkt->insn[i].opcode == opcode) {
+ return true;
+ }
+ }
+ return false;
+}
+
static bool need_slot_cancelled(Packet *pkt)
{
/* We only need slot_cancelled for conditional store instructions */
@@ -283,6 +293,90 @@ static bool need_slot_cancelled(Packet *pkt)
return false;
}
+#ifndef CONFIG_USER_ONLY
+static bool sreg_write_ends_tb(int reg_num)
+{
+ return reg_num == HEX_SREG_SSR ||
+ reg_num == HEX_SREG_STID ||
+ reg_num == HEX_SREG_IMASK ||
+ reg_num == HEX_SREG_IPENDAD ||
+ reg_num == HEX_SREG_BESTWAIT ||
+ reg_num == HEX_SREG_SCHEDCFG;
+}
+
+static bool has_sreg_write_ends_tb(Packet const *pkt)
+{
+ for (int i = 0; i < pkt->num_insns; i++) {
+ Insn const *insn = &pkt->insn[i];
+ uint16_t opcode = insn->opcode;
+ if (opcode == Y2_tfrsrcr) {
+ /* Write to a single sreg */
+ int reg_num = insn->regno[0];
+ if (sreg_write_ends_tb(reg_num)) {
+ return true;
+ }
+ } else if (opcode == Y4_tfrspcp) {
+ /* Write to a sreg pair */
+ int reg_num = insn->regno[0];
+ if (sreg_write_ends_tb(reg_num)) {
+ return true;
+ }
+ if (sreg_write_ends_tb(reg_num + 1)) {
+ return true;
+ }
+ }
+ }
+ return false;
+}
+#endif
+
+static bool pkt_ends_tb(Packet *pkt)
+{
+ if (pkt->pkt_has_cof) {
+ return true;
+ }
+#ifndef CONFIG_USER_ONLY
+ /* System mode instructions that end TLB */
+ if (check_for_opcode(pkt, Y2_swi) ||
+ check_for_opcode(pkt, Y2_cswi) ||
+ check_for_opcode(pkt, Y2_ciad) ||
+ check_for_opcode(pkt, Y4_siad) ||
+ check_for_opcode(pkt, Y2_wait) ||
+ check_for_opcode(pkt, Y2_resume) ||
+ check_for_opcode(pkt, Y2_iassignw) ||
+ check_for_opcode(pkt, Y2_setimask) ||
+ check_for_opcode(pkt, Y4_nmi) ||
+ check_for_opcode(pkt, Y2_setprio) ||
+ check_for_opcode(pkt, Y2_start) ||
+ check_for_opcode(pkt, Y2_stop) ||
+ check_for_opcode(pkt, Y2_k0lock) ||
+ check_for_opcode(pkt, Y2_k0unlock) ||
+ check_for_opcode(pkt, Y2_tlblock) ||
+ check_for_opcode(pkt, Y2_tlbunlock) ||
+ check_for_opcode(pkt, Y2_break) ||
+ check_for_opcode(pkt, Y2_isync) ||
+ check_for_opcode(pkt, Y2_syncht) ||
+ check_for_opcode(pkt, Y2_tlbp) ||
+ check_for_opcode(pkt, Y2_tlbw) ||
+ check_for_opcode(pkt, Y5_ctlbw) ||
+ check_for_opcode(pkt, Y5_tlbasidi)) {
+ return true;
+ }
+
+ /*
+ * Check for sreg writes that would end the TB
+ */
+ if (check_for_attrib(pkt, A_IMPLICIT_WRITES_SSR)) {
+ return true;
+ }
+ if (has_sreg_write_ends_tb(pkt)) {
+ return true;
+ }
+#endif
+ return false;
+}
+
+
static bool need_next_PC(DisasContext *ctx)
{
/* Check for conditional control flow or HW loop end */
@@ -439,7 +533,11 @@ static void analyze_packet(DisasContext *ctx)
static void gen_start_packet(DisasContext *ctx)
{
- target_ulong next_PC = ctx->base.pc_next + ctx->pkt.encod_pkt_size_in_bytes;
+ Packet *pkt = &ctx->pkt;
+ target_ulong next_PC = (check_for_opcode(pkt, Y2_k0lock) ||
+ check_for_opcode(pkt, Y2_tlblock)) ?
+ ctx->base.pc_next :
+ ctx->base.pc_next + pkt->encod_pkt_size_in_bytes;
int i;
/* Clear out the disassembly context */
@@ -944,7 +1042,7 @@ static void gen_commit_packet(DisasContext *ctx)
ctx->pkt.vhist_insn->generate(ctx);
}
- if (ctx->pkt.pkt_has_cof) {
+ if (pkt_ends_tb(&ctx->pkt) || ctx->base.is_jmp == DISAS_NORETURN) {
gen_end_tb(ctx);
}
}
--
2.34.1
next prev parent reply other threads:[~2026-06-29 13:45 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 13:11 [PULL v5 00/77] hex queue Brian Cain
2026-06-29 13:11 ` [PULL v5 01/77] tests/docker: add flex and bison to emsdk-wasm64-cross Brian Cain
2026-06-29 13:11 ` [PULL v5 02/77] configs/meson: disable hexagon idef-parser for emscripten builds Brian Cain
2026-06-29 13:11 ` [PULL v5 03/77] target/hexagon: use cmd_array() instead of get_id() Brian Cain
2026-06-29 13:11 ` [PULL v5 04/77] target/hexagon/idef-parser: open input file in binary mode Brian Cain
2026-06-29 13:11 ` [PULL v5 05/77] docs: Add hexagon sysemu docs Brian Cain
2026-06-29 13:11 ` [PULL v5 06/77] docs/system: Add hexagon CPU emulation Brian Cain
2026-06-29 13:11 ` [PULL v5 07/77] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-06-29 13:11 ` [PULL v5 08/77] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-06-29 13:11 ` [PULL v5 09/77] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-06-29 13:11 ` [PULL v5 10/77] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-06-29 13:11 ` [PULL v5 11/77] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain
2026-06-29 13:11 ` [PULL v5 12/77] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-06-29 13:11 ` [PULL v5 13/77] target/hexagon: Add a placeholder fp exception Brian Cain
2026-06-29 13:11 ` [PULL v5 14/77] target/hexagon: Add guest, system reg number defs Brian Cain
2026-06-29 13:11 ` [PULL v5 15/77] target/hexagon: Add guest, system reg number state Brian Cain
2026-06-29 13:11 ` [PULL v5 16/77] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-06-29 13:11 ` [PULL v5 17/77] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-06-29 13:11 ` [PULL v5 18/77] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-06-29 13:11 ` [PULL v5 19/77] target/hexagon: Add new macro definitions " Brian Cain
2026-06-29 13:11 ` [PULL v5 20/77] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-06-29 13:11 ` [PULL v5 21/77] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 22/77] target/hexagon: Add vmstate representation Brian Cain
2026-06-29 13:11 ` [PULL v5 23/77] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-06-29 13:11 ` [PULL v5 24/77] target/hexagon: Define register fields for system regs Brian Cain
2026-06-29 13:11 ` [PULL v5 25/77] target/hexagon: Implement do_raise_exception() Brian Cain
2026-06-29 13:11 ` [PULL v5 26/77] target/hexagon: Add system reg insns Brian Cain
2026-06-29 13:11 ` [PULL v5 27/77] target/hexagon: Add sysemu TCG overrides Brian Cain
2026-06-29 13:11 ` [PULL v5 28/77] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-06-29 13:11 ` [PULL v5 29/77] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-06-29 13:11 ` [PULL v5 30/77] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-06-29 13:11 ` [PULL v5 31/77] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-06-29 13:11 ` [PULL v5 32/77] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 33/77] target/hexagon: Add representation to count cycles Brian Cain
2026-06-29 13:11 ` [PULL v5 34/77] target/hexagon: Add implementation of cycle counters Brian Cain
2026-06-29 13:11 ` [PULL v5 35/77] target/hexagon: Add pcycle setting functionality Brian Cain
2026-06-29 13:11 ` [PULL v5 36/77] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-06-29 13:11 ` [PULL v5 37/77] hw/hexagon: Declare hexagon TLB device interface Brian Cain
2026-06-29 13:11 ` [PULL v5 38/77] target/hexagon: Update TARGET_PAGE_BITS, stubs for modify_ssr/get_exe_mode Brian Cain
2026-07-03 10:46 ` Peter Maydell
2026-06-29 13:11 ` [PULL v5 39/77] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-06-29 13:11 ` [PULL v5 40/77] target/hexagon: Add hex_interrupts support Brian Cain
2026-06-29 13:11 ` [PULL v5 41/77] target/hexagon: Implement {c,}swi helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 42/77] target/hexagon: Implement iassign{r,w} helpers Brian Cain
2026-06-29 13:11 ` [PULL v5 43/77] target/hexagon: Implement start/stop helpers, soft reset Brian Cain
2026-06-29 13:11 ` [PULL v5 44/77] target/hexagon: Implement {g,s}etimask helpers Brian Cain
2026-06-29 13:12 ` [PULL v5 45/77] target/hexagon: Implement wait helper Brian Cain
2026-06-29 13:12 ` [PULL v5 46/77] target/hexagon: Implement get_exe_mode() Brian Cain
2026-06-29 13:12 ` [PULL v5 47/77] target/hexagon: Implement hex_tlb_entry_get_perm() Brian Cain
2026-06-29 13:12 ` [PULL v5 48/77] target/hexagon: Implement software interrupt Brian Cain
2026-06-29 13:12 ` [PULL v5 49/77] target/hexagon: Implement stack overflow exception Brian Cain
2026-06-29 13:12 ` [PULL v5 50/77] target/hexagon: Implement exec_interrupt, set_irq Brian Cain
2026-06-29 13:12 ` [PULL v5 51/77] target/hexagon: add simple cpu_exec_reset and pointer_wrap Brian Cain
2026-06-29 13:12 ` [PULL v5 52/77] target/hexagon: Implement hexagon_tlb_fill() Brian Cain
2026-06-29 13:12 ` [PULL v5 53/77] target/hexagon: Implement siad inst Brian Cain
2026-06-29 13:12 ` [PULL v5 54/77] target/hexagon: Implement hexagon_resume_threads() Brian Cain
2026-06-29 13:12 ` [PULL v5 55/77] target/hexagon: Implement setprio, resched Brian Cain
2026-06-29 13:12 ` [PULL v5 56/77] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug() Brian Cain
2026-06-29 13:12 ` [PULL v5 57/77] target/hexagon: extend hexagon_cpu_mmu_index() for sysemu Brian Cain
2026-06-29 13:12 ` [PULL v5 58/77] target/hexagon: Decode trap1, rte as COF Brian Cain
2026-06-29 13:12 ` [PULL v5 59/77] target/hexagon: Implement modify_ssr, resched, pending_interrupt Brian Cain
2026-06-29 13:12 ` Brian Cain [this message]
2026-06-29 13:12 ` [PULL v5 61/77] target/hexagon: Add next_PC, {s,g}reg writes Brian Cain
2026-06-29 13:12 ` [PULL v5 62/77] target/hexagon: Add implicit sysreg writes Brian Cain
2026-06-29 13:12 ` [PULL v5 63/77] target/hexagon: Define system, guest reg names Brian Cain
2026-06-29 13:12 ` [PULL v5 64/77] target/hexagon: Add k0 {un,}lock Brian Cain
2026-07-03 10:48 ` Peter Maydell
2026-06-29 13:12 ` [PULL v5 65/77] target/hexagon: Add PC to raise_exception, use fTRAP() helper Brian Cain
2026-06-29 13:12 ` [PULL v5 66/77] target/hexagon: Add TCG overrides for transfer insts Brian Cain
2026-06-29 13:12 ` [PULL v5 67/77] target/hexagon: Add support for loadw_phys Brian Cain
2026-06-29 13:12 ` [PULL v5 68/77] target/hexagon: Add guest reg reading functionality Brian Cain
2026-06-29 13:12 ` [PULL v5 69/77] hw/hexagon: Add globalreg model Brian Cain
2026-06-29 13:12 ` [PULL v5 70/77] hw/hexagon: Add global register tracing Brian Cain
2026-06-29 13:12 ` [PULL v5 71/77] hw/hexagon: Add hexagon TLB device implementation Brian Cain
2026-06-29 13:12 ` [PULL v5 72/77] hw/hexagon: Add machine configs for sysemu Brian Cain
2026-06-29 13:12 ` [PULL v5 73/77] hw/hexagon: Add v68, sa8775-cdsp0 defs Brian Cain
2026-06-29 13:12 ` [PULL v5 74/77] hw/hexagon: Add support for cfgbase Brian Cain
2026-06-29 13:12 ` [PULL v5 75/77] target/hexagon: add build config for softmmu Brian Cain
2026-06-29 13:12 ` [PULL v5 76/77] hw/hexagon: Define hexagon "virt" machine Brian Cain
2026-06-29 13:12 ` [PULL v5 77/77] tests/qtest: Add hexagon boot-serial-test Brian Cain
2026-06-29 18:28 ` [PULL v5 00/77] hex queue Stefan Hajnoczi
2026-06-30 4:37 ` Philippe Mathieu-Daudé
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