From: sashiko-bot@kernel.org
To: "Varshini Rajendran" <varshini.rajendran@microchip.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 11/13] ARM: dts: microchip: sama7d65: add cells for temperature calibration
Date: Tue, 30 Jun 2026 10:12:41 +0000 [thread overview]
Message-ID: <20260630101242.4325B1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260630093603.38663-12-varshini.rajendran@microchip.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
New issues:
- [Medium] Adding `nvmem-cells` and `nvmem-cell-names` to the ADC device tree node will cause `dtbs_check` validation failures because they are not documented in the corresponding YAML binding.
Pre-existing issues:
- [Critical] A raw ADC hardware reading of 0 for the bandgap voltage causes a kernel panic due to division by zero.
- [High] The ADC driver fails to propagate `-EPROBE_DEFER` when acquiring the calibration NVMEM cell, permanently breaking temperature calibration if the NVMEM provider probes later.
--
commit 6142abae648297aaf43eed2fdd08d882882efb74
Author: Varshini Rajendran <varshini.rajendran@microchip.com>
Subject: ARM: dts: microchip: sama7d65: add cells for temperature calibration
This commit adds NVMEM cells to the ADC node for temperature calibration data
on the sama7d65 platform.
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index 5867fda378b19..c336f863406de 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
[ ... ]
> @@ -323,6 +323,8 @@ adc: adc@e1000000 {
> atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
> atmel,startup-time-ms = <4>;
> #io-channel-cells = <1>;
> + nvmem-cells = <&temperature_calib>;
> + nvmem-cell-names = "temperature_calib";
[Severity: Medium]
Will adding these properties cause dtbs_check validation failures?
It appears the corresponding YAML binding schema
(Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml) restricts
properties via additionalProperties: false, but lacks the definitions for
nvmem-cells and nvmem-cell-names. Do we need a matching binding update?
[Severity: High]
This is a pre-existing issue, but will adding these nvmem cells expose a
probe deferral bug in the driver?
Looking at at91_adc_probe() in drivers/iio/adc/at91-sama5d2_adc.c, if the
NVMEM provider hasn't probed yet, nvmem_cell_get() returns -EPROBE_DEFER:
drivers/iio/adc/at91-sama5d2_adc.c:at91_adc_probe() {
...
ret = at91_adc_temp_sensor_init(st, &pdev->dev);
/* Don't register temperature channel if initialization failed. */
if (ret)
num_channels = st->soc_info.platform->max_channels - 1;
else
num_channels = st->soc_info.platform->max_channels;
...
}
Since -EPROBE_DEFER is swallowed here and the probe completes successfully,
does this mean the driver will never retry, permanently breaking the
temperature calibration if the NVMEM provider probes later?
[Severity: Critical]
This is a pre-existing issue, but since we are enabling temperature sensor
capabilities here, does at91_adc_read_temp() have a division by zero risk?
When userspace reads the temperature from the IIO sysfs node, the hardware
is requested to read the bandgap voltage (vbg). If the hardware returns 0
(due to a glitch, lack of analog power, or being unplugged), it is used as
a divisor:
drivers/iio/adc/at91-sama5d2_adc.c:at91_adc_read_temp() {
...
div1 = DIV_ROUND_CLOSEST_ULL(((u64)vtemp * clb->p6), vbg);
...
}
Can a raw ADC hardware reading of 0 for the bandgap voltage cause a system
crash due to this unchecked division by zero?
> status = "disabled";
> };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260630093603.38663-1-varshini.rajendran@microchip.com?part=11
next prev parent reply other threads:[~2026-06-30 10:12 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-30 9:35 [PATCH v3 00/13] Add thermal management support for sama7d65 Varshini Rajendran
2026-06-30 9:35 ` [PATCH v3 01/13] dt-bindings: iio: adc: at91-sama5d2: document sama7d65 Varshini Rajendran
2026-06-30 9:35 ` [PATCH v3 02/13] iio: adc: at91-sama5d2_adc: use cleanup.h for NVMEM buffer Varshini Rajendran
2026-06-30 12:12 ` Andy Shevchenko
2026-06-30 23:36 ` Jonathan Cameron
2026-06-30 9:35 ` [PATCH v3 03/13] iio: adc: at91-sama5d2_adc: rework temp calibration layout handling Varshini Rajendran
2026-06-30 12:16 ` Andy Shevchenko
2026-06-30 23:38 ` Jonathan Cameron
2026-06-30 9:35 ` [PATCH v3 04/13] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65 Varshini Rajendran
2026-06-30 12:18 ` Andy Shevchenko
2026-06-30 23:43 ` Jonathan Cameron
2026-06-30 9:35 ` [PATCH v3 05/13] dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example Varshini Rajendran
2026-06-30 9:35 ` [PATCH v3 06/13] nvmem: microchip-otpc: add tag-based packet lookup Varshini Rajendran
2026-06-30 10:00 ` sashiko-bot
2026-06-30 12:23 ` Andy Shevchenko
2026-06-30 12:26 ` Andy Shevchenko
2026-06-30 23:49 ` Jonathan Cameron
2026-06-30 9:35 ` [PATCH v3 07/13] ARM: dts: microchip: sama7d65: add cpu opps Varshini Rajendran
2026-06-30 9:35 ` [PATCH v3 08/13] ARM: dts: microchip: sama7d65: Add ADC node Varshini Rajendran
2026-06-30 9:35 ` [PATCH v3 09/13] ARM: dts: microchip: sama7d65_curiosity: Enable ADC, DVFS Varshini Rajendran
2026-06-30 9:36 ` [PATCH v3 10/13] ARM: dts: microchip: sama7d65: add otpc node Varshini Rajendran
2026-06-30 9:36 ` [PATCH v3 11/13] ARM: dts: microchip: sama7d65: add cells for temperature calibration Varshini Rajendran
2026-06-30 10:12 ` sashiko-bot [this message]
2026-06-30 9:36 ` [PATCH v3 12/13] ARM: dts: microchip: sama7d65: add temperature sensor Varshini Rajendran
2026-06-30 9:36 ` [PATCH v3 13/13] ARM: dts: microchip: sama7d65: add thermal zones node Varshini Rajendran
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