[PATCH 0/4] Add Support for AMD EPYC Zen 6 CPU Model

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

This series adds support for AMD's upcoming EPYC Zen 6 CPU models
(EPYC-Venice). The first four patches add support for the EPYC-Venice
model while the last patch adds the actual model.

The EPYC-Venice model is based on the EPYC-Turin model feature set with
the following feature additions:

	ERAPS, TSC Adjustment, Shadow Stack, and SRSO_NO vulnerability fix

and support for the following instructions:

	AVX512 FP16, AVX512 IFMA, AVX NE-Convert, AVX VNNI Int8, and
	AVX512 BMM instructions

as well as new cache values.

Some of these features (ERAPS) were only just recently merged into the
Linux kernel. It's recommended to use a v7.0+ kernel to leverage the
full support of the model.

Amit Shah (1):
  target/i386: Add getting RAPSIZE for ERAPS enabled guests

Ben Cheatham (2):
  target/i386: Update RAPSIZE definition
  target/i386: Add EPYC-Venice CPU model

Nikunj A Dadhania (1):
  target/i386: Add AVX512 Bit Matrix Multiply (BMM) support

 target/i386/cpu.c | 152 +++++++++++++++++++++++++++++++++++++++++++++-
 target/i386/cpu.h |   9 ++-
 2 files changed, 156 insertions(+), 5 deletions(-)

base-commit: 10a9fa0065a3cd3dcf12e2eae6b8caaac6ecdec7
-- 
2.53.0