[PATCH 1/4] target/i386: Add AVX512 Bit Matrix Multiply (BMM) support

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

From: Nikunj A Dadhania <nikunj@amd.com>

Add the AVX512 Bit Matrix Multiply feature flag at CPUID leaf
0x80000021_EAX[23], enabling guests to detect and use BMM instructions
for accelerated bit matrix multiply operations. Add the "avx512-bmm"
feature name to allow QEMU to expose this capability when available on
the host.

avx512-bmm: AVX512 Bit Matrix Multiply instruction

Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8929a75c7c92..a85cc67700fa 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1434,7 +1434,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "auto-ibrs", NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
-            "prefetchi", NULL, NULL, NULL,
+            "prefetchi", NULL, NULL, "avx512-bmm",
             "eraps", NULL, NULL, "sbpb",
             "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL,
         },
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 67e2ecf32517..e66333cd9c24 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1200,6 +1200,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define CPUID_8000_0021_EAX_AUTO_IBRS                    (1U << 8)
 /* Indicates support for IC prefetch */
 #define CPUID_8000_0021_EAX_PREFETCHI                    (1U << 20)
+/* AVX512 Bit Matrix Multiply (BMM) instruction support */
+#define CPUID_8000_0021_EAX_AVX512_BMM                   (1U << 23)
 /* Enhanced Return Address Predictor Scurity */
 #define CPUID_8000_0021_EAX_ERAPS                        (1U << 24)
 /* Selective Branch Predictor Barrier */
-- 
2.53.0