Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[kernel test robot]

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20260630134324.61085-3-g-praveen@ti.com>
References: <20260630134324.61085-3-g-praveen@ti.com>
TO: Gokul Praveen <g-praveen@ti.com>
TO: conor+dt@kernel.org
TO: devicetree@vger.kernel.org
TO: krzk+dt@kernel.org
TO: linux-arm-kernel@lists.infradead.org
TO: linux-kernel@vger.kernel.org
TO: linux-phy@lists.infradead.org
TO: neil.armstrong@linaro.org
TO: nm@ti.com
TO: robh@kernel.org
TO: sjakhade@cadence.com
TO: kristo@kernel.org
TO: vigneshr@ti.com
TO: vkoul@kernel.org
TO: yamonkar@cadence.com

Hi Gokul,

kernel test robot noticed the following build warnings:

[auto build test WARNING on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/Gokul-Praveen/arm64-dts-ti-Add-PLL1-refclk-to-J784S4-SoC-SERDES-node/20260630-214733
base:   net-next/main
patch link:    https://lore.kernel.org/r/20260630134324.61085-3-g-praveen%40ti.com
patch subject: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks
:::::: branch date: 13 hours ago
:::::: commit date: 13 hours ago
config: arm64-randconfig-2051-20260630 (https://download.01.org/0day-ci/archive/20260701/202607010413.ARNFa3Bx-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 9.5.0
dtschema: 2026.7.dev1+g2203c1720
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260701/202607010413.ARNFa3Bx-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202607010413.ARNFa3Bx-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[147, 0], [147, 1], [147, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[152, 0], [152, 1], [152, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-am69-sk.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[115, 0], [115, 1], [115, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-j784s4-evm.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-j784s4-evm.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[132, 0], [132, 1], [132, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[132, 0], [132, 1], [132, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[132, 0], [132, 1], [132, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-j784s4-evm-usb0-type-a.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-j784s4-evm-usb0-type-a.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[132, 0], [132, 1], [132, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[132, 0], [132, 1], [132, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-am69-sk-csi2-dual-imx219.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-am69-sk-csi2-dual-imx219.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[115, 0], [115, 1], [115, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
--
>> arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtb: serdes@5020000 (ti,j721e-serdes-10g): clock-names: ['refclk', 'pll1_refclk', 'phy_en_refclk'] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml
   arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtb: serdes@5020000 (ti,j721e-serdes-10g): clocks: [[115, 0], [115, 1], [115, 16]] is too long
   	from schema $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH v3 net-next 0/2] Add support for dual port USXGMII+SGMII

[Gokul Praveen]

This patch series enables dual port USXGMII and SGMII Ethernet mode
support on the TI J784S4 EVM platform using the CPSW9G Ethernet switch.

The CPSW9G instance supports both SGMII and USXGMII modes simultaneously
on MAC Ports 1 and 2, which connect to ENET Expansion 1 and ENET
Expansion 2 slots through the SERDES2 instance. The series includes:

Multilink SERDES configuration support added to the SERDES2 node by adding
the PLL1 refclk.

v2 <==> v1
===========
* Added modifications to the device tree bindings documentation.

v3 <=> v2
==========
* Added net-next suffix in the patch subject.
* Added a separate bindings patch and added appropriate subject
  format expected for Bindings patches.
* Updated the cover letter description

Gokul Praveen (2):
  arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node
  dt-bindings: phy: cadence-torrent: Update property values to support 3
    clocks

 .../devicetree/bindings/phy/phy-cadence-torrent.yaml          | 4 ++--
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi                    | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

-- 
2.34.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Gokul Praveen]

Update maxItems value of "clocks" property to 3 as description of
this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
and phy_en_refclk(optional))

Update the "clock-names" property as well with the 3 clocks.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
 .../devicetree/bindings/phy/phy-cadence-torrent.yaml          | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 9af39b33646a..54fe78da297a 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -34,7 +34,7 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     description:
       PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
       pll1_refclk is optional and used for multi-protocol configurations requiring
@@ -47,7 +47,7 @@ properties:
     minItems: 1
     items:
       - const: refclk
-      - enum: [ pll1_refclk, phy_en_refclk ]
+      - enum: [refclk, pll1_refclk, phy_en_refclk ]
 
   reg:
     minItems: 1
-- 
2.34.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Gokul Praveen]

Update maxItems value of "clocks" property to 3 as description of
this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
and phy_en_refclk(optional))

Update the "clock-names" property as well with the 3 clocks.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
 .../devicetree/bindings/phy/phy-cadence-torrent.yaml          | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 9af39b33646a..54fe78da297a 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -34,7 +34,7 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     description:
       PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
       pll1_refclk is optional and used for multi-protocol configurations requiring
@@ -47,7 +47,7 @@ properties:
     minItems: 1
     items:
       - const: refclk
-      - enum: [ pll1_refclk, phy_en_refclk ]
+      - enum: [refclk, pll1_refclk, phy_en_refclk ]
 
   reg:
     minItems: 1
-- 
2.34.1

Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `clock-names` schema definition incorrectly restricts the array to a maximum of 2 items and allows duplicate clock names. While the commit correctly updates `clocks` to allow `maxItems: 3`, it only modifies the second element of the `items` array for `clock-names`. In `dt-schema` (based on JSON Schema), defining `items` as an array of schemas implicitly limits the maximum number of items to the length of that array (because `additionalItems` is implicitly false). As a result, a device tree specifying 3 clocks will fail `dt_binding_check` validation. Additionally, adding `refclk` to the second element's `enum` creates a logic error, permitting redundant sequences such as `clock-names = "refclk", "refclk";`.
--

commit d737f6b2f91949e839e21f62c39ca9db8f322775
Author: Gokul Praveen <g-praveen@ti.com>

dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

This commit updates the Cadence Torrent PHY device tree binding to support up
to 3 clocks. It increases the maxItems of the clocks property and updates the
clock-names property.

> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646ac..54fe78da297a2 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      description:
>        PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).

[ ... ]

> @@ -47,7 +47,7 @@ properties:
>      minItems: 1
>      items:
>        - const: refclk
> -      - enum: [ pll1_refclk, phy_en_refclk ]
> +      - enum: [refclk, pll1_refclk, phy_en_refclk ]

[Severity: Medium]
Will this fail schema validation when a device tree specifies 3 clocks? 

Because the items sequence for clock-names only defines two elements, it
implicitly restricts the array to a maximum of 2 items. Even though the clocks
property was updated to maxItems: 3 above, the clock-names array is now
mismatched and will reject 3 items during dt_binding_check.

Also, does this unintentionally allow duplicate clock names? Adding refclk to
the second element's enum makes it possible to define a redundant sequence
like clock-names = "refclk", "refclk".

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260630134324.61085-1-g-praveen@ti.com?part=2

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `clock-names` schema definition incorrectly restricts the array to a maximum of 2 items and allows duplicate clock names. While the commit correctly updates `clocks` to allow `maxItems: 3`, it only modifies the second element of the `items` array for `clock-names`. In `dt-schema` (based on JSON Schema), defining `items` as an array of schemas implicitly limits the maximum number of items to the length of that array (because `additionalItems` is implicitly false). As a result, a device tree specifying 3 clocks will fail `dt_binding_check` validation. Additionally, adding `refclk` to the second element's `enum` creates a logic error, permitting redundant sequences such as `clock-names = "refclk", "refclk";`.
--

commit d737f6b2f91949e839e21f62c39ca9db8f322775
Author: Gokul Praveen <g-praveen@ti.com>

dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

This commit updates the Cadence Torrent PHY device tree binding to support up
to 3 clocks. It increases the maxItems of the clocks property and updates the
clock-names property.

> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646ac..54fe78da297a2 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      description:
>        PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).

[ ... ]

> @@ -47,7 +47,7 @@ properties:
>      minItems: 1
>      items:
>        - const: refclk
> -      - enum: [ pll1_refclk, phy_en_refclk ]
> +      - enum: [refclk, pll1_refclk, phy_en_refclk ]

[Severity: Medium]
Will this fail schema validation when a device tree specifies 3 clocks? 

Because the items sequence for clock-names only defines two elements, it
implicitly restricts the array to a maximum of 2 items. Even though the clocks
property was updated to maxItems: 3 above, the clock-names array is now
mismatched and will reject 3 items during dt_binding_check.

Also, does this unintentionally allow duplicate clock names? Adding refclk to
the second element's enum makes it possible to define a redundant sequence
like clock-names = "refclk", "refclk".

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260630134324.61085-1-g-praveen@ti.com?part=2

Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1647 bytes --]

On Tue, Jun 30, 2026 at 07:13:24PM +0530, Gokul Praveen wrote:
> Update maxItems value of "clocks" property to 3 as description of
> this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
> and phy_en_refclk(optional))
> 
> Update the "clock-names" property as well with the 3 clocks.
> 
> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> ---
>  .../devicetree/bindings/phy/phy-cadence-torrent.yaml          | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646a..54fe78da297a 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      description:
>        PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>        pll1_refclk is optional and used for multi-protocol configurations requiring
> @@ -47,7 +47,7 @@ properties:
>      minItems: 1
>      items:
>        - const: refclk
> -      - enum: [ pll1_refclk, phy_en_refclk ]
> +      - enum: [refclk, pll1_refclk, phy_en_refclk ]

This does not do what you want it to do, I would think, since it means
you can only have two clock names.

Additionally, please restrict 3 clocks to only whatever new TI device
actually has 3 clocks.

pw-bot: changes-requested

Thanks,
Conor.

>  
>    reg:
>      minItems: 1
> -- 
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v3 net-next 2/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1647 bytes --]

On Tue, Jun 30, 2026 at 07:13:24PM +0530, Gokul Praveen wrote:
> Update maxItems value of "clocks" property to 3 as description of
> this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
> and phy_en_refclk(optional))
> 
> Update the "clock-names" property as well with the 3 clocks.
> 
> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> ---
>  .../devicetree/bindings/phy/phy-cadence-torrent.yaml          | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646a..54fe78da297a 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      description:
>        PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>        pll1_refclk is optional and used for multi-protocol configurations requiring
> @@ -47,7 +47,7 @@ properties:
>      minItems: 1
>      items:
>        - const: refclk
> -      - enum: [ pll1_refclk, phy_en_refclk ]
> +      - enum: [refclk, pll1_refclk, phy_en_refclk ]

This does not do what you want it to do, I would think, since it means
you can only have two clock names.

Additionally, please restrict 3 clocks to only whatever new TI device
actually has 3 clocks.

pw-bot: changes-requested

Thanks,
Conor.

>  
>    reg:
>      minItems: 1
> -- 
> 2.34.1
> 

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 112 bytes --]

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy