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From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: linux-perf-users@vger.kernel.org, robh@kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v8 09/22] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
Date: Wed, 01 Jul 2026 09:11:25 +0000	[thread overview]
Message-ID: <20260701091125.C8F191F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260701-counter_delegation-v8-9-7909f863a645@meta.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The Supervisor-level `Ssccfg` extension validation strictly requires the Machine-level `Smcdeleg` extension, breaking S-mode guest VMs.
- [Medium] riscv_ext_ssccfg_validate passes the wrong context pointer to riscv_ext_smcdeleg_validate and performs a logically redundant check.
--

commit 6cf182c3b2cfda28c919d7041cfd7b6c8a237b86
Author: Atish Patra <atishp@rivosinc.com>

RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing

This commit introduces definitions and parsing for the Smcdeleg and Ssccfg
ISA extensions on RISC-V. It adds validation logic to ensure that required
dependencies are present before enabling these extensions.

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1452521d740a6..1fe647e035157 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -330,6 +330,27 @@ static const unsigned int riscv_a_exts[] = {
>  	RISCV_ISA_EXT_ZKNE,	\
>  	RISCV_ISA_EXT_ZKNH
>  
> +static int riscv_ext_smcdeleg_validate(const struct riscv_isa_ext_data *data,
> +				       const unsigned long *isa_bitmap)
> +{
> +	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSCSRIND) &&
> +	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZIHPM) &&
> +	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZICNTR))
> +		return 0;
> +
> +	return -EPROBE_DEFER;
> +}
> +
> +static int riscv_ext_ssccfg_validate(const struct riscv_isa_ext_data *data,
> +				     const unsigned long *isa_bitmap)
> +{
> +	if (!riscv_ext_smcdeleg_validate(data, isa_bitmap) &&
> +	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SMCDELEG))

[Severity: High]
Does this code inadvertently break Ssccfg support in S-mode guest VMs?

When Linux runs as a guest VM under a hypervisor, M-mode extensions like
Smcdeleg are hidden from the guest OS. Since this validation strictly requires
RISCV_ISA_EXT_SMCDELEG to be present in the ISA string, Ssccfg will always
return -EPROBE_DEFER and be disabled.

Should a Supervisor-level extension depend on the presence of a Machine-level
extension?

[Severity: Medium]
Is it intentional to pass the SSCCFG data pointer to a function expecting
SMCDELEG's context?

While it currently doesn't crash because riscv_ext_smcdeleg_validate() ignores
the data pointer, this seems to violate the validation callback API contract.

Additionally, is it necessary to call riscv_ext_smcdeleg_validate() directly
here? If RISCV_ISA_EXT_SMCDELEG is present in the resolved isa_bitmap, it
should already be guaranteed to have passed its own validation function during
a previous loop iteration.

> +		return 0;
> +
> +	return -EPROBE_DEFER;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260701-counter_delegation-v8-0-7909f863a645@meta.com?part=9

  reply	other threads:[~2026-07-01  9:11 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-01  8:46 [PATCH v8 00/22] Add Counter delegation ISA extension support Atish Patra
2026-07-01  8:46 ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 01/22] RISC-V: perf: fix resource cleanup on driver probe failure Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  9:11   ` sashiko-bot
2026-07-01  8:46 ` [PATCH v8 02/22] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 03/22] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 04/22] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 05/22] RISC-V: Define indirect CSR access helpers Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 06/22] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 07/22] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 08/22] RISC-V: Add Sscfg extension CSR definition Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 09/22] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  9:11   ` sashiko-bot [this message]
2026-07-01  8:46 ` [PATCH v8 10/22] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:46 ` [PATCH v8 11/22] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-07-01  8:46   ` Atish Patra
2026-07-01  8:47 ` [PATCH v8 12/22] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  9:20   ` sashiko-bot
2026-07-07  7:45   ` Yicong Yang
2026-07-07  7:45     ` Yicong Yang
2026-07-01  8:47 ` [PATCH v8 13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  9:19   ` sashiko-bot
2026-07-07  7:51   ` Yicong Yang
2026-07-07  7:51     ` Yicong Yang
2026-07-01  8:47 ` [PATCH v8 14/22] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  9:27   ` sashiko-bot
2026-07-07  8:24   ` Yicong Yang
2026-07-07  8:24     ` Yicong Yang
2026-07-01  8:47 ` [PATCH v8 15/22] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  9:26   ` sashiko-bot
2026-07-01  8:47 ` [PATCH v8 16/22] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  9:35   ` sashiko-bot
2026-07-01  8:47 ` [PATCH v8 17/22] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  8:47 ` [PATCH v8 18/22] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  8:47 ` [PATCH v8 19/22] tools/perf: Support event code for arch standard events Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01 17:44   ` Ian Rogers
2026-07-01 17:44     ` Ian Rogers
2026-07-01  8:47 ` [PATCH v8 20/22] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01 17:44   ` Ian Rogers
2026-07-01 17:44     ` Ian Rogers
2026-07-01  8:47 ` [PATCH v8 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  9:38   ` sashiko-bot
2026-07-01  8:47 ` [PATCH v8 22/22] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Atish Patra
2026-07-01  8:47   ` Atish Patra
2026-07-01  9:34   ` sashiko-bot

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