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From: sashiko-bot@kernel.org
To: "Christian Marangi" <ansuelsmth@gmail.com>
Cc: robh@kernel.org, vkoul@kernel.org, olteanv@gmail.com,
	neil.armstrong@linaro.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v10 2/5] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY
Date: Thu, 02 Jul 2026 09:54:46 +0000	[thread overview]
Message-ID: <20260702095447.1214F1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260702093812.15918-3-ansuelsmth@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Encoding fixed internal SoC routing in the device tree via the `airoha,usb2-monitor-clk-sel` property.
--

commit 82d75d6a8695c967604982f45c3db95efe45a784
Author: Christian Marangi <ansuelsmth@gmail.com>

dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY

This commit adds device tree binding documentation for the Airoha AN7581
USB PHY. It details properties for configuring the always-supported USB 2.0
mode and the optional USB 3.0 mode, including slew rate calibration and
Serdes configuration.

> diff --git a/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> new file mode 100644
> index 0000000000000..f42e3d49a61fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> @@ -0,0 +1,62 @@
[ ... ]
> +  reg:
> +    maxItems: 1
> +
> +  airoha,usb2-monitor-clk-sel:
> +    description: Describe what oscillator across the available 4
> +      should be selected for USB 2.0 Slew Rate calibration.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2, 3]

[Severity: Low]
Since the commit message mentions that each port has only one of the 4 monitor
clocks actually connected in HW, does this property encode a fixed internal
SoC routing rather than a board-specific configuration?

Could the driver deduce the correct clock selection internally (for example,
from the port's register address) instead of requiring a DT property for a
fixed SoC hardware characteristic?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093812.15918-1-ansuelsmth@gmail.com?part=2

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Christian Marangi" <ansuelsmth@gmail.com>
Cc: robh@kernel.org, vkoul@kernel.org, olteanv@gmail.com,
	neil.armstrong@linaro.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v10 2/5] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY
Date: Thu, 02 Jul 2026 09:54:46 +0000	[thread overview]
Message-ID: <20260702095447.1214F1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260702093812.15918-3-ansuelsmth@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Encoding fixed internal SoC routing in the device tree via the `airoha,usb2-monitor-clk-sel` property.
--

commit 82d75d6a8695c967604982f45c3db95efe45a784
Author: Christian Marangi <ansuelsmth@gmail.com>

dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY

This commit adds device tree binding documentation for the Airoha AN7581
USB PHY. It details properties for configuring the always-supported USB 2.0
mode and the optional USB 3.0 mode, including slew rate calibration and
Serdes configuration.

> diff --git a/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> new file mode 100644
> index 0000000000000..f42e3d49a61fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> @@ -0,0 +1,62 @@
[ ... ]
> +  reg:
> +    maxItems: 1
> +
> +  airoha,usb2-monitor-clk-sel:
> +    description: Describe what oscillator across the available 4
> +      should be selected for USB 2.0 Slew Rate calibration.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2, 3]

[Severity: Low]
Since the commit message mentions that each port has only one of the 4 monitor
clocks actually connected in HW, does this property encode a fixed internal
SoC routing rather than a board-specific configuration?

Could the driver deduce the correct clock selection internally (for example,
from the port's register address) instead of requiring a DT property for a
fixed SoC hardware characteristic?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093812.15918-1-ansuelsmth@gmail.com?part=2

  reply	other threads:[~2026-07-02  9:54 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-02  9:38 [PATCH v10 0/5] airoha: an7581: USB support Christian Marangi
2026-07-02  9:38 ` Christian Marangi
2026-07-02  9:38 ` [PATCH v10 1/5] dt-bindings: clock: airoha: Add PHY binding for Serdes port Christian Marangi
2026-07-02  9:38   ` Christian Marangi
2026-07-02  9:48   ` sashiko-bot
2026-07-02  9:48     ` sashiko-bot
2026-07-02  9:38 ` [PATCH v10 2/5] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY Christian Marangi
2026-07-02  9:38   ` Christian Marangi
2026-07-02  9:54   ` sashiko-bot [this message]
2026-07-02  9:54     ` sashiko-bot
2026-07-02  9:38 ` [PATCH v10 3/5] clk: en7523: Add support for selecting the Serdes port in SCU Christian Marangi
2026-07-02  9:38   ` Christian Marangi
2026-07-02  9:38 ` [PATCH v10 4/5] phy: move and rename Airoha PCIe PHY driver to dedicated directory Christian Marangi
2026-07-02  9:38   ` Christian Marangi
2026-07-02 10:14   ` sashiko-bot
2026-07-02 10:14     ` sashiko-bot
2026-07-02  9:38 ` [PATCH v10 5/5] phy: airoha: Add support for Airoha AN7581 USB PHY Christian Marangi
2026-07-02  9:38   ` Christian Marangi
2026-07-02 10:26   ` sashiko-bot
2026-07-02 10:26     ` sashiko-bot

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