From: Enzo Adriano <enzo.adriano.code@gmail.com>
To: Junhui Liu <junhui.liu@pigmoral.tech>
Cc: Andre Przywara <andre.przywara@arm.com>,
Brian Masney <bmasney@redhat.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Chen-Yu Tsai <wens@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Richard Cochran <richardcochran@gmail.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 4/8] clk: sunxi-ng: a733: Add PLL clocks support
Date: Thu, 2 Jul 2026 13:10:20 -0400 [thread overview]
Message-ID: <20260702171020.836546-1-enzo.adriano.code@gmail.com> (raw)
In-Reply-To: <20260310-a733-clk-v1-4-36b4e9b24457@pigmoral.tech>
Hi Junhui,
Register check for the PLLs against the public A733 User Manual V0.92:
13 of the 14 PLL control registers match the manual's offsets
(PLL_DDR 0x0020 through PLL_DE 0x02E0, section 4.1.6.1 onwards).
The one exception is pll-ref at 0x0000: the manual's CCU register list
starts at 0x0020 (PLL_DDR), so the PLL_REF control register is not in
the public V0.92 document. It does match the vendor kernel's CCU
(SUN60IW2_PLL_REF_CTRL_REG 0x0000), so a short provenance note near the
definition might help future readers, same as for the other
vendor-sourced entries discussed in this thread. For what it's worth,
on a Radxa Cubie A7S (26 MHz DCXO) we can confirm at runtime that
pll-ref produces the normalized 24 MHz reference with the hosc-side
clocks reading 26 MHz, so the modeling demonstrably works on hardware.
Thanks,
Enzo
WARNING: multiple messages have this Message-ID (diff)
From: Enzo Adriano <enzo.adriano.code@gmail.com>
To: Junhui Liu <junhui.liu@pigmoral.tech>
Cc: Andre Przywara <andre.przywara@arm.com>,
Brian Masney <bmasney@redhat.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Chen-Yu Tsai <wens@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Richard Cochran <richardcochran@gmail.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 4/8] clk: sunxi-ng: a733: Add PLL clocks support
Date: Thu, 2 Jul 2026 13:10:20 -0400 [thread overview]
Message-ID: <20260702171020.836546-1-enzo.adriano.code@gmail.com> (raw)
In-Reply-To: <20260310-a733-clk-v1-4-36b4e9b24457@pigmoral.tech>
Hi Junhui,
Register check for the PLLs against the public A733 User Manual V0.92:
13 of the 14 PLL control registers match the manual's offsets
(PLL_DDR 0x0020 through PLL_DE 0x02E0, section 4.1.6.1 onwards).
The one exception is pll-ref at 0x0000: the manual's CCU register list
starts at 0x0020 (PLL_DDR), so the PLL_REF control register is not in
the public V0.92 document. It does match the vendor kernel's CCU
(SUN60IW2_PLL_REF_CTRL_REG 0x0000), so a short provenance note near the
definition might help future readers, same as for the other
vendor-sourced entries discussed in this thread. For what it's worth,
on a Radxa Cubie A7S (26 MHz DCXO) we can confirm at runtime that
pll-ref produces the normalized 24 MHz reference with the hosc-side
clocks reading 26 MHz, so the modeling demonstrably works on hardware.
Thanks,
Enzo
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next prev parent reply other threads:[~2026-07-02 17:10 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-10 8:33 [PATCH RFC 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Junhui Liu
2026-03-10 8:33 ` Junhui Liu
2026-03-10 8:33 ` [PATCH RFC 1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support Junhui Liu
2026-03-10 8:33 ` Junhui Liu
2026-03-28 12:07 ` Chen-Yu Tsai
2026-03-28 12:07 ` Chen-Yu Tsai
2026-03-10 8:33 ` [PATCH RFC 2/8] clk: sunxi-ng: sdm: Add dual patterns support Junhui Liu
2026-03-10 8:33 ` Junhui Liu
2026-03-29 7:56 ` Chen-Yu Tsai
2026-03-29 7:56 ` Chen-Yu Tsai
2026-03-10 8:33 ` [PATCH RFC 3/8] clk: sunxi-ng: a733: Add PRCM CCU Junhui Liu
2026-03-10 8:33 ` Junhui Liu
2026-03-28 15:04 ` Chen-Yu Tsai
2026-03-28 15:04 ` Chen-Yu Tsai
2026-07-02 16:59 ` Enzo Adriano
2026-07-02 16:59 ` Enzo Adriano
2026-03-10 8:33 ` [PATCH RFC 4/8] clk: sunxi-ng: a733: Add PLL clocks support Junhui Liu
2026-03-10 8:33 ` Junhui Liu
2026-07-02 17:10 ` Enzo Adriano [this message]
2026-07-02 17:10 ` Enzo Adriano
2026-03-10 8:33 ` [PATCH RFC 5/8] clk: sunxi-ng: a733: Add bus " Junhui Liu
2026-03-10 8:33 ` Junhui Liu
2026-06-23 22:35 ` Andre Przywara
2026-06-23 22:35 ` Andre Przywara
2026-03-10 8:33 ` [PATCH RFC 6/8] clk: sunxi-ng: a733: Add mod " Junhui Liu
2026-03-10 8:33 ` Junhui Liu
2026-07-02 17:24 ` Enzo Adriano
2026-07-02 17:24 ` Enzo Adriano
2026-03-10 8:34 ` [PATCH RFC 7/8] clk: sunxi-ng: a733: Add bus clock gates Junhui Liu
2026-03-10 8:34 ` Junhui Liu
2026-04-15 22:14 ` Andre Przywara
2026-04-15 22:14 ` Andre Przywara
2026-07-02 17:34 ` Enzo Adriano
2026-07-02 17:34 ` Enzo Adriano
2026-03-10 8:34 ` [PATCH RFC 8/8] clk: sunxi-ng: a733: Add reset lines Junhui Liu
2026-03-10 8:34 ` Junhui Liu
2026-05-13 23:22 ` Andre Przywara
2026-05-13 23:22 ` Andre Przywara
2026-05-14 2:41 ` Junhui Liu
2026-05-14 2:41 ` Junhui Liu
2026-07-02 18:11 ` Enzo Adriano
2026-07-02 18:11 ` Enzo Adriano
2026-06-29 12:52 ` [PATCH RFC 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Jerome Brunet
2026-06-29 12:52 ` Jerome Brunet
2026-07-01 16:07 ` Enzo Adriano
2026-07-01 16:07 ` Enzo Adriano
2026-07-02 8:57 ` Andre Przywara
2026-07-02 8:57 ` Andre Przywara
2026-07-02 15:44 ` Junhui Liu
2026-07-02 15:44 ` Junhui Liu
2026-07-02 23:51 ` Enzo Adriano
2026-07-02 23:51 ` Enzo Adriano
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