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From: sashiko-bot@kernel.org
To: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org, vkoul@kernel.org,
	olteanv@gmail.com, neil.armstrong@linaro.org,
	linux-phy@lists.infradead.org, conor+dt@kernel.org,
	robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 09/12] phy: phy-mtk-dp: Rewrite and document default driving param macros
Date: Tue, 07 Jul 2026 14:28:15 +0000	[thread overview]
Message-ID: <20260707142816.695821F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260707141931.191172-10-angelogioacchino.delregno@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch uses `FIELD_PREP_CONST` (and earlier patches in the series use `FIELD_PREP`) without explicitly including `<linux/bitfield.h>`.
--

--- Patch [9]: [PATCH v2 09/12] phy: phy-mtk-dp: Rewrite and document default driving param macros ---
commit e682fc4989b37eaa003ac03d4d2a9a69b306a63b
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

phy: phy-mtk-dp: Rewrite and document default driving param macros

This commit rewrites the default driving parameters for the PHY using
FIELD_PREP_CONST. It also adds definitions and comments to explain what
these parameters are supposed to set.

> diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
> index d0ef8e8f6670c..9a800d6b91c3f 100644
> --- a/drivers/phy/mediatek/phy-mtk-dp.c
> +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> @@ -85,51 +85,47 @@

[ ... ]

> +#define XTP_LN_TX_LCTXC_SW2_PRE1	GENMASK(5, 0)
> +#define XTP_LN_TX_LCTXC_SW3_PRE0	GENMASK(13, 8)
> +
> +#define BUILD_DRIVING_PARAM_0(sw0_pre0, sw0_pre1, sw0_pre2, sw0_pre3) (	\
> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE0, sw0_pre0) |		\

[Severity: Low]
This isn't a bug, but should linux/bitfield.h be explicitly included since
this code now uses FIELD_PREP_CONST? 

Relying on implicit inclusions can cause build breakages in the future if a
header like linux/phy/phy.h or linux/regmap.h stops including it.

> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE1, sw0_pre1) |		\
> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE2, sw0_pre2) |		\
> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE3, sw0_pre3)		\
> +)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260707141931.191172-1-angelogioacchino.delregno@collabora.com?part=9

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org, vkoul@kernel.org,
	olteanv@gmail.com, neil.armstrong@linaro.org,
	linux-phy@lists.infradead.org, conor+dt@kernel.org,
	robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 09/12] phy: phy-mtk-dp: Rewrite and document default driving param macros
Date: Tue, 07 Jul 2026 14:28:15 +0000	[thread overview]
Message-ID: <20260707142816.695821F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260707141931.191172-10-angelogioacchino.delregno@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch uses `FIELD_PREP_CONST` (and earlier patches in the series use `FIELD_PREP`) without explicitly including `<linux/bitfield.h>`.
--

--- Patch [9]: [PATCH v2 09/12] phy: phy-mtk-dp: Rewrite and document default driving param macros ---
commit e682fc4989b37eaa003ac03d4d2a9a69b306a63b
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

phy: phy-mtk-dp: Rewrite and document default driving param macros

This commit rewrites the default driving parameters for the PHY using
FIELD_PREP_CONST. It also adds definitions and comments to explain what
these parameters are supposed to set.

> diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
> index d0ef8e8f6670c..9a800d6b91c3f 100644
> --- a/drivers/phy/mediatek/phy-mtk-dp.c
> +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> @@ -85,51 +85,47 @@

[ ... ]

> +#define XTP_LN_TX_LCTXC_SW2_PRE1	GENMASK(5, 0)
> +#define XTP_LN_TX_LCTXC_SW3_PRE0	GENMASK(13, 8)
> +
> +#define BUILD_DRIVING_PARAM_0(sw0_pre0, sw0_pre1, sw0_pre2, sw0_pre3) (	\
> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE0, sw0_pre0) |		\

[Severity: Low]
This isn't a bug, but should linux/bitfield.h be explicitly included since
this code now uses FIELD_PREP_CONST? 

Relying on implicit inclusions can cause build breakages in the future if a
header like linux/phy/phy.h or linux/regmap.h stops including it.

> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE1, sw0_pre1) |		\
> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE2, sw0_pre2) |		\
> +	FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE3, sw0_pre3)		\
> +)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260707141931.191172-1-angelogioacchino.delregno@collabora.com?part=9

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2026-07-07 14:28 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-07 14:19 [PATCH v2 00/12] PHY: MediaTek DP PHY refactor and MT8196 eDP AngeloGioacchino Del Regno
2026-07-07 14:19 ` AngeloGioacchino Del Regno
2026-07-07 14:19 ` [PATCH v2 01/12] dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYs AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:35   ` sashiko-bot
2026-07-07 14:35     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 02/12] phy: phy-mtk-dp: Rename regs to regmap in struct mtk_dp_phy AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:27   ` sashiko-bot
2026-07-07 14:27     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 03/12] phy: phy-mtk-dp: Allow probing with devicetree match AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:31   ` sashiko-bot
2026-07-07 14:31     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 04/12] phy: phy-mtk-dp: Migrate register offsets to SoC specific pdata AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:34   ` sashiko-bot
2026-07-07 14:34     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 05/12] phy: phy-mtk-dp: Implement power_on and power_off PHY callbacks AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:33   ` sashiko-bot
2026-07-07 14:33     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 06/12] phy: phy-mtk-dp: Support set_lanes in configure and properly cleanup AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:34   ` sashiko-bot
2026-07-07 14:34     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 07/12] phy: phy-mtk-dp: Support setting volt swing and preemphasis values AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:33   ` sashiko-bot
2026-07-07 14:33     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 08/12] phy: phy-mtk-dp: Add support for digital and analog calibration AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:31   ` sashiko-bot
2026-07-07 14:31     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 09/12] phy: phy-mtk-dp: Rewrite and document default driving param macros AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:28   ` sashiko-bot [this message]
2026-07-07 14:28     ` sashiko-bot
2026-07-07 14:19 ` [PATCH v2 10/12] phy: phy-mtk-dp: Add bitrate register val definitions to SoC data AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:19 ` [PATCH v2 11/12] phy: phy-mtk-dp: Add PHYD Lane EN register mask " AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno
2026-07-07 14:19 ` [PATCH v2 12/12] phy: phy-mtk-dp: Add support for MT8196 eDP PHY AngeloGioacchino Del Regno
2026-07-07 14:19   ` AngeloGioacchino Del Regno

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