From: sashiko-bot@kernel.org
To: "Tomer Maimon" <tmaimon77@gmail.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v8 3/4] arm64: dts: nuvoton: npcm845: Add peripheral nodes
Date: Wed, 08 Jul 2026 17:15:30 +0000 [thread overview]
Message-ID: <20260708171530.F04951F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260708165929.2233934-4-tmaimon77@gmail.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing required DT aliases for the FIU nodes, which will cause the FIU SPI driver to fail to probe.
- [Medium] The `fiu0`, `fiu1`, and `fiu3` SPI controller nodes are missing the required `memory` register region.
--
--- Patch [3]: [PATCH v8 3/4] arm64: dts: nuvoton: npcm845: Add peripheral nodes ---
commit 206c681ed8ed3430aac99224e79975aed3d5da1b
Author: Tomer Maimon <tmaimon77@gmail.com>
arm64: dts: nuvoton: npcm845: Add peripheral nodes
Extend the NPCM845 SoC DTSI with the peripheral controller nodes needed
by the evaluation board and downstream platforms.
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
[ ... ]
> + fiu0: spi@fb000000 {
[Severity: High]
Will the FIU SPI driver fail to probe due to missing device tree aliases?
During driver initialization, spi-npcm-fiu.c calls
of_alias_get_id(dev->of_node, "fiu") to determine the controller index.
Since the fiu0, fiu1, fiu3, and fiux nodes do not have corresponding aliases
defined, this lookup will return a negative error code.
This causes the driver to return -EINVAL and fail to probe. The
nuvoton,npcm-fiu binding also mandates that all FIU controllers be
represented in the aliases node.
> + compatible = "nuvoton,npcm845-fiu";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0xfb000000 0x0 0x1000>;
> + reg-names = "control";
[Severity: Medium]
Will this cause a fallback to slower indirect PIO reads?
The fiu0, fiu1, and fiu3 SPI controller nodes omit the second 'memory'
register region and its corresponding 'memory' reg-name.
When the SPI controller probes, it looks up the memory region using:
platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory")
If it fails to find the memory resource, the driver sets desc->nodirmap = true
which disables direct memory-mapped reads. The dt binding for nuvoton,npcm-fiu
requires both 'control' and 'memory' regions to be specified.
> + clocks = <&clk NPCM8XX_CLK_SPI0>;
> + status = "disabled";
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260708165929.2233934-1-tmaimon77@gmail.com?part=3
next prev parent reply other threads:[~2026-07-08 17:15 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 16:59 [PATCH v8 0/4] arm64: dts: nuvoton: add NPCM845 SoC and EVB support Tomer Maimon
2026-07-08 16:59 ` [PATCH v8 1/4] arm64: dts: nuvoton: npcm845: Drop redundant timer clock-names Tomer Maimon
2026-07-08 16:59 ` [PATCH v8 2/4] arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes Tomer Maimon
2026-07-08 16:59 ` [PATCH v8 3/4] arm64: dts: nuvoton: npcm845: Add peripheral nodes Tomer Maimon
2026-07-08 17:15 ` sashiko-bot [this message]
2026-07-08 16:59 ` [PATCH v8 4/4] arm64: dts: nuvoton: npcm845-evb: " Tomer Maimon
2026-07-08 17:13 ` sashiko-bot
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