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* [linux-next:master 5449/5655] drivers/spi/spi-geni-qcom.c:637 spi_geni_init() warn: missing error code? 'ret'
@ 2026-07-13  8:02 ` Dan Carpenter
  0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2026-07-12 15:35 UTC (permalink / raw)
  To: oe-kbuild; +Cc: lkp, Dan Carpenter

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
TO: Praveen Talari <praveen.talari@oss.qualcomm.com>
CC: Mark Brown <broonie@kernel.org>
CC: "Rafael J. Wysocki (Intel)" <rafael@kernel.org>
CC: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   bee763d5f341b99cf472afeb508d4988f62a6ca1
commit: d8e9ea989acb54508477e4a8c9d9eaf8217e0081 [5449/5655] spi: qcom-geni: Fix missing error check on pm_runtime_get_sync()
:::::: branch date: 2 days ago
:::::: commit date: 2 days ago
config: microblaze-randconfig-r071-20260711 (https://download.01.org/0day-ci/archive/20260712/202607122241.qzP3QAXF-lkp@intel.com/config)
compiler: microblaze-linux-gcc (GCC) 8.5.0
smatch: v0.5.0-9185-gbcc58b9c

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202607122241.qzP3QAXF-lkp@intel.com/

New smatch warnings:
drivers/spi/spi-geni-qcom.c:637 spi_geni_init() warn: missing error code? 'ret'

Old smatch warnings:
drivers/spi/spi-geni-qcom.c:648 spi_geni_init() warn: missing error code? 'ret'

vim +/ret +637 drivers/spi/spi-geni-qcom.c

b59c122484ecb1 Vinod Koul              2021-10-20  616  
561de45f72bd5f Girish Mahadevan        2018-10-03  617  static int spi_geni_init(struct spi_geni_master *mas)
561de45f72bd5f Girish Mahadevan        2018-10-03  618  {
14cea92338a077 Uwe Kleine-König        2024-02-07  619  	struct spi_controller *spi = dev_get_drvdata(mas->dev);
561de45f72bd5f Girish Mahadevan        2018-10-03  620  	struct geni_se *se = &mas->se;
561de45f72bd5f Girish Mahadevan        2018-10-03  621  	unsigned int proto, major, minor, ver;
b59c122484ecb1 Vinod Koul              2021-10-20  622  	u32 spi_tx_cfg, fifo_disable;
b59c122484ecb1 Vinod Koul              2021-10-20  623  	int ret = -ENXIO;
561de45f72bd5f Girish Mahadevan        2018-10-03  624  
d8e9ea989acb54 Praveen Talari          2026-07-10  625  	PM_RUNTIME_ACQUIRE_IF_ENABLED(mas->dev, pm);
d8e9ea989acb54 Praveen Talari          2026-07-10  626  	ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
d8e9ea989acb54 Praveen Talari          2026-07-10  627  	if (ret < 0) {
d8e9ea989acb54 Praveen Talari          2026-07-10  628  		dev_err(mas->dev, "Failed to resume and get %d\n", ret);
d8e9ea989acb54 Praveen Talari          2026-07-10  629  		return ret;
d8e9ea989acb54 Praveen Talari          2026-07-10  630  	}
561de45f72bd5f Girish Mahadevan        2018-10-03  631  
561de45f72bd5f Girish Mahadevan        2018-10-03  632  	proto = geni_se_read_proto(se);
d7f74cc31a89a4 Praveen Talari          2023-07-14  633  
8726bdcef62eac Yang Yingliang          2023-11-28  634  	if (spi->target) {
d7f74cc31a89a4 Praveen Talari          2023-07-14  635  		if (proto != GENI_SE_SPI_SLAVE) {
d7f74cc31a89a4 Praveen Talari          2023-07-14  636  			dev_err(mas->dev, "Invalid proto %d\n", proto);
d8e9ea989acb54 Praveen Talari          2026-07-10 @637  			return ret;
d7f74cc31a89a4 Praveen Talari          2023-07-14  638  		}
d7f74cc31a89a4 Praveen Talari          2023-07-14  639  		spi_slv_setup(mas);
99cf351ee1c46b Viken Dadhaniya         2025-09-11  640  	} else if (proto == GENI_SE_INVALID_PROTO) {
99cf351ee1c46b Viken Dadhaniya         2025-09-11  641  		ret = geni_load_se_firmware(se, GENI_SE_SPI);
99cf351ee1c46b Viken Dadhaniya         2025-09-11  642  		if (ret) {
99cf351ee1c46b Viken Dadhaniya         2025-09-11  643  			dev_err(mas->dev, "spi master firmware load failed ret: %d\n", ret);
d8e9ea989acb54 Praveen Talari          2026-07-10  644  			return ret;
99cf351ee1c46b Viken Dadhaniya         2025-09-11  645  		}
d7f74cc31a89a4 Praveen Talari          2023-07-14  646  	} else if (proto != GENI_SE_SPI) {
561de45f72bd5f Girish Mahadevan        2018-10-03  647  		dev_err(mas->dev, "Invalid proto %d\n", proto);
d8e9ea989acb54 Praveen Talari          2026-07-10  648  		return ret;
561de45f72bd5f Girish Mahadevan        2018-10-03  649  	}
561de45f72bd5f Girish Mahadevan        2018-10-03  650  	mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
561de45f72bd5f Girish Mahadevan        2018-10-03  651  
561de45f72bd5f Girish Mahadevan        2018-10-03  652  	/* Width of Tx and Rx FIFO is same */
561de45f72bd5f Girish Mahadevan        2018-10-03  653  	mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
561de45f72bd5f Girish Mahadevan        2018-10-03  654  
561de45f72bd5f Girish Mahadevan        2018-10-03  655  	/*
561de45f72bd5f Girish Mahadevan        2018-10-03  656  	 * Hardware programming guide suggests to configure
561de45f72bd5f Girish Mahadevan        2018-10-03  657  	 * RX FIFO RFR level to fifo_depth-2.
561de45f72bd5f Girish Mahadevan        2018-10-03  658  	 */
fc129a43aa2705 Douglas Anderson        2020-09-12  659  	geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
561de45f72bd5f Girish Mahadevan        2018-10-03  660  	/* Transmit an entire FIFO worth of data per IRQ */
561de45f72bd5f Girish Mahadevan        2018-10-03  661  	mas->tx_wm = 1;
561de45f72bd5f Girish Mahadevan        2018-10-03  662  	ver = geni_se_get_qup_hw_version(se);
561de45f72bd5f Girish Mahadevan        2018-10-03  663  	major = GENI_SE_VERSION_MAJOR(ver);
561de45f72bd5f Girish Mahadevan        2018-10-03  664  	minor = GENI_SE_VERSION_MINOR(ver);
561de45f72bd5f Girish Mahadevan        2018-10-03  665  
561de45f72bd5f Girish Mahadevan        2018-10-03  666  	if (major == 1 && minor == 0)
561de45f72bd5f Girish Mahadevan        2018-10-03  667  		mas->oversampling = 2;
561de45f72bd5f Girish Mahadevan        2018-10-03  668  	else
561de45f72bd5f Girish Mahadevan        2018-10-03  669  		mas->oversampling = 1;
561de45f72bd5f Girish Mahadevan        2018-10-03  670  
b59c122484ecb1 Vinod Koul              2021-10-20  671  	fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
b59c122484ecb1 Vinod Koul              2021-10-20  672  	switch (fifo_disable) {
b59c122484ecb1 Vinod Koul              2021-10-20  673  	case 1:
b59c122484ecb1 Vinod Koul              2021-10-20  674  		ret = spi_geni_grab_gpi_chan(mas);
b59c122484ecb1 Vinod Koul              2021-10-20  675  		if (!ret) { /* success case */
b59c122484ecb1 Vinod Koul              2021-10-20  676  			mas->cur_xfer_mode = GENI_GPI_DMA;
b59c122484ecb1 Vinod Koul              2021-10-20  677  			geni_se_select_mode(se, GENI_GPI_DMA);
b59c122484ecb1 Vinod Koul              2021-10-20  678  			dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
b59c122484ecb1 Vinod Koul              2021-10-20  679  			break;
9d7054fb3ac2e8 Neil Armstrong          2023-06-15  680  		} else if (ret == -EPROBE_DEFER) {
d8e9ea989acb54 Praveen Talari          2026-07-10  681  			return ret;
b59c122484ecb1 Vinod Koul              2021-10-20  682  		}
b59c122484ecb1 Vinod Koul              2021-10-20  683  		/*
e5f0dfa78ac773 Vijaya Krishna Nivarthi 2022-12-08  684  		 * in case of failure to get gpi dma channel, we can still do the
b59c122484ecb1 Vinod Koul              2021-10-20  685  		 * FIFO mode, so fallthrough
b59c122484ecb1 Vinod Koul              2021-10-20  686  		 */
b59c122484ecb1 Vinod Koul              2021-10-20  687  		dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
b59c122484ecb1 Vinod Koul              2021-10-20  688  		fallthrough;
b59c122484ecb1 Vinod Koul              2021-10-20  689  
b59c122484ecb1 Vinod Koul              2021-10-20  690  	case 0:
b59c122484ecb1 Vinod Koul              2021-10-20  691  		mas->cur_xfer_mode = GENI_SE_FIFO;
da48dc8c70c20e Douglas Anderson        2020-07-01  692  		geni_se_select_mode(se, GENI_SE_FIFO);
739062a9f1e9a7 Jonathan Marek          2025-11-20  693  		/* setup_fifo_params assumes that these registers start with a zero value */
739062a9f1e9a7 Jonathan Marek          2025-11-20  694  		writel(0, se->base + SE_SPI_LOOPBACK);
739062a9f1e9a7 Jonathan Marek          2025-11-20  695  		writel(0, se->base + SE_SPI_DEMUX_SEL);
739062a9f1e9a7 Jonathan Marek          2025-11-20  696  		writel(0, se->base + SE_SPI_CPHA);
739062a9f1e9a7 Jonathan Marek          2025-11-20  697  		writel(0, se->base + SE_SPI_CPOL);
739062a9f1e9a7 Jonathan Marek          2025-11-20  698  		writel(0, se->base + SE_SPI_DEMUX_OUTPUT_INV);
b59c122484ecb1 Vinod Koul              2021-10-20  699  		ret = 0;
b59c122484ecb1 Vinod Koul              2021-10-20  700  		break;
b59c122484ecb1 Vinod Koul              2021-10-20  701  	}
da48dc8c70c20e Douglas Anderson        2020-07-01  702  
b99181cdf9fa02 Jonathan Marek          2025-11-20  703  	/* We never control CS manually */
8726bdcef62eac Yang Yingliang          2023-11-28  704  	if (!spi->target) {
14ac4e049dc118 Douglas Anderson        2020-09-12  705  		spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
14ac4e049dc118 Douglas Anderson        2020-09-12  706  		spi_tx_cfg &= ~CS_TOGGLE;
14ac4e049dc118 Douglas Anderson        2020-09-12  707  		writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
d7f74cc31a89a4 Praveen Talari          2023-07-14  708  	}
14ac4e049dc118 Douglas Anderson        2020-09-12  709  
b59c122484ecb1 Vinod Koul              2021-10-20  710  	return ret;
561de45f72bd5f Girish Mahadevan        2018-10-03  711  }
561de45f72bd5f Girish Mahadevan        2018-10-03  712  

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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2026-07-12 15:35 [linux-next:master 5449/5655] drivers/spi/spi-geni-qcom.c:637 spi_geni_init() warn: missing error code? 'ret' kernel test robot
2026-07-13  8:02 ` Dan Carpenter

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