From: sashiko-bot@kernel.org
To: "Chaitanya Kumar Borah" <chaitanya.kumar.borah@intel.com>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [CI v4 14/14] drm/i915/color: Add color pipeline support for SDR planes
Date: Mon, 13 Jul 2026 05:59:43 +0000 [thread overview]
Message-ID: <20260713055943.B1A991F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260713051516.4087420-15-chaitanya.kumar.borah@intel.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Pre-existing issues:
- [High] Missing NULL check for kasprintf() return value in _intel_color_pipeline_plane_init() leads to a deterministic NULL pointer dereference.
- [High] If a color operation initialization fails early, the cleanup path unconditionally calls drm_colorop_cleanup on a partially initialized object, triggering a NULL pointer dereference.
--
--- Patch [14]: [CI v4 14/14] drm/i915/color: Add color pipeline support for SDR planes ---
commit 6fb2b458fe3e54b8772eb125265bd378c4f8ec9e
Author: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
drm/i915/color: Add color pipeline support for SDR planes
This commit exposes the SDR plane color pipeline to user-space by
removing the HDR plane restriction during initialization.
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 136b9378ca484..a99b6eb204488 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -188,17 +188,11 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en
>
> int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe)
> {
> - struct drm_device *dev = plane->dev;
> - struct intel_display *display = to_intel_display(dev);
> struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES] = {};
> int len = 0;
> int ret = 0;
> int i;
>
> - /* Currently expose pipeline only for HDR planes */
> - if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
> - return 0;
> -
> /* Add pipeline consisting of transfer functions */
> ret = _intel_color_pipeline_plane_init(plane, &pipelines[len], pipe);
[Severity: High]
This is a pre-existing issue, but does _intel_color_pipeline_plane_init()
lack a check for kasprintf() allocation failures?
If memory allocation fails during plane initialization, kasprintf()
returns a NULL pointer:
_intel_color_pipeline_plane_init()
list->name = kasprintf(GFP_KERNEL, ...);
return 0;
The function then returns success (0) even though list->name is NULL.
This NULL pointer is propagated up through
drm_plane_create_color_pipeline_property(), and eventually passed to
drm_property_add_enum(), which does an unconditional strlen():
drm_property_add_enum()
if (WARN_ON(strlen(name) >= DRM_PROP_NAME_LEN))
Would it be safer to check for a NULL return from kasprintf() and return
an error code like -ENOMEM?
[Severity: High]
This is also a pre-existing issue, but if a colorop fails to initialize
during the pipeline plane setup, can it cause a NULL pointer dereference
during cleanup?
If an error occurs early in intel_color_pipeline_plane_add_colorop()
(for example, if drm_mode_object_add() fails to allocate an ID), the
cleanup path unconditionally invokes intel_colorop_destroy():
intel_color_pipeline_plane_add_colorop()
...
cleanup:
intel_colorop_destroy(&colorop->base);
This calls into drm_colorop_cleanup() with a partially initialized object
where colorop->dev is still NULL, leading to a dereference:
drm_colorop_cleanup()
struct drm_device *dev = colorop->dev;
struct drm_mode_config *config = &dev->mode_config;
...
list_del(&colorop->head);
Since colorop->dev is NULL, &dev->mode_config will trigger a dereference,
and list_del() will be called on a zeroed list_head. Could this error path
be reached if there is resource exhaustion during plane initialization?
> if (ret)
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260713051516.4087420-1-chaitanya.kumar.borah@intel.com?part=14
next prev parent reply other threads:[~2026-07-13 5:59 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-13 5:15 [CI v4 00/14] drm/i915/color: Enable SDR plane color pipeline Chaitanya Kumar Borah
2026-07-13 5:15 ` [CI v4 01/14] drm/colorop: Add DRM_COLOROP_FIXED_MATRIX Chaitanya Kumar Borah
2026-07-13 5:48 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 02/14] drm/i915/color: Add CSC on SDR plane color pipeline Chaitanya Kumar Borah
2026-07-13 6:01 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 03/14] drm/i915/display: extract glk_plane_color_ctl_input_csc helper Chaitanya Kumar Borah
2026-07-13 5:15 ` [CI v4 04/14] drm/i915/display: simplify glk_plane_color_ctl_input_csc Chaitanya Kumar Borah
2026-07-13 5:15 ` [CI v4 05/14] drm/i915/display: Track CSC mode in intel plane state Chaitanya Kumar Borah
2026-07-13 5:59 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 06/14] drm/i915/display: Program input CSC on SDR planes Chaitanya Kumar Borah
2026-07-13 6:01 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 07/14] drm/i915/color: Add YCbCr limited-to-full range color block support Chaitanya Kumar Borah
2026-07-13 5:55 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 08/14] drm/i915/color: Add YUV range correction to SDR plane pipeline Chaitanya Kumar Borah
2026-07-13 5:55 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 09/14] drm/i915/color: Add support for 1D LUT in SDR planes Chaitanya Kumar Borah
2026-07-13 5:56 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 10/14] drm/i915/color: Extract HDR pre-CSC LUT programming to helper function Chaitanya Kumar Borah
2026-07-13 5:15 ` [CI v4 11/14] drm/i915/color: Program Pre-CSC registers for SDR Chaitanya Kumar Borah
2026-07-13 5:15 ` [CI v4 12/14] drm/i915/color: Extract HDR post-CSC LUT programming to helper function Chaitanya Kumar Borah
2026-07-13 5:15 ` [CI v4 13/14] drm/i915/color: Program Plane Post CSC registers for SDR planes Chaitanya Kumar Borah
2026-07-13 6:05 ` sashiko-bot
2026-07-13 5:15 ` [CI v4 14/14] drm/i915/color: Add color pipeline support " Chaitanya Kumar Borah
2026-07-13 5:59 ` sashiko-bot [this message]
2026-07-13 5:50 ` ✓ CI.KUnit: success for drm/i915/color: Enable SDR plane color pipeline (rev5) Patchwork
2026-07-13 6:34 ` ✓ Xe.CI.BAT: " Patchwork
2026-07-13 6:51 ` ✓ i915.CI.BAT: " Patchwork
2026-07-13 8:29 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-07-13 10:24 ` ✗ i915.CI.Full: " Patchwork
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