Re: [CI v4 13/14] drm/i915/color: Program Plane Post CSC registers for SDR planes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The newly added SDR plane color pipeline functionality is inaccessible to userspace due to an early return in the pipeline initialization function, rendering the feature incomplete and the newly added programming functions as dead code.
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--- Patch [13]: [CI v4 13/14] drm/i915/color: Program Plane Post CSC registers for SDR planes ---
commit 2ccaf3515c1ab87e0ae3d1f70b7f38f7f0aa3375
Author: Pranay Samala <pranay.samala@intel.com>

drm/i915/color: Program Plane Post CSC registers for SDR planes

This commit implements plane post-CSC LUT support for SDR planes in the
Intel display driver.

> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 3600469795565..be2e1d8ce0e6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
[ ... ]
> @@ -4082,6 +4082,45 @@ xelpd_load_hdr_post_csc_lut(struct intel_display *display,
>  	intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);
>  }
>  
> +static void
> +xelpd_load_sdr_post_csc_lut(struct intel_display *display,
> +			    struct intel_dsb *dsb,
> +			    enum pipe pipe,
> +			    enum plane_id plane,
> +			    const struct drm_color_lut32 *post_csc_lut)
> +{
[Severity: Medium]
Will this newly added function ever be executed?

Looking at intel_color_pipeline_plane_init() in
drivers/gpu/drm/i915/display/intel_color_pipeline.c, there is an early return
that prevents initialization for non-HDR planes:

	/* Currently expose pipeline only for HDR planes */
	if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
		return 0;

Because this check remains, the color pipeline properties are never attached
to SDR planes. This means plane_state->hw.gamma_lut will always be NULL for
these planes, making this new hardware programming function effectively dead
code.

Does the check in intel_color_pipeline_plane_init() need to be updated to
expose this new functionality to userspace?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260713051516.4087420-1-chaitanya.kumar.borah@intel.com?part=13