* [PATCH i-g-t 0/2] benchmarks/gem_wsim: explicit VM create/assign + LR mode
@ 2026-07-14 15:12 Marcin Bernatowicz
2026-07-14 15:12 ` [PATCH i-g-t 1/2] benchmarks/gem_wsim: add explicit VM create/assign steps Marcin Bernatowicz
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Marcin Bernatowicz @ 2026-07-14 15:12 UTC (permalink / raw)
To: igt-dev; +Cc: adam.miszczak, lukasz.laguna, tvrtko.ursulin, Marcin Bernatowicz
This series extends gem_wsim VM management for Xe.
Patch 1 adds explicit VM create/assign steps in workload descriptors:
V.N to create VM N and v.N.M to bind context M to VM N.
Patch 2 adds c.N to enable compute/LR mode on selected VMs.
README is updated with syntax and VM usage examples.
Marcin Bernatowicz (2):
benchmarks/gem_wsim: add explicit VM create/assign steps
benchmarks/gem_wsim: add compute/LR mode support for Xe VMs
benchmarks/gem_wsim.c | 310 ++++++++++++++++++++++++++++++++++++-----
benchmarks/wsim/README | 32 +++++
2 files changed, 311 insertions(+), 31 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH i-g-t 1/2] benchmarks/gem_wsim: add explicit VM create/assign steps 2026-07-14 15:12 [PATCH i-g-t 0/2] benchmarks/gem_wsim: explicit VM create/assign + LR mode Marcin Bernatowicz @ 2026-07-14 15:12 ` Marcin Bernatowicz 2026-07-14 15:12 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: add compute/LR mode support for Xe VMs Marcin Bernatowicz ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Marcin Bernatowicz @ 2026-07-14 15:12 UTC (permalink / raw) To: igt-dev; +Cc: adam.miszczak, lukasz.laguna, tvrtko.ursulin, Marcin Bernatowicz Add explicit VM management to workload descriptors so Xe runs can model VM topology directly. Introduce two new descriptor steps: - V.N create VM id N (1-based) - v.N.M assign VM N to context M Implementation details: - Add VM_CREATE and CTX_VM step types and vm_id storage in w_step. - Parse V/v syntax with validation and clear error messages. - Add allocate_vms() pre-scan to size and allocate vm_list from V steps. - Update xe_prepare_contexts() to support explicit VM mode: - create all explicit VMs - default contexts to VM 0 - apply per-context VM assignments from v steps - retain implicit single-VM fallback when no V steps are present - Make get_vm() use per-context VM linkage. Documentation: - Add VM management step documentation into benchmarks/wsim/README. This keeps i915 behavior unchanged while enabling explicit VM topology control for Xe workloads. Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> Cc: Adam Miszczak <adam.miszczak@linux.intel.com> Cc: Lukasz Laguna <lukasz.laguna@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> --- benchmarks/gem_wsim.c | 143 +++++++++++++++++++++++++++++++++++++---- benchmarks/wsim/README | 19 ++++++ 2 files changed, 150 insertions(+), 12 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 8be44d0c8..b3c46772f 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -130,6 +130,8 @@ enum w_type { TERMINATE, SSEU, WORKINGSET, + VM_CREATE, + CTX_VM, }; struct dep_entry { @@ -210,6 +212,7 @@ struct w_step { struct bond bond; int sseu; struct working_set working_set; + int vm_id; }; /* Implementation details */ @@ -241,6 +244,7 @@ struct w_step { struct vm { uint32_t id; + bool declared; bool compute_mode; uint64_t ahnd; }; @@ -1240,6 +1244,55 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur, step.type = WORKINGSET; goto add_step; + } else if (!strcmp(field, "V")) { + /* + * V.N - create VM with id N (xe only, ignored on i915) + * VM ids are 1-based in the descriptor. + */ + field = strtok_r(fstart, ".", &fctx); + check_arg(!field, "Missing VM id at step %u!\n", + nr_steps); + tmp = atoi(field); + check_arg(tmp <= 0, "Invalid VM id at step %u!\n", + nr_steps); + step.vm_id = tmp; + step.type = VM_CREATE; + goto add_step; + } else if (!strcmp(field, "v")) { + /* + * v.N.M - assign VM N to ctx M + * (xe only, ignored on i915) + */ + unsigned int nr = 0; + int vm = 0, ctx_id = 0; + + while ((field = strtok_r(fstart, ".", &fctx))) { + fstart = NULL; + tmp = atoi(field); + if (nr == 0) { + check_arg(tmp <= 0, + "Invalid VM id at step %u!\n", + nr_steps); + vm = tmp; + } else if (nr == 1) { + check_arg(tmp <= 0, + "Invalid ctx id at step %u!\n", + nr_steps); + ctx_id = tmp; + } else { + check_arg(1, + "Too many fields in v step at step %u!\n", + nr_steps); + } + nr++; + } + check_arg(nr != 2, + "v step requires VM id and ctx id at step %u!\n", + nr_steps); + step.vm_id = vm; + step.context = ctx_id; + step.type = CTX_VM; + goto add_step; } if (!field) { @@ -1665,6 +1718,14 @@ xe_get_eq(struct workload *wrk, const struct w_step *w) static struct vm * get_vm(struct workload *wrk, const struct w_step *w) { + struct ctx *ctx = __get_ctx(wrk, w); + + /* If the ctx has been linked to an explicit VM, use it; otherwise + * fall back to the implicit single vm_list[0]. + */ + if (ctx->vm) + return ctx->vm; + return wrk->vm_list; } @@ -2087,6 +2148,33 @@ static void xe_exec_queue_create_(struct ctx *ctx, struct xe_exec_queue *eq) eq->id = create.exec_queue_id; } +static void allocate_vms(struct workload *wrk) +{ + int max_vm = 0; + struct w_step *w; + + /* + * Slot 0 is always the implicit/default VM. Descriptor VM ids are + * 1-based and map directly to vm_list[N] for explicit V.N steps. + */ + for_each_w_step(w, wrk) { + if (w->type != VM_CREATE) + continue; + if (w->vm_id > max_vm) + max_vm = w->vm_id; + } + + wrk->nr_vms = max_vm + 1; + wrk->vm_list = calloc(wrk->nr_vms, sizeof(*wrk->vm_list)); + igt_assert(wrk->vm_list); + + for_each_w_step(w, wrk) { + if (w->type == VM_CREATE) + /* Mark only explicitly declared VMs; slot 0 stays implicit. */ + wrk->vm_list[w->vm_id].declared = true; + } +} + static void allocate_contexts(unsigned int id, struct workload *wrk) { int max_ctx = -1; @@ -2094,13 +2182,19 @@ static void allocate_contexts(unsigned int id, struct workload *wrk) /* * Pre-scan workload steps to allocate context list storage. + * Skip VM management steps whose context field is unused. */ for_each_w_step(w, wrk) { - int ctx = w->context + 1; + int ctx; int delta; w->wrk = wrk; + if (w->type == VM_CREATE) + continue; + + ctx = w->context + 1; + if (ctx <= max_ctx) continue; @@ -2333,18 +2427,38 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk) struct ctx *ctx; unsigned int i; - /* shortcut, create one vm */ - wrk->nr_vms = 1; - wrk->vm_list = calloc(wrk->nr_vms, sizeof(struct vm)); - igt_assert(wrk->vm_list); - wrk->vm_list->compute_mode = false; - xe_vm_create_(wrk->vm_list); - wrk->vm_list->ahnd = intel_allocator_open(fd, wrk->vm_list->id, - INTEL_ALLOCATOR_RELOC); + /* Slot 0 is the implicit/default VM. */ + xe_vm_create_(&wrk->vm_list[0]); + wrk->vm_list[0].ahnd = intel_allocator_open(fd, wrk->vm_list[0].id, + INTEL_ALLOCATOR_RELOC); + + for (i = 1; i < wrk->nr_vms; i++) { + if (!wrk->vm_list[i].declared) + continue; + + xe_vm_create_(&wrk->vm_list[i]); + wrk->vm_list[i].ahnd = + intel_allocator_open(fd, wrk->vm_list[i].id, + INTEL_ALLOCATOR_RELOC); + } + + /* + * Process CTX_VM steps to link each ctx to an explicit VM. Contexts + * without a v.N.M mapping remain on the implicit VM in slot 0. + */ + __for_each_ctx(ctx, wrk, ctx_idx) + ctx->vm = &wrk->vm_list[0]; + + for_each_w_step(w, wrk) { + if (w->type != CTX_VM) + continue; + igt_assert_lt((unsigned int)w->vm_id, wrk->nr_vms); + igt_assert(wrk->vm_list[w->vm_id].declared); + igt_assert_lt((unsigned int)w->context, wrk->nr_ctxs); + wrk->ctx_list[w->context].vm = &wrk->vm_list[w->vm_id]; + } __for_each_ctx(ctx, wrk, ctx_idx) { - /* link with vm */ - ctx->vm = wrk->vm_list; for_each_w_step(w, wrk) { if (w->context != ctx_idx) continue; @@ -2537,6 +2651,9 @@ static int prepare_workload(unsigned int id, struct workload *wrk) allocate_contexts(id, wrk); + if (is_xe) + allocate_vms(wrk); + if (is_xe) ret = xe_prepare_contexts(id, wrk); else @@ -2857,7 +2974,9 @@ static void *run_workload(void *data) w->type == ENGINE_MAP || w->type == LOAD_BALANCE || w->type == BOND || - w->type == WORKINGSET) { + w->type == WORKINGSET || + w->type == VM_CREATE || + w->type == CTX_VM) { /* No action for these at execution time. */ continue; } diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index e43813335..909c1f039 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -11,6 +11,8 @@ P|S|X.<uint>.<int> d|p|s|t|q|a|T.<int>,... b.<uint>.<str>[|<str>].<str> w|W.<uint>.<str>[/<str>]... +V.<uint> +v.<uint>.<uint> f For duration a range can be given from which a random value will be picked @@ -39,6 +41,11 @@ Additional workload steps are also supported: 'W' - Shared working set. 'X' - Context preemption control. +VM management steps (Xe: active; i915: ignored): + + 'V' - Create VM with id N (V.N, VM ids are 1-based). + 'v' - Assign VM N to context/queue M (v.N.M). + Engine ids: DEFAULT, RCS, BCS, VCS, VCS1, VCS2, VECS Example (leading spaces must not be present in the actual file): @@ -88,6 +95,18 @@ Batch durations can also be specified as infinite by using the '*' in the duration field. Such batches must be ended by the terminate command ('T') otherwise they will cause a GPU hang to be reported. +VM Example: + + V.1 + M.1.VCS + v.1.1 + B.1 + 1.VCS.1000.0.0 + +Creates VM 1, configures context 1 with a VCS engine map, assigns context 1 +to VM 1, enables load balancing for context 1, and runs a single 1ms VCS +batch. + Xe and i915 differences ------------------------ -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH i-g-t 2/2] benchmarks/gem_wsim: add compute/LR mode support for Xe VMs 2026-07-14 15:12 [PATCH i-g-t 0/2] benchmarks/gem_wsim: explicit VM create/assign + LR mode Marcin Bernatowicz 2026-07-14 15:12 ` [PATCH i-g-t 1/2] benchmarks/gem_wsim: add explicit VM create/assign steps Marcin Bernatowicz @ 2026-07-14 15:12 ` Marcin Bernatowicz 2026-07-14 20:26 ` ✗ Xe.CI.BAT: failure for benchmarks/gem_wsim: explicit VM create/assign + LR mode Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Marcin Bernatowicz @ 2026-07-14 15:12 UTC (permalink / raw) To: igt-dev; +Cc: adam.miszczak, lukasz.laguna, tvrtko.ursulin, Marcin Bernatowicz Introduce new descriptor step: 'c' - Enable compute/LR mode for VM N (c.N). Example: gem_wsim -w "V.1,c.1,v.1.1,1.BCS.100.0.0,1.CCS.8000000.-1.0,1.BCS.100.-1.1" 8.009s elapsed (0.125 workloads/s) Creates VM 1, enables compute/LR mode on it, assigns context 1 to the VM, then runs BCS and CCS work with cross-step dependencies (8s CCS depends on the first BCS step, and the final BCS step depends on the CCS step). Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> Cc: Adam Miszczak <adam.miszczak@linux.intel.com> Cc: Lukasz Laguna <lukasz.laguna@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> --- benchmarks/gem_wsim.c | 171 ++++++++++++++++++++++++++++++++++++----- benchmarks/wsim/README | 17 +++- 2 files changed, 165 insertions(+), 23 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index b3c46772f..d6638bcdf 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -132,6 +132,7 @@ enum w_type { WORKINGSET, VM_CREATE, CTX_VM, + VM_COMPUTE_MODE, }; struct dep_entry { @@ -246,6 +247,7 @@ struct vm { uint32_t id; bool declared; bool compute_mode; + uint32_t bind_exec_queue; uint64_t ahnd; }; @@ -323,6 +325,7 @@ static unsigned int master_prng; static int verbose = 1; static int fd; static bool is_xe; +static const uint64_t user_fence_value = 0xdeadbeefdeadbeefull; static struct drm_i915_gem_context_param_sseu device_sseu = { .slice_mask = -1 /* Force read on first use. */ }; @@ -334,10 +337,18 @@ static struct drm_i915_gem_context_param_sseu device_sseu = { static void w_step_sync(struct w_step *w) { - if (is_xe) - igt_assert(syncobj_wait(fd, &w->xe.syncs[0].handle, 1, INT64_MAX, 0, NULL)); - else + if (is_xe) { + if (w->xe.syncs[0].type == DRM_XE_SYNC_TYPE_USER_FENCE) { + xe_wait_ufence(fd, &w->xe.data->spin.exec_sync, + w->xe.syncs[0].timeline_value, 0, + INT64_MAX); + } else { + igt_assert(syncobj_wait(fd, &w->xe.syncs[0].handle, 1, + INT64_MAX, 0, NULL)); + } + } else { gem_sync(fd, w->i915.obj[0].handle); + } } static int read_timestamp_frequency(int i915) @@ -1293,6 +1304,20 @@ parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur, step.context = ctx_id; step.type = CTX_VM; goto add_step; + } else if (!strcmp(field, "c")) { + /* + * c.N - enable compute/LR mode on VM N + * (xe only, ignored on i915) + */ + field = strtok_r(fstart, ".", &fctx); + check_arg(!field, + "Missing VM id at step %u!\n", nr_steps); + tmp = atoi(field); + check_arg(tmp <= 0, + "Invalid VM id at step %u!\n", nr_steps); + step.vm_id = tmp; + step.type = VM_COMPUTE_MODE; + goto add_step; } if (!field) { @@ -1855,10 +1880,27 @@ xe_alloc_step_batch(struct workload *wrk, struct w_step *w) vram_if_possible(fd, eq->hwe_list[0].gt_id), DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM); w->xe.data = xe_bo_map(fd, w->bb_handle, w->bb_size); + w->xe.data->spin.exec_sync = 0; + w->xe.data->vm_sync = 0; w->xe.exec.address = intel_allocator_alloc_with_strategy(vm->ahnd, w->bb_handle, w->bb_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH); - xe_vm_bind_sync(fd, vm->id, w->bb_handle, 0, w->xe.exec.address, w->bb_size); + if (vm->compute_mode) { + struct drm_xe_sync sync = { + .type = DRM_XE_SYNC_TYPE_USER_FENCE, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + .addr = to_user_pointer(&w->xe.data->vm_sync), + .timeline_value = user_fence_value, + }; + + xe_vm_bind_async(fd, vm->id, vm->bind_exec_queue, w->bb_handle, 0, + w->xe.exec.address, w->bb_size, &sync, 1); + xe_wait_ufence(fd, &w->xe.data->vm_sync, user_fence_value, + vm->bind_exec_queue, 10 * NSEC_PER_SEC); + w->xe.data->vm_sync = 0; + } else { + xe_vm_bind_sync(fd, vm->id, w->bb_handle, 0, w->xe.exec.address, w->bb_size); + } w->duration.requested_ticks = xe_spin_nsec_to_ticks(fd, eq->hwe_list[0].gt_id, 1000LL * get_duration(wrk, w)); xe_spin_init_opts(&w->xe.data->spin, @@ -1875,8 +1917,15 @@ xe_alloc_step_batch(struct workload *wrk, struct w_step *w) igt_assert(dep_idx >= 0 && dep_idx < w->idx); igt_assert(wrk->steps[dep_idx].type == BATCH); + igt_assert(wrk->steps[dep_idx].xe.syncs); - w->xe.exec.num_syncs++; + /* + * USER_FENCE is valid as an out-fence in LR mode, but cannot be + * consumed as an in-fence in xe_exec. Those deps are resolved in + * userspace before submission. + */ + if (wrk->steps[dep_idx].xe.syncs[0].type != DRM_XE_SYNC_TYPE_USER_FENCE) + w->xe.exec.num_syncs++; } for_each_dep(dep, w->fence_deps) { int dep_idx = w->idx + dep->target; @@ -1884,34 +1933,70 @@ xe_alloc_step_batch(struct workload *wrk, struct w_step *w) igt_assert(dep_idx >= 0 && dep_idx < w->idx); igt_assert(wrk->steps[dep_idx].type == SW_FENCE || wrk->steps[dep_idx].type == BATCH); + igt_assert(wrk->steps[dep_idx].xe.syncs); - w->xe.exec.num_syncs++; + if (wrk->steps[dep_idx].xe.syncs[0].type != DRM_XE_SYNC_TYPE_USER_FENCE) + w->xe.exec.num_syncs++; } w->xe.syncs = calloc(w->xe.exec.num_syncs, sizeof(*w->xe.syncs)); /* fill syncs */ i = 0; /* out fence */ - w->xe.syncs[i].handle = syncobj_create(fd, 0); - w->xe.syncs[i].type = DRM_XE_SYNC_TYPE_SYNCOBJ; - w->xe.syncs[i++].flags = DRM_XE_SYNC_FLAG_SIGNAL; + if (vm->compute_mode) { + w->xe.syncs[i].type = DRM_XE_SYNC_TYPE_USER_FENCE; + w->xe.syncs[i].flags = DRM_XE_SYNC_FLAG_SIGNAL; + w->xe.syncs[i].addr = w->xe.exec.address + offsetof(struct xe_spin, exec_sync); + w->xe.syncs[i++].timeline_value = user_fence_value; + } else { + w->xe.syncs[i].handle = syncobj_create(fd, 0); + w->xe.syncs[i].type = DRM_XE_SYNC_TYPE_SYNCOBJ; + w->xe.syncs[i++].flags = DRM_XE_SYNC_FLAG_SIGNAL; + } /* in fence(s) */ for_each_dep(dep, w->data_deps) { int dep_idx = w->idx + dep->target; - igt_assert(wrk->steps[dep_idx].xe.syncs && wrk->steps[dep_idx].xe.syncs[0].handle); - w->xe.syncs[i].handle = wrk->steps[dep_idx].xe.syncs[0].handle; - w->xe.syncs[i++].type = DRM_XE_SYNC_TYPE_SYNCOBJ; + igt_assert(wrk->steps[dep_idx].xe.syncs); + if (wrk->steps[dep_idx].xe.syncs[0].type == DRM_XE_SYNC_TYPE_USER_FENCE) + continue; + w->xe.syncs[i] = wrk->steps[dep_idx].xe.syncs[0]; + w->xe.syncs[i++].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL; } for_each_dep(dep, w->fence_deps) { int dep_idx = w->idx + dep->target; - igt_assert(wrk->steps[dep_idx].xe.syncs && wrk->steps[dep_idx].xe.syncs[0].handle); - w->xe.syncs[i].handle = wrk->steps[dep_idx].xe.syncs[0].handle; - w->xe.syncs[i++].type = DRM_XE_SYNC_TYPE_SYNCOBJ; + igt_assert(wrk->steps[dep_idx].xe.syncs); + if (wrk->steps[dep_idx].xe.syncs[0].type == DRM_XE_SYNC_TYPE_USER_FENCE) + continue; + w->xe.syncs[i] = wrk->steps[dep_idx].xe.syncs[0]; + w->xe.syncs[i++].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL; } w->xe.exec.syncs = to_user_pointer(w->xe.syncs); } +static void xe_sync_user_fence_deps(struct workload *wrk, struct w_step *w) +{ + struct dep_entry *dep; + + for_each_dep(dep, w->data_deps) { + int dep_idx = w->idx + dep->target; + + igt_assert(dep_idx >= 0 && dep_idx < w->idx); + igt_assert(wrk->steps[dep_idx].xe.syncs); + if (wrk->steps[dep_idx].xe.syncs[0].type == DRM_XE_SYNC_TYPE_USER_FENCE) + w_step_sync(&wrk->steps[dep_idx]); + } + + for_each_dep(dep, w->fence_deps) { + int dep_idx = w->idx + dep->target; + + igt_assert(dep_idx >= 0 && dep_idx < w->idx); + igt_assert(wrk->steps[dep_idx].xe.syncs); + if (wrk->steps[dep_idx].xe.syncs[0].type == DRM_XE_SYNC_TYPE_USER_FENCE) + w_step_sync(&wrk->steps[dep_idx]); + } +} + static bool set_priority(uint32_t ctx_id, int prio) { struct drm_i915_gem_context_param param = { @@ -2190,7 +2275,7 @@ static void allocate_contexts(unsigned int id, struct workload *wrk) w->wrk = wrk; - if (w->type == VM_CREATE) + if (w->type == VM_CREATE || w->type == VM_COMPUTE_MODE) continue; ctx = w->context + 1; @@ -2427,6 +2512,14 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk) struct ctx *ctx; unsigned int i; + for_each_w_step(w, wrk) { + if (w->type == VM_COMPUTE_MODE) { + igt_assert_lt((unsigned int)w->vm_id, wrk->nr_vms); + igt_assert(wrk->vm_list[w->vm_id].declared); + wrk->vm_list[w->vm_id].compute_mode = true; + } + } + /* Slot 0 is the implicit/default VM. */ xe_vm_create_(&wrk->vm_list[0]); wrk->vm_list[0].ahnd = intel_allocator_open(fd, wrk->vm_list[0].id, @@ -2437,6 +2530,9 @@ static int xe_prepare_contexts(unsigned int id, struct workload *wrk) continue; xe_vm_create_(&wrk->vm_list[i]); + if (wrk->vm_list[i].compute_mode) + wrk->vm_list[i].bind_exec_queue = + xe_bind_exec_queue_create(fd, wrk->vm_list[i].id, 0); wrk->vm_list[i].ahnd = intel_allocator_open(fd, wrk->vm_list[i].id, INTEL_ALLOCATOR_RELOC); @@ -2767,11 +2863,22 @@ static void w_sync_to(struct workload *wrk, struct w_step *w, int target) static void do_xe_exec(struct workload *wrk, struct w_step *w) { struct xe_exec_queue *eq = xe_get_eq(wrk, w); + struct vm *vm = get_vm(wrk, w); igt_assert(w->emit_fence <= 0); if (w->emit_fence == -1) syncobj_reset(fd, &w->xe.syncs[0].handle, 1); + /* + * LR mode reuses the same user-fence location for completion. + * Re-arm it before every submit so waiters do not observe the + * previous iteration's signaled value. + */ + if (vm->compute_mode) + w->xe.data->spin.exec_sync = 0; + + xe_sync_user_fence_deps(wrk, w); + /* update duration if random */ if (w->duration.max != w->duration.min) { w->duration.requested_ticks = xe_spin_nsec_to_ticks(fd, eq->hwe_list[0].gt_id, @@ -2976,7 +3083,8 @@ static void *run_workload(void *data) w->type == BOND || w->type == WORKINGSET || w->type == VM_CREATE || - w->type == CTX_VM) { + w->type == CTX_VM || + w->type == VM_COMPUTE_MODE) { /* No action for these at execution time. */ continue; } @@ -3066,14 +3174,35 @@ static void *run_workload(void *data) for_each_w_step(w, wrk) { if (w->type == BATCH) { w_step_sync(w); - syncobj_destroy(fd, w->xe.syncs[0].handle); + if (w->xe.syncs[0].type == DRM_XE_SYNC_TYPE_SYNCOBJ) + syncobj_destroy(fd, w->xe.syncs[0].handle); free(w->xe.syncs); - xe_vm_unbind_sync(fd, get_vm(wrk, w)->id, 0, w->xe.exec.address, - w->bb_size); + if (get_vm(wrk, w)->compute_mode) { + struct vm *vm = get_vm(wrk, w); + struct drm_xe_sync sync = { + .type = DRM_XE_SYNC_TYPE_USER_FENCE, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + .addr = to_user_pointer(&w->xe.data->vm_sync), + .timeline_value = user_fence_value, + }; + + xe_vm_unbind_async(fd, vm->id, vm->bind_exec_queue, + 0, w->xe.exec.address, w->bb_size, + &sync, 1); + xe_wait_ufence(fd, &w->xe.data->vm_sync, + user_fence_value, + vm->bind_exec_queue, + 10 * NSEC_PER_SEC); + w->xe.data->vm_sync = 0; + } else { + xe_vm_unbind_sync(fd, get_vm(wrk, w)->id, 0, + w->xe.exec.address, w->bb_size); + } gem_munmap(w->xe.data, w->bb_size); gem_close(fd, w->bb_handle); } else if (w->type == SW_FENCE) { - syncobj_destroy(fd, w->xe.syncs[0].handle); + if (w->xe.syncs[0].type == DRM_XE_SYNC_TYPE_SYNCOBJ) + syncobj_destroy(fd, w->xe.syncs[0].handle); free(w->xe.syncs); } } diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 909c1f039..7c180cfb5 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -11,7 +11,7 @@ P|S|X.<uint>.<int> d|p|s|t|q|a|T.<int>,... b.<uint>.<str>[|<str>].<str> w|W.<uint>.<str>[/<str>]... -V.<uint> +V|c.<uint> v.<uint>.<uint> f @@ -45,6 +45,7 @@ VM management steps (Xe: active; i915: ignored): 'V' - Create VM with id N (V.N, VM ids are 1-based). 'v' - Assign VM N to context/queue M (v.N.M). + 'c' - Enable compute/LR mode for VM N (c.N). Engine ids: DEFAULT, RCS, BCS, VCS, VCS1, VCS2, VECS @@ -95,7 +96,7 @@ Batch durations can also be specified as infinite by using the '*' in the duration field. Such batches must be ended by the terminate command ('T') otherwise they will cause a GPU hang to be reported. -VM Example: +VM Examples: V.1 M.1.VCS @@ -107,6 +108,18 @@ Creates VM 1, configures context 1 with a VCS engine map, assigns context 1 to VM 1, enables load balancing for context 1, and runs a single 1ms VCS batch. + V.1 + c.1 + v.1.1 + v.1.2 + 1.BCS.5000.0.0 + 2.CCS.7000000.-1.0 + 1.BCS.5000.-1.1 + +Creates VM 1, enables compute/LR mode on it, assigns contexts 1 and 2 to the +same VM, then runs BCS and CCS work with cross-step dependencies (CCS depends +on the first BCS step, and the final BCS step depends on the CCS step). + Xe and i915 differences ------------------------ -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Xe.CI.BAT: failure for benchmarks/gem_wsim: explicit VM create/assign + LR mode 2026-07-14 15:12 [PATCH i-g-t 0/2] benchmarks/gem_wsim: explicit VM create/assign + LR mode Marcin Bernatowicz 2026-07-14 15:12 ` [PATCH i-g-t 1/2] benchmarks/gem_wsim: add explicit VM create/assign steps Marcin Bernatowicz 2026-07-14 15:12 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: add compute/LR mode support for Xe VMs Marcin Bernatowicz @ 2026-07-14 20:26 ` Patchwork 2026-07-14 20:39 ` ✗ i915.CI.BAT: " Patchwork 2026-07-15 4:17 ` ✗ Xe.CI.FULL: " Patchwork 4 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2026-07-14 20:26 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 4033 bytes --] == Series Details == Series: benchmarks/gem_wsim: explicit VM create/assign + LR mode URL : https://patchwork.freedesktop.org/series/170422/ State : failure == Summary == CI Bug Log - changes from XEIGT_9006_BAT -> XEIGTPW_15527_BAT ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with XEIGTPW_15527_BAT absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_15527_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 12) ------------------------------ Additional (1): bat-bmg-2 Missing (1): bat-bmg-vm Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_15527_BAT: ### IGT changes ### #### Possible regressions #### * igt@xe_module_load@load: - bat-ptl-2: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-ptl-2/igt@xe_module_load@load.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-ptl-2/igt@xe_module_load@load.html - bat-wcl-1: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-wcl-1/igt@xe_module_load@load.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-wcl-1/igt@xe_module_load@load.html - bat-ptl-1: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-ptl-1/igt@xe_module_load@load.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-ptl-1/igt@xe_module_load@load.html - bat-wcl-2: [PASS][7] -> [ABORT][8] [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-wcl-2/igt@xe_module_load@load.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-wcl-2/igt@xe_module_load@load.html - bat-lnl-1: [PASS][9] -> [ABORT][10] [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-lnl-1/igt@xe_module_load@load.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-lnl-1/igt@xe_module_load@load.html - bat-bmg-2: NOTRUN -> [ABORT][11] [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-bmg-2/igt@xe_module_load@load.html - bat-bmg-3: [PASS][12] -> [ABORT][13] [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-bmg-3/igt@xe_module_load@load.html [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-bmg-3/igt@xe_module_load@load.html - bat-bmg-1: [PASS][14] -> [ABORT][15] [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-bmg-1/igt@xe_module_load@load.html [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-bmg-1/igt@xe_module_load@load.html - bat-adlp-7: [PASS][16] -> [ABORT][17] [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-adlp-7/igt@xe_module_load@load.html [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-adlp-7/igt@xe_module_load@load.html - bat-lnl-2: [PASS][18] -> [ABORT][19] [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/bat-lnl-2/igt@xe_module_load@load.html [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/bat-lnl-2/igt@xe_module_load@load.html Build changes ------------- * IGT: IGT_9006 -> IGTPW_15527 * Linux: xe-5397-4df02bb6acd1307de4de001699112cbdaf5afdfc -> xe-5402-9cf91140eff27765d402aedeea89505d52db121e IGTPW_15527: 15527 IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-5397-4df02bb6acd1307de4de001699112cbdaf5afdfc: 4df02bb6acd1307de4de001699112cbdaf5afdfc xe-5402-9cf91140eff27765d402aedeea89505d52db121e: 9cf91140eff27765d402aedeea89505d52db121e == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/index.html [-- Attachment #2: Type: text/html, Size: 4686 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ i915.CI.BAT: failure for benchmarks/gem_wsim: explicit VM create/assign + LR mode 2026-07-14 15:12 [PATCH i-g-t 0/2] benchmarks/gem_wsim: explicit VM create/assign + LR mode Marcin Bernatowicz ` (2 preceding siblings ...) 2026-07-14 20:26 ` ✗ Xe.CI.BAT: failure for benchmarks/gem_wsim: explicit VM create/assign + LR mode Patchwork @ 2026-07-14 20:39 ` Patchwork 2026-07-15 4:17 ` ✗ Xe.CI.FULL: " Patchwork 4 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2026-07-14 20:39 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 11695 bytes --] == Series Details == Series: benchmarks/gem_wsim: explicit VM create/assign + LR mode URL : https://patchwork.freedesktop.org/series/170422/ State : failure == Summary == CI Bug Log - changes from IGT_9006 -> IGTPW_15527 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_15527 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_15527, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/index.html Participating hosts (42 -> 40) ------------------------------ Missing (2): bat-dg2-13 fi-snb-2520m Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_15527: ### IGT changes ### #### Possible regressions #### * igt@i915_module_load@load: - fi-ilk-650: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-ilk-650/igt@i915_module_load@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-ilk-650/igt@i915_module_load@load.html - fi-bsw-n3050: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-bsw-n3050/igt@i915_module_load@load.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-bsw-n3050/igt@i915_module_load@load.html - bat-adlp-6: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-adlp-6/igt@i915_module_load@load.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-adlp-6/igt@i915_module_load@load.html - bat-arlh-2: [PASS][7] -> [ABORT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-arlh-2/igt@i915_module_load@load.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-arlh-2/igt@i915_module_load@load.html - fi-rkl-11600: [PASS][9] -> [ABORT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-rkl-11600/igt@i915_module_load@load.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-rkl-11600/igt@i915_module_load@load.html - fi-skl-6600u: [PASS][11] -> [ABORT][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-skl-6600u/igt@i915_module_load@load.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-skl-6600u/igt@i915_module_load@load.html - bat-arlh-3: [PASS][13] -> [ABORT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-arlh-3/igt@i915_module_load@load.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-arlh-3/igt@i915_module_load@load.html - fi-pnv-d510: [PASS][15] -> [ABORT][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-pnv-d510/igt@i915_module_load@load.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-pnv-d510/igt@i915_module_load@load.html - bat-dg1-7: [PASS][17] -> [ABORT][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-dg1-7/igt@i915_module_load@load.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-dg1-7/igt@i915_module_load@load.html - fi-glk-j4005: [PASS][19] -> [ABORT][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-glk-j4005/igt@i915_module_load@load.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-glk-j4005/igt@i915_module_load@load.html - bat-adlp-9: [PASS][21] -> [ABORT][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-adlp-9/igt@i915_module_load@load.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-adlp-9/igt@i915_module_load@load.html - bat-twl-2: [PASS][23] -> [ABORT][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-twl-2/igt@i915_module_load@load.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-twl-2/igt@i915_module_load@load.html - bat-rpls-4: [PASS][25] -> [ABORT][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-rpls-4/igt@i915_module_load@load.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-rpls-4/igt@i915_module_load@load.html - fi-kbl-7567u: [PASS][27] -> [ABORT][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-kbl-7567u/igt@i915_module_load@load.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-kbl-7567u/igt@i915_module_load@load.html - fi-cfl-8700k: [PASS][29] -> [ABORT][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-cfl-8700k/igt@i915_module_load@load.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-cfl-8700k/igt@i915_module_load@load.html - bat-twl-1: [PASS][31] -> [ABORT][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-twl-1/igt@i915_module_load@load.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-twl-1/igt@i915_module_load@load.html - fi-kbl-8809g: [PASS][33] -> [ABORT][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-kbl-8809g/igt@i915_module_load@load.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-kbl-8809g/igt@i915_module_load@load.html - bat-jsl-5: [PASS][35] -> [ABORT][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-jsl-5/igt@i915_module_load@load.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-jsl-5/igt@i915_module_load@load.html - bat-apl-1: [PASS][37] -> [ABORT][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-apl-1/igt@i915_module_load@load.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-apl-1/igt@i915_module_load@load.html - bat-dg2-14: [PASS][39] -> [ABORT][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-dg2-14/igt@i915_module_load@load.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-dg2-14/igt@i915_module_load@load.html - fi-elk-e7500: [PASS][41] -> [ABORT][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-elk-e7500/igt@i915_module_load@load.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-elk-e7500/igt@i915_module_load@load.html - fi-bsw-nick: [PASS][43] -> [ABORT][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-bsw-nick/igt@i915_module_load@load.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-bsw-nick/igt@i915_module_load@load.html - bat-kbl-2: [PASS][45] -> [ABORT][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-kbl-2/igt@i915_module_load@load.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-kbl-2/igt@i915_module_load@load.html - bat-arls-5: [PASS][47] -> [ABORT][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-arls-5/igt@i915_module_load@load.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-arls-5/igt@i915_module_load@load.html - bat-rplp-1: [PASS][49] -> [ABORT][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-rplp-1/igt@i915_module_load@load.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-rplp-1/igt@i915_module_load@load.html - fi-tgl-1115g4: [PASS][51] -> [ABORT][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-tgl-1115g4/igt@i915_module_load@load.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-tgl-1115g4/igt@i915_module_load@load.html - fi-cfl-guc: [PASS][53] -> [ABORT][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-cfl-guc/igt@i915_module_load@load.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-cfl-guc/igt@i915_module_load@load.html - bat-mtlp-9: [PASS][55] -> [ABORT][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-mtlp-9/igt@i915_module_load@load.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-mtlp-9/igt@i915_module_load@load.html - bat-arls-6: [PASS][57] -> [ABORT][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-arls-6/igt@i915_module_load@load.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-arls-6/igt@i915_module_load@load.html - bat-dg2-9: [PASS][59] -> [ABORT][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-dg2-9/igt@i915_module_load@load.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-dg2-9/igt@i915_module_load@load.html - fi-kbl-x1275: [PASS][61] -> [ABORT][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-kbl-x1275/igt@i915_module_load@load.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-kbl-x1275/igt@i915_module_load@load.html - bat-adlp-11: [PASS][63] -> [ABORT][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-adlp-11/igt@i915_module_load@load.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-adlp-11/igt@i915_module_load@load.html - fi-hsw-4770: [PASS][65] -> [ABORT][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-hsw-4770/igt@i915_module_load@load.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-hsw-4770/igt@i915_module_load@load.html - fi-cfl-8109u: [PASS][67] -> [ABORT][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-cfl-8109u/igt@i915_module_load@load.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-cfl-8109u/igt@i915_module_load@load.html - fi-ivb-3770: [PASS][69] -> [ABORT][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/fi-ivb-3770/igt@i915_module_load@load.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/fi-ivb-3770/igt@i915_module_load@load.html - bat-mtlp-8: [PASS][71] -> [ABORT][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-mtlp-8/igt@i915_module_load@load.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-mtlp-8/igt@i915_module_load@load.html - bat-dg1-6: [PASS][73] -> [ABORT][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-dg1-6/igt@i915_module_load@load.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-dg1-6/igt@i915_module_load@load.html - bat-dg2-8: [PASS][75] -> [ABORT][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-dg2-8/igt@i915_module_load@load.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-dg2-8/igt@i915_module_load@load.html - bat-adls-6: [PASS][77] -> [ABORT][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_9006/bat-adls-6/igt@i915_module_load@load.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/bat-adls-6/igt@i915_module_load@load.html Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_9006 -> IGTPW_15527 * Linux: CI_DRM_18816 -> CI_DRM_18821 CI-20190529: 20190529 CI_DRM_18816: 4df02bb6acd1307de4de001699112cbdaf5afdfc @ git://anongit.freedesktop.org/gfx-ci/linux CI_DRM_18821: 9cf91140eff27765d402aedeea89505d52db121e @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_15527: 15527 IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_15527/index.html [-- Attachment #2: Type: text/html, Size: 12478 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Xe.CI.FULL: failure for benchmarks/gem_wsim: explicit VM create/assign + LR mode 2026-07-14 15:12 [PATCH i-g-t 0/2] benchmarks/gem_wsim: explicit VM create/assign + LR mode Marcin Bernatowicz ` (3 preceding siblings ...) 2026-07-14 20:39 ` ✗ i915.CI.BAT: " Patchwork @ 2026-07-15 4:17 ` Patchwork 4 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2026-07-15 4:17 UTC (permalink / raw) To: Marcin Bernatowicz; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 13905 bytes --] == Series Details == Series: benchmarks/gem_wsim: explicit VM create/assign + LR mode URL : https://patchwork.freedesktop.org/series/170422/ State : failure == Summary == CI Bug Log - changes from XEIGT_9006_FULL -> XEIGTPW_15527_FULL ==================================================== Summary ------- **WARNING** Minor unknown changes coming with XEIGTPW_15527_FULL need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in XEIGTPW_15527_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (2 -> 2) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in XEIGTPW_15527_FULL: ### IGT changes ### #### Warnings #### * igt@xe_module_load@load: - shard-lnl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [SKIP][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([Intel XE#378] / [Intel XE#7405]) -> ([DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [DMESG-WARN][30], [DMESG-WARN][31], [DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50], [DMESG-WARN][51]) [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-2/igt@xe_module_load@load.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-6/igt@xe_module_load@load.html [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-5/igt@xe_module_load@load.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-5/igt@xe_module_load@load.html [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-5/igt@xe_module_load@load.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-6/igt@xe_module_load@load.html [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-6/igt@xe_module_load@load.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-5/igt@xe_module_load@load.html [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-3/igt@xe_module_load@load.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-3/igt@xe_module_load@load.html [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-3/igt@xe_module_load@load.html [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-2/igt@xe_module_load@load.html [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-2/igt@xe_module_load@load.html [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-4/igt@xe_module_load@load.html [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-7/igt@xe_module_load@load.html [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-7/igt@xe_module_load@load.html [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-7/igt@xe_module_load@load.html [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-8/igt@xe_module_load@load.html [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-8/igt@xe_module_load@load.html [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-8/igt@xe_module_load@load.html [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-4/igt@xe_module_load@load.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-4/igt@xe_module_load@load.html [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-1/igt@xe_module_load@load.html [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-1/igt@xe_module_load@load.html [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-1/igt@xe_module_load@load.html [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-lnl-4/igt@xe_module_load@load.html [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-1/igt@xe_module_load@load.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-1/igt@xe_module_load@load.html [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-1/igt@xe_module_load@load.html [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-8/igt@xe_module_load@load.html [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-8/igt@xe_module_load@load.html [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-8/igt@xe_module_load@load.html [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-4/igt@xe_module_load@load.html [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-4/igt@xe_module_load@load.html [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-4/igt@xe_module_load@load.html [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-6/igt@xe_module_load@load.html [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-6/igt@xe_module_load@load.html [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-6/igt@xe_module_load@load.html [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-3/igt@xe_module_load@load.html [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-3/igt@xe_module_load@load.html [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-3/igt@xe_module_load@load.html [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-2/igt@xe_module_load@load.html [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-2/igt@xe_module_load@load.html [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-2/igt@xe_module_load@load.html [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-7/igt@xe_module_load@load.html [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-7/igt@xe_module_load@load.html [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-7/igt@xe_module_load@load.html [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-5/igt@xe_module_load@load.html [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-5/igt@xe_module_load@load.html [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-5/igt@xe_module_load@load.html [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-lnl-5/igt@xe_module_load@load.html - shard-bmg: ([PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [SKIP][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77]) ([Intel XE#2457] / [Intel XE#7405]) -> ([DMESG-WARN][78], [DMESG-WARN][79], [DMESG-WARN][80], [DMESG-WARN][81], [DMESG-WARN][82], [DMESG-WARN][83], [DMESG-WARN][84], [DMESG-WARN][85], [DMESG-WARN][86], [DMESG-WARN][87], [DMESG-WARN][88], [DMESG-WARN][89], [DMESG-WARN][90], [DMESG-WARN][91], [DMESG-WARN][92], [DMESG-WARN][93], [DMESG-WARN][94], [DMESG-WARN][95], [DMESG-WARN][96], [DMESG-WARN][97], [DMESG-WARN][98], [DMESG-WARN][99], [DMESG-WARN][100], [DMESG-WARN][101], [DMESG-WARN][102]) [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-4/igt@xe_module_load@load.html [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-4/igt@xe_module_load@load.html [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-4/igt@xe_module_load@load.html [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-2/igt@xe_module_load@load.html [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-2/igt@xe_module_load@load.html [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-2/igt@xe_module_load@load.html [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-5/igt@xe_module_load@load.html [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-3/igt@xe_module_load@load.html [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-8/igt@xe_module_load@load.html [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-5/igt@xe_module_load@load.html [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-8/igt@xe_module_load@load.html [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-6/igt@xe_module_load@load.html [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-2/igt@xe_module_load@load.html [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-3/igt@xe_module_load@load.html [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-3/igt@xe_module_load@load.html [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-9/igt@xe_module_load@load.html [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-9/igt@xe_module_load@load.html [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-5/igt@xe_module_load@load.html [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-10/igt@xe_module_load@load.html [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-7/igt@xe_module_load@load.html [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-7/igt@xe_module_load@load.html [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-7/igt@xe_module_load@load.html [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-6/igt@xe_module_load@load.html [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-1/igt@xe_module_load@load.html [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-1/igt@xe_module_load@load.html [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_9006/shard-bmg-10/igt@xe_module_load@load.html [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-4/igt@xe_module_load@load.html [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-4/igt@xe_module_load@load.html [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-4/igt@xe_module_load@load.html [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-8/igt@xe_module_load@load.html [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-8/igt@xe_module_load@load.html [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-10/igt@xe_module_load@load.html [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-10/igt@xe_module_load@load.html [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-10/igt@xe_module_load@load.html [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-1/igt@xe_module_load@load.html [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-1/igt@xe_module_load@load.html [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-1/igt@xe_module_load@load.html [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-7/igt@xe_module_load@load.html [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-7/igt@xe_module_load@load.html [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-9/igt@xe_module_load@load.html [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-9/igt@xe_module_load@load.html [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-2/igt@xe_module_load@load.html [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-2/igt@xe_module_load@load.html [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-2/igt@xe_module_load@load.html [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-6/igt@xe_module_load@load.html [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-6/igt@xe_module_load@load.html [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-3/igt@xe_module_load@load.html [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-3/igt@xe_module_load@load.html [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-3/igt@xe_module_load@load.html [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-5/igt@xe_module_load@load.html [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/shard-bmg-5/igt@xe_module_load@load.html [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457 [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378 [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405 Build changes ------------- * IGT: IGT_9006 -> IGTPW_15527 * Linux: xe-5397-4df02bb6acd1307de4de001699112cbdaf5afdfc -> xe-5402-9cf91140eff27765d402aedeea89505d52db121e IGTPW_15527: 15527 IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-5397-4df02bb6acd1307de4de001699112cbdaf5afdfc: 4df02bb6acd1307de4de001699112cbdaf5afdfc xe-5402-9cf91140eff27765d402aedeea89505d52db121e: 9cf91140eff27765d402aedeea89505d52db121e == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_15527/index.html [-- Attachment #2: Type: text/html, Size: 14521 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-07-15 4:18 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-14 15:12 [PATCH i-g-t 0/2] benchmarks/gem_wsim: explicit VM create/assign + LR mode Marcin Bernatowicz 2026-07-14 15:12 ` [PATCH i-g-t 1/2] benchmarks/gem_wsim: add explicit VM create/assign steps Marcin Bernatowicz 2026-07-14 15:12 ` [PATCH i-g-t 2/2] benchmarks/gem_wsim: add compute/LR mode support for Xe VMs Marcin Bernatowicz 2026-07-14 20:26 ` ✗ Xe.CI.BAT: failure for benchmarks/gem_wsim: explicit VM create/assign + LR mode Patchwork 2026-07-14 20:39 ` ✗ i915.CI.BAT: " Patchwork 2026-07-15 4:17 ` ✗ Xe.CI.FULL: " Patchwork
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.