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From: sashiko-bot@kernel.org
To: "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v6 07/11] drm/mediatek: mtk_dsi: Add support for MT8189
Date: Wed, 15 Jul 2026 14:40:11 +0000	[thread overview]
Message-ID: <20260715144012.A17D21F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260715135703.46540-8-angelogioacchino.delregno@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] DSI link rate calculations ignore DSC compression, breaking high-resolution support.
--

--- Patch [7]: [PATCH v6 07/11] drm/mediatek: mtk_dsi: Add support for MT8189 ---
commit d3eecfadd8fa60f56b5a609d3b36986202e453a5
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

drm/mediatek: mtk_dsi: Add support for MT8189

This commit adds support for the DSI IP in the MT8189 SoC, which supports a
higher link rate of 2.5Gbps. It introduces a max_link_rate_mbps parameter to
the driver data and updates the mode_valid callback to use this value
instead of a hardcoded 1.5Gbps limit.

> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index e1803f1b9c587..95f7d94bdad3b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c

[ ... ]

> @@ -926,7 +928,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
>  	}
>  	bit_per_pixel = ret;
>  
> -	dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
> +	dsi->data_rate = DIV_ROUND_UP_ULL((u64)dsi->vm.pixelclock * bit_per_pixel,
>  					  dsi->lanes);

[Severity: High]
This is a pre-existing issue, but does this calculation break DSC-enabled
panels? When DSC is used, bit_per_pixel appears to be the uncompressed
bpp. Using the uncompressed bpp instead of the compressed bpp for the
link rate calculation will configure the hs_clk much higher than intended,
which might exceed hardware limits or cause FIFO underflows.

>  	ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);

[ ... ]

> @@ -1101,13 +1103,21 @@ mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
>  			  const struct drm_display_mode *mode)
>  {
>  	struct mtk_dsi *dsi = bridge_to_dsi(bridge);
> +	const struct mtk_dsi_driver_data *data = dsi->driver_data;
> +	u64 wanted_link_rate, max_link_rate;
>  	int bpp;
>  
>  	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
>  	if (bpp < 0)
>  		return MODE_ERROR;
>  
> -	if (mode->clock * bpp / dsi->lanes > 1500000)
> +	wanted_link_rate = mode->clock;
> +	wanted_link_rate *= bpp;
> +	max_link_rate = data->max_link_rate_mbps;
> +	max_link_rate *= dsi->lanes;
> +	max_link_rate *= KILO;
> +
> +	if (wanted_link_rate > max_link_rate)

[Severity: High]
This is a pre-existing issue, but will wanted_link_rate incorrectly reject
high-resolution compressed modes here? Since wanted_link_rate uses the
uncompressed bpp rather than the compressed bpp, it looks like high
resolution modes that require DSC to fit within the max_link_rate_mbps
will be erroneously rejected as MODE_CLOCK_HIGH.

>  		return MODE_CLOCK_HIGH;
>  
>  	if (dsi->dsc) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260715135703.46540-1-angelogioacchino.delregno@collabora.com?part=7

  reply	other threads:[~2026-07-15 14:40 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-15 13:56 [PATCH v6 00/11] drm/mediatek: Add DSC, WDMA, MT8189/96 DSI support AngeloGioacchino Del Regno
2026-07-15 13:56 ` [PATCH v6 01/11] dt-bindings: display: mediatek: dsc: Add MT8196 compatible AngeloGioacchino Del Regno
2026-07-15 13:56 ` [PATCH v6 02/11] drm/mediatek: Implement Display Stream Compression support AngeloGioacchino Del Regno
2026-07-15 14:09   ` sashiko-bot
2026-07-15 13:56 ` [PATCH v6 03/11] dt-bindings: display: mediatek: dsi: Document MT8189 and MT8196 AngeloGioacchino Del Regno
2026-07-15 13:56 ` [PATCH v6 04/11] drm/mediatek: mtk_dsi: Cleanup encoder if reset fails during bind AngeloGioacchino Del Regno
2026-07-15 14:25   ` sashiko-bot
2026-07-15 13:56 ` [PATCH v6 05/11] drm/mediatek: mtk_dsi: Enable interrupt at component bind time AngeloGioacchino Del Regno
2026-07-15 14:29   ` sashiko-bot
2026-07-15 13:56 ` [PATCH v6 06/11] drm/mediatek: mtk_dsi: Transfer register offsets to per-SoC const AngeloGioacchino Del Regno
2026-07-15 13:56 ` [PATCH v6 07/11] drm/mediatek: mtk_dsi: Add support for MT8189 AngeloGioacchino Del Regno
2026-07-15 14:40   ` sashiko-bot [this message]
2026-07-15 13:57 ` [PATCH v6 08/11] drm/mediatek: mtk_dsi: Add support for MT8196 AngeloGioacchino Del Regno
2026-07-15 14:51   ` sashiko-bot
2026-07-15 13:57 ` [PATCH v6 09/11] drm/mediatek: mtk_dsi: Enable PM Runtime on probe AngeloGioacchino Del Regno
2026-07-15 15:24   ` sashiko-bot
2026-07-15 13:57 ` [PATCH v6 10/11] dt-bindings: display: mediatek: wdma: Add compatibles for more SoCs AngeloGioacchino Del Regno
2026-07-15 13:57 ` [PATCH v6 11/11] drm/mediatek: Add Write DMA (WDMA) Engine for Writeback support AngeloGioacchino Del Regno
2026-07-15 15:24   ` sashiko-bot

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