Re: [PATCH v6 1/6] arm64: dts: qcom: Add device tree for Nord SoC series

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Thermal zones lack a 'critical' trip point and passive cooling is non-functional, disabling thermal safety protections.
- [Medium] QUP wrapper nodes (qupv3_0, qupv3_1, qupv3_2) are missing mandatory 'clocks' and 'clock-names' properties.
--

--- Patch [1]: [PATCH v6 1/6] arm64: dts: qcom: Add device tree for Nord SoC series ---
commit 95c2014f3c2e44a525b136382378e1766eccc72c
Author: Shawn Guo <shengchao.guo@oss.qualcomm.com>

arm64: dts: qcom: Add device tree for Nord SoC series

Add base device tree include (nord.dtsi) for the Nord SoC series
describing the core hardware components.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> new file mode 100644
> index 0000000000000..117bcc2c88377
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -0,0 +1,4605 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "qcom,oryon-1-5";

[Severity: High]
Are these CPU nodes missing the #cooling-cells property?

Without #cooling-cells, passive cooling mitigation cannot function for these
cores when thermal limits are reached.

[ ... ]

> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		dma-ranges = <0 0 0 0 0x10 0>;
> +		ranges = <0 0 0 0 0x10 0>;
> +
> +		qupv3_2: geniqup@8c0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x0 0x008c0000 0x0 0x2000>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			iommus = <&apps_smmu_0 0x15a3 0x0>;
> +			ranges;

[Severity: Medium]
Will the qcom,geni-se-qup driver fail to probe here?

It appears this node (along with qupv3_0 and qupv3_1 below) is missing the
mandatory clocks and clock-names properties. Without the m-ahb and s-ahb
clocks, devm_clk_bulk_get() during probe will return an error, preventing
all child serial interfaces from initializing.

[ ... ]

> +	thermal_zones: thermal-zones {
> +		ddr-0-0-thermal {
> +			polling-delay-passive = <0>;
> +			polling-delay = <0>;
> +			thermal-sensors = <&tsens0 0>;
> +
> +			trips {
> +				trip-point0 {
> +					temperature = <105000>;
> +					hysteresis = <10000>;
> +					type = "passive";
> +				};
> +
> +				trip-point1 {
> +					temperature = <115000>;
> +					hysteresis = <10000>;
> +					type = "passive";
> +				};

[Severity: High]
Should this maximum trip point type be "critical" instead of "passive"?

Since there are no cooling-maps defined in the thermal zones and the CPU
nodes lack #cooling-cells, passive cooling is non-functional. Setting the
highest trip points (e.g., 115C or 125C) across all thermal zones to
passive instead of critical means the kernel will not trigger a forced
emergency shutdown when the hardware overheats, which could lead to
hardware damage.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716142605.2398433-1-shengchao.guo@oss.qualcomm.com?part=1